CN114628248B - Silicon carbide device and preparation method thereof - Google Patents
Silicon carbide device and preparation method thereof Download PDFInfo
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- CN114628248B CN114628248B CN202210526000.XA CN202210526000A CN114628248B CN 114628248 B CN114628248 B CN 114628248B CN 202210526000 A CN202210526000 A CN 202210526000A CN 114628248 B CN114628248 B CN 114628248B
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 124
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 123
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 259
- 238000000034 method Methods 0.000 claims abstract description 119
- 230000008569 process Effects 0.000 claims abstract description 101
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000001259 photo etching Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims description 33
- 238000004519 manufacturing process Methods 0.000 claims description 26
- 230000003647 oxidation Effects 0.000 claims description 25
- 238000007254 oxidation reaction Methods 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 238000005224 laser annealing Methods 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims 4
- 238000000206 photolithography Methods 0.000 abstract description 7
- 239000000463 material Substances 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 7
- 230000004913 activation Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
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- H01L29/42356—Disposition, e.g. buried gate electrode
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Abstract
The invention provides a silicon carbide device and a preparation method thereof, comprising the following steps: providing a base structure comprising, in order: a silicon carbide substrate, a silicon carbide epitaxial layer, a first ion implantation layer of a first conductivity type, and a second ion implantation layer of a second conductivity type; forming a first patterned mask structure on the second ion implantation layer by using a photolithography process; forming a trench in the base structure using the first patterned mask structure; forming a gate structure in the trench; forming a second patterned mask structure on the second ion implantation layer by using the gate structure; forming an opening in the second ion implantation layer by using the second patterned mask structure, wherein the opening exposes a part of the first ion implantation layer; forming a contact structure in the exposed first ion implantation layer by using the opening; and forming a conductive layer connected to the contact structure; the first conductivity type is opposite to the second conductivity type. Therefore, the problem of overlay accuracy difference between two photoetching processes can be avoided.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a silicon carbide device and a preparation method thereof.
Background
A Metal-Oxide-semiconductor field effect transistor (MOSFET) is a field effect transistor that can be widely used in analog circuits and digital circuits. The silicon carbide material metal-oxide semiconductor field effect transistor (SiC MOSFET) has the characteristics of low on-resistance, high switching speed, high temperature resistance and the like, and has great application advantages in the fields of high-voltage frequency conversion, new energy automobiles, rail transit and the like. In order to increase the current density of silicon carbide devices, effective control and shortening of the cell width of the devices is one of the main research directions. When the cell width of the device is shortened, the photoetching alignment process needs to have extremely high precision requirements, and great challenges are brought to process manufacture. In particular, in the existing silicon carbide device manufacturing, the distance between the gate structure and the contact structure is controlled by a two-layer mask (mask), and the overlay accuracy difference exists between the two photolithography processes, so that the problem of poor distance control is often generated.
Disclosure of Invention
The invention aims to provide a silicon carbide device and a preparation method thereof, which are used for solving the problem that the distance between a grid structure and a contact hole in the prior art is controlled by two layers of photomasks and the overlay accuracy is different.
In order to solve the technical problems, the invention provides a preparation method of a silicon carbide device, which comprises the following steps: providing a base structure, the base structure comprising: a silicon carbide substrate, a silicon carbide epitaxial layer on the silicon carbide substrate, a first ion implantation layer of a first conductivity type on the silicon carbide epitaxial layer, and a second ion implantation layer of a second conductivity type on the first ion implantation layer; forming a first patterned mask structure on the second ion implantation layer by using a photoetching process; forming a trench in the base structure using the first patterned mask structure; forming a gate structure in the trench; forming a second patterned mask structure on the second ion implantation layer by utilizing the gate structure; forming an opening in the second ion implantation layer by using the second patterned mask structure, wherein the opening exposes a part of the first ion implantation layer; forming a contact structure in the exposed first ion implantation layer by using the opening; and forming a conductive layer, the conductive layer being connected to the contact structure; wherein the first conductivity type is opposite to the second conductivity type.
Optionally, in the method for manufacturing a silicon carbide device, forming a second patterned mask structure on the second ion implantation layer by using the gate structure includes: etching the first patterned mask structure, forming a first side wall structure on two sides of the grid structure and exposing part of the second ion implantation layer; performing an oxidation process to form a first oxide layer on the surface of the second ion implantation layer and the surface of the gate structure; and etching the first oxide layer to form the second patterned mask structure, wherein the second patterned mask structure comprises the first side wall structure and the rest of the first oxide layer.
Optionally, in the method for manufacturing a silicon carbide device, forming a second patterned mask structure on the second ion implantation layer by using the gate structure includes: removing the first patterned mask structure; forming a second oxide layer, wherein the second oxide layer covers the gate structure and the second ion implantation layer; and etching the second oxide layer to form second side wall structures on two sides of the grid electrode structure, wherein the second side wall structures serve as the second graphical mask structures.
Optionally, in the method for manufacturing a silicon carbide device, after forming an opening in the second ion implantation layer by using the second patterned mask structure, and after exposing a portion of the first ion implantation layer by using the opening, before forming a contact structure in the exposed first ion implantation layer by using the opening, the method for manufacturing a silicon carbide device further includes: performing an oxidation process to form a third oxide layer on the inner wall of the opening, the upper surface of the second ion implantation layer and the surface of the grid structure; and etching to remove the third oxide layer on the surface of the first ion implantation layer.
Optionally, in the method for manufacturing a silicon carbide device, forming a second patterned mask structure on the second ion implantation layer by using the gate structure includes: removing the first patterned mask structure; forming a fourth oxide layer, wherein the fourth oxide layer covers the gate structure and the second ion implantation layer; etching the fourth oxide layer to form a third side wall structure on two sides of the grid structure; performing an oxidation process to form a fifth oxide layer on the surface of the second ion implantation layer and the surface of the gate structure; and etching the fifth oxide layer to form the second patterned mask structure, wherein the second patterned mask structure comprises the third side wall structure and the rest of the fifth oxide layer.
Optionally, in the method for manufacturing a silicon carbide device, the material of the first patterned mask structure is silicon oxide.
Optionally, in the method for manufacturing a silicon carbide device, forming a trench in the substrate structure using the first patterned mask structure includes: and performing an etching process on the substrate structure by taking the first patterned mask structure as a mask to form the groove, wherein the groove extends from the surface of the first patterned mask structure into the silicon carbide epitaxial layer.
Optionally, in the method for manufacturing a silicon carbide device, forming a gate structure in the trench includes: performing an ion implantation process on the bottom of the trench to form a third ion implantation layer of the first conductivity type at the bottom of the trench; forming a dielectric layer, wherein the dielectric layer covers the inner wall of the groove; and filling the polysilicon layer in the groove to form the grid structure.
Optionally, in the method for preparing a silicon carbide device, a ratio of an oxidation rate of the gate structure to an oxidation rate of the second ion implantation layer is between (3:1) and (15:1).
Optionally, in the method for manufacturing a silicon carbide device, forming a contact structure in the exposed first ion implantation layer by using the opening includes: performing an ion implantation process on the first ion implantation layer to form a fourth ion implantation layer; and performing a laser annealing process on the fourth ion implantation layer to form the contact structure.
Optionally, in the method for preparing a silicon carbide device, the process temperature of executing the laser annealing process is between 800 ℃ and 1200 ℃.
The present invention also provides a silicon carbide device comprising: a base structure, the base structure comprising: a silicon carbide substrate, a silicon carbide epitaxial layer on the silicon carbide substrate, a first ion implantation layer of a first conductivity type on the silicon carbide epitaxial layer, and a second ion implantation layer of a second conductivity type on the first ion implantation layer; a gate structure formed in the base structure; a second patterned mask structure formed over the second ion implantation layer; a contact structure formed in the first ion implantation layer on the second patterned mask structure side; and a conductive layer connected to the contact structure; wherein the first conductivity type is opposite to the second conductivity type.
In the silicon carbide device and the preparation method thereof provided by the invention, only one photoetching process is needed in the process of forming the gate structure and the contact structure, specifically, a groove is formed by one photoetching process to form the gate structure in the groove, and then the contact structure is formed by a self-alignment process. Therefore, the problem of overlay accuracy difference between two photoetching processes can be avoided. Further, the contact structure is formed through a self-aligned process, so that the distance between the gate structure and the contact structure is better controlled.
Drawings
Fig. 1 is a flow chart of a method of fabricating a silicon carbide device according to an embodiment of the present invention.
Fig. 2 to 12 are schematic cross-sectional views of structures formed by performing a method of manufacturing a silicon carbide device according to a first embodiment of the present invention.
Fig. 13 to 25 are schematic cross-sectional views of structures formed by performing a method of manufacturing a silicon carbide device according to a second embodiment of the present invention.
Fig. 26 to 38 are schematic cross-sectional views of structures formed by performing a method of manufacturing a silicon carbide device according to a third embodiment of the present invention.
Wherein reference numerals are as follows: 100-base structure; 102-a silicon carbide epitaxial layer; 104-a first ion implantation layer; 106-a second ion implantation layer; 108-a first patterned mask structure; 110-grooves; 112-a third ion implantation layer; 114-a dielectric layer; 116-a polysilicon layer; 118-gate structure; 120-a second patterned mask structure; 122-a first side wall structure; 124-a first oxide layer; 126-opening; 128-contact structures; 130-a conductive layer; 200-a base structure; 202-silicon carbide epitaxial layer; 204-a first ion implantation layer; 206-a second ion implantation layer; 208-a first patterned mask structure; 210-grooves; 212-a third ion implantation layer; 214-a dielectric layer; 216-a polysilicon layer; 218-gate structure; 220-a second patterned mask structure; 222-a second oxide layer; 224-opening; 225-a third oxide layer; 226-contact structures; 228-a conductive layer; 300-a base structure; 302-a silicon carbide epitaxial layer; 304-a first ion implantation layer; 306-a second ion implantation layer; 308-a first patterned mask structure; 310-groove; 312-a third ion implantation layer; 314-a dielectric layer; 316-polysilicon layer; 318-gate structure; 320-a second patterned mask structure; 322-fourth oxide layer; 324-a third side wall structure; 326-a fifth oxide layer; 328-opening; 330-contact structure; 332-conductive layer.
Detailed Description
The silicon carbide device and the preparation method thereof according to the present invention are described in further detail below with reference to the accompanying drawings and specific examples. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Unless defined otherwise herein, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The terms first, second and the like in the description and in the claims, are not used for any order, quantity or importance, but are used for distinguishing between different elements. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "plurality" means two or more. Unless otherwise indicated, the terms "front," "rear," "lower," and/or "upper" and the like are merely for convenience of description and are not limited to one location or one spatial orientation. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
Referring to fig. 1, a flow chart of a method for manufacturing a silicon carbide device according to an embodiment of the invention is shown. As shown in fig. 1, the preparation method of the silicon carbide device includes: step S10: providing a base structure, the base structure comprising: a silicon carbide substrate, a silicon carbide epitaxial layer on the silicon carbide substrate, a first ion implantation layer of a first conductivity type on the silicon carbide epitaxial layer, and a second ion implantation layer of a second conductivity type on the first ion implantation layer; step S11: forming a first patterned mask structure on the second ion implantation layer by using a photoetching process; step S12: forming a trench in the base structure using the first patterned mask structure; step S13: forming a gate structure in the trench; step S14: forming a second patterned mask structure on the second ion implantation layer by utilizing the gate structure; step S15: forming an opening in the second ion implantation layer by using the second patterned mask structure, wherein the opening exposes a part of the first ion implantation layer; step S16: forming a contact structure in the exposed first ion implantation layer by using the opening; step S17: forming a conductive layer, wherein the conductive layer is connected with the contact structure; wherein the first conductivity type is opposite to the second conductivity type.
In the embodiment of the invention, only one photoetching process is needed in the process of forming the gate structure and the contact structure, specifically, a groove is formed by one photoetching process to form the gate structure in the groove, and then the contact structure is formed by a self-alignment process. Therefore, the problem of overlay accuracy difference between two photoetching processes can be avoided. Further, the contact structure is formed through a self-aligned process, so that the distance between the gate structure and the contact structure is better controlled.
[ embodiment one ].
Referring to fig. 2 to 12, schematic cross-sectional views of structures formed by performing a method for fabricating a silicon carbide device according to a first embodiment of the present invention are shown.
As shown in fig. 2, in an embodiment of the present application, a base structure 100 is provided, the base structure 100 comprising: a silicon carbide substrate (not shown), a silicon carbide epitaxial layer 102 on the silicon carbide substrate, a first ion implantation layer 104 of a first conductivity type on the silicon carbide epitaxial layer 102, and a second ion implantation layer 106 of a second conductivity type on the first ion implantation layer 104. With continued reference to fig. 2, in one embodiment of the present application, a silicon carbide substrate (not shown) may be provided; then, an epitaxial process is performed on the silicon carbide substrate, thereby forming the silicon carbide epitaxial layer 102. Then, an ion implantation process is performed on the silicon carbide epitaxial layer 102 to obtain the first ion implantation layer 104, and a P-type ion implantation is performed on the silicon carbide epitaxial layer 102 to obtain the P-type first ion implantation layer 104. Then, an ion implantation process is performed on the first ion implantation layer 104 to obtain the second ion implantation layer 106, and N-type heavy doping is performed on the first ion implantation layer 104, so as to obtain the n+ type second ion implantation layer 106. In other embodiments of the present application, the doping types of the first ion implantation layer 104 and the second ion implantation layer 106 may be opposite.
Next, as shown in fig. 3, a first patterned mask structure 108 is formed on the second ion implantation layer 106 using a photolithography process. Here, the first patterned mask structure 108 is a hard mask layer, and may be a silicon oxide material. Specifically, a silicon oxide layer may be formed on the second ion implantation layer 106; then, an exposure process is performed on the silicon oxide layer by using a mask plate, and in this embodiment, an etching process is performed on the exposed silicon oxide layer to obtain the first patterned mask structure 108. The first patterned mask structure 108 exposes a portion of the second ion implantation layer 106.
Referring to fig. 4, a trench 110 is then formed in the base structure 100 using the first patterned mask structure 108. Specifically, the trench 110 is formed by etching the second ion implantation layer 106, the first ion implantation layer 104, and a portion of the thickness of the silicon carbide epitaxial layer 102. Here, the trench 110 is in communication with an opening in the first patterned mask structure 108, whereby the trench 110 extends from the surface of the first patterned mask structure 108 into the silicon carbide epitaxial layer 102.
In an embodiment of the present application, a gate structure is then formed in the trench 110. Specifically, as shown in fig. 5 and 6, first, an ion implantation process is performed on the bottom of the trench 110 to form a third ion implantation layer 112 of the first conductivity type at the bottom of the trench 110. Here, P-type ion implantation is performed on the bottom of the trench 110 to form a P-type third ion implantation layer 112 at the bottom of the trench 110. Next, a dielectric layer 114 is formed, the dielectric layer 114 covering the inner walls of the trench 110 and extending to cover the surface of the first patterned mask structure 108. The material of the dielectric layer 114 may be the same as that of the first patterned mask structure 108, for example, silicon oxide. A polysilicon layer 116 is formed on the dielectric layer 114, the polysilicon layer 116 filling the trench 110. With continued reference to fig. 6, the polysilicon layer 116 and the dielectric layer 114 on the first patterned mask structure 108 are then removed to form the gate structure 118 in the trench 110. Specifically, the polysilicon layer 116 and the dielectric layer 114 on the first patterned mask structure 108 may be removed by an etching process or a chemical mechanical polishing process.
Here, the silicon carbide epitaxial layer 102 between the first ion implantation layer 104 and the third ion implantation layer 112 may form a depletion region, so that the performance of the formed silicon carbide device may be improved.
As shown in fig. 7 to 9, in the embodiment of the present application, a second patterned mask structure 120 is formed on the second ion implantation layer 106 by using the gate structure 118.
First, referring to fig. 7, the first patterned mask structure 108 is etched, and a first sidewall structure 122 is formed on both sides of the gate structure 118 and exposes a portion of the second ion implantation layer 106. Here, the first patterned mask structure 108 may be etched by a dry etching process with an inclined angle to form inclined first sidewall structures 122 at both sides of the gate structure 118 and expose a portion of the second ion implantation layer 106.
Next, as shown in fig. 8, an oxidation process is performed to form a first oxide layer 124 on the exposed surface of the second ion implantation layer 106 and the surface of the gate structure 118. In the embodiment of the present application, the portions of the gate structure 118 above the surface of the two ion implantation layers 106 are oxidized as part of the first oxide layer 124. Wherein the ratio of the oxidation rate of the gate structure 118 to the oxidation rate of the second ion implantation layer 106 is between (3:1) - (15:1), for example, the ratio of the oxidation rate of the gate structure 118 to the oxidation rate of the second ion implantation layer 106 is 7:1;12:1, etc. Thus, the oxidation rate of the gate structure 118 will be substantially faster than the oxidation rate of the second ion implantation layer 106, such that the thickness of the first oxide layer 124 on the gate structure 118 will be substantially greater than the thickness of the first oxide layer 124 on the second ion implantation layer 106. In the embodiment of the present application, the thickness of the first oxide layer 124 on the gate structure 118 is 3000 a-10000 a, and the thickness of the first oxide layer 124 on the second ion implantation layer 106 is 200 a-2000 a.
As shown in fig. 9, the first oxide layer 124 is then etched to form the second patterned mask structure 120. Specifically, the first oxide layer 124 may be etched by a vertical dry etching process. Here, etching is stopped to expose the second ion implantation layer 106. Because the thickness of the first oxide layer 124 on the second ion implantation layer 106 is relatively thin, a portion of the thickness of the first oxide layer 124 remains on the gate structure 118 when etching to expose the second ion implantation layer 106. The remaining first oxide layer 124 and the first sidewall structure 122 serve as the second patterned mask structure 120. I.e., the first sidewall structure 122 is formed using the gate structure 118 and the first oxide layer 124 is formed with a height difference therein, thereby forming the second patterned mask structure 120.
As shown in fig. 10, an opening 126 is formed in the second ion implantation layer 106 using the second patterned mask structure 120, the opening 126 exposing a portion of the first ion implantation layer 104. Specifically, with the second patterned mask structure 120 as a mask, an etching process is performed on the second ion implantation layer 106 to form the opening 126 in the second ion implantation layer 106, where the opening 126 extends from the surface of the second ion implantation layer 106 to the surface of the first ion implantation layer 104, so as to expose the first ion implantation layer 104.
In an embodiment of the present application, the contact structure 128 is then formed in the exposed first ion implantation layer 104 using the opening 126, as shown in fig. 11. Specifically, an ion implantation process is performed on the first ion implantation layer 104 to form a fourth ion implantation layer (not shown in the figure) of a first conductivity type, where the first conductivity type is P-type. The ion implantation concentration of the fourth ion implantation layer is higher than that of the first ion implantation layer 104 of the first conductivity type, and a fourth ion implantation layer of p+ type is formed therein. Next, a laser annealing process is performed on the fourth ion implantation layer to form the contact structure 128. Preferably, the process temperature for executing the laser annealing process is 800-1200 ℃. The laser annealing process is adopted instead of the conventional high-temperature furnace tube annealing process, so that impurity activation can be realized at a lower temperature, and the quality and reliability of the formed silicon carbide device are improved.
Referring to fig. 12, in the embodiment of the present application, a conductive layer 130 is formed, and the conductive layer 130 is connected to the contact structure 128. Specifically, the conductive layer 130 may be formed by depositing a metal layer.
Accordingly, embodiments of the present application also provide a silicon carbide device, including: a base structure 100, the base structure 100 comprising: a silicon carbide substrate (not shown), a silicon carbide epitaxial layer 102 on the silicon carbide substrate, a first ion implantation layer 104 of a first conductivity type on the silicon carbide epitaxial layer 102, and a second ion implantation layer 106 of a second conductivity type on the first ion implantation layer 104; a gate structure 118 formed in the base structure 100; a second patterned mask structure 120 formed on the second ion implantation layer 106; a contact structure 128 formed in the first ion implantation layer 104 on the second patterned mask structure 120 side; and a conductive layer 130 connected to the contact structure 128; wherein the first conductivity type and the second conductivity type are opposite in conductivity type, i.e., one of the two conductivity types is a P-type conductivity type and the other is an N-type conductivity type.
[ example two ].
Please refer to fig. 13-25, which are schematic cross-sectional views illustrating a structure formed by performing a method for fabricating a silicon carbide device according to a second embodiment of the present invention.
As shown in fig. 13, in an embodiment of the present application, a base structure 200 is provided, the base structure 200 comprising: a silicon carbide substrate (not shown), a silicon carbide epitaxial layer 202 on the silicon carbide substrate, a first ion implantation layer 204 of a first conductivity type on the silicon carbide epitaxial layer 202, and a second ion implantation layer 206 of a second conductivity type on the first ion implantation layer 204. With continued reference to fig. 13, in one embodiment of the present application, a silicon carbide substrate (not shown) may be provided; then, an epitaxial process is performed on the silicon carbide substrate, thereby forming the silicon carbide epitaxial layer 202. Then, an ion implantation process is performed on the silicon carbide epitaxial layer 202 to obtain the first ion implantation layer 204, and a P-type ion implantation is performed on the silicon carbide epitaxial layer 202 to obtain the P-type first ion implantation layer 204. Next, an ion implantation process is performed on the first ion implantation layer 204 to obtain the second ion implantation layer 206, where N-type heavy doping is performed on the first ion implantation layer 204 to obtain an n+ type second ion implantation layer 206. In other embodiments of the present application, the doping types of the first ion implantation layer 204 and the second ion implantation layer 206 may be opposite.
Next, as shown in fig. 14, a first patterned mask structure 208 is formed on the second ion implantation layer 206 using a photolithography process. Here, the first patterned mask structure 208 is a hard mask layer, and may be a silicon oxide material. Specifically, a silicon oxide layer may be formed on the second ion implantation layer 206; then, an exposure process is performed on the silicon oxide layer by using a mask plate, and in this embodiment, an etching process is performed on the exposed silicon oxide layer to obtain the first patterned mask structure 208. The first patterned masking structure 208 exposes a portion of the second ion implantation layer 206.
Referring to fig. 15, a trench 210 is then formed in the base structure 200 using the first patterned mask structure 208. Specifically, the trench 210 is formed by etching the second ion implantation layer 206, the first ion implantation layer 204, and a portion of the thickness of the silicon carbide epitaxial layer 202. Here, the trench 210 communicates with an opening in the first patterned mask structure 208, whereby the trench 210 extends from a surface of the first patterned mask structure 208 into the silicon carbide epitaxial layer 202.
In the embodiment of the present application, a gate structure is then formed in the trench 210. Specifically, as shown in fig. 16 and 17, first, an ion implantation process is performed on the bottom of the trench 210 to form a third ion implantation layer 212 of the first conductivity type at the bottom of the trench 210. Here, P-type ion implantation is performed on the bottom of the trench 210 to form a P-type third ion implantation layer 212 at the bottom of the trench 210. Next, a dielectric layer 214 is formed, the dielectric layer 214 covering the inner walls of the trench 210 and extending over the surface of the first patterned mask structure 208. The material of the dielectric layer 214 may be the same as that of the first patterned mask structure 208, for example, silicon oxide. A polysilicon layer 216 is formed on the dielectric layer 214, the polysilicon layer 216 filling the trench 210. With continued reference to fig. 17, the polysilicon layer 216 and the dielectric layer 214 on the first patterned mask structure 208 are then removed to form the gate structure 218 in the trench 210. Specifically, the polysilicon layer 216 and the dielectric layer 214 on the first patterned mask structure 208 may be removed by an etching process or a chemical mechanical polishing process.
Here, the silicon carbide epitaxial layer 202 between the first ion implantation layer 204 and the third ion implantation layer 212 may form a depletion region, so that the performance of the formed silicon carbide device may be improved.
As shown in fig. 18 to 20, in the embodiment of the present application, a second patterned mask structure 220 is formed on the second ion implantation layer 206 by using the gate structure 218.
Specifically, referring first to fig. 18, the first patterned mask structure 208 is removed, exposing the second ion implantation layer 206.
Next, as shown in fig. 19, a second oxide layer 222 is formed, and the second oxide layer 222 covers the gate structure 218 and the second ion implantation layer 206. Here, the second oxide layer 222 may be formed by a deposition process.
Next, as shown in fig. 20, the second oxide layer 222 is etched to form second sidewall structures on both sides of the gate structure 218, where the second sidewall structures serve as the second patterned mask structures 220. I.e., the second sidewall structures are formed here using the gate structure 218, thereby forming the second patterned mask structure 220. Here, the second oxide layer 222 may be etched by a vertical dry etching process to form the second patterned mask structure 220 having a square shape, thereby enabling better control of the distance between the gate structure 218 and a subsequently formed contact structure.
Next, as shown in fig. 21, an opening 224 is formed in the second ion implantation layer 206 using the second patterned mask structure 220, and the opening 224 exposes a portion of the first ion implantation layer 204. Specifically, with the second patterned mask structure 220 as a mask, an etching process is performed on the second ion implantation layer 206 to form the opening 224 in the second ion implantation layer 206, where the opening 224 extends from the surface of the second ion implantation layer 206 to the surface of the first ion implantation layer 204, so as to expose the first ion implantation layer 204.
As shown in fig. 22, in the embodiment of the present application, an oxidation process is performed to form a third oxide layer 225 on the surface of the first ion implantation layer 204, the side and upper surfaces of the second ion implantation layer 206, and the surface of the gate structure 218, that is, a third oxide layer 225 is formed on the inner wall of the opening 224, the upper surface of the second ion implantation layer 206, and the surface of the gate structure 218. Here, the third oxide layer 225 and the second patterned mask structure 220 (i.e., the second sidewall structure) formed by etching the second oxide layer 222 are both made of silicon oxide and are connected together, which is not further differentiated in fig. 22 to 25 of the present application.
Next, as shown in fig. 23, the third oxide layer 225 on the surface of the first ion implantation layer 204 is etched away to expose the first ion implantation layer 204, and in this embodiment, the third oxide layer 225 on the side of the second ion implantation layer 206 is also removed. Specifically, the third oxide layer 225 on the inner wall of the opening 224 may be removed by a wet or dry etching process. Here, an isotropic etching process may be used to remove the third oxide layer 225 on the inner wall of the opening 224, and a wet etching process or an etching parameter of a dry etching process may be adjusted to remove the third oxide layer 225 on the inner wall of the opening 224. In other embodiments of the present application, only the third oxide layer 225 on the surface of the first ion implantation layer 204 may be removed to expose the first ion implantation layer 204.
In an embodiment of the present application, a contact structure 226 is then formed in the exposed first ion implantation layer 204 using the opening 224, as shown in fig. 24. Specifically, an ion implantation process is performed on the first ion implantation layer 204 to form a fourth ion implantation layer (not shown in the figure) of a first conductivity type, where the first conductivity type is P-type. The ion implantation concentration of the fourth ion implantation layer is higher than that of the first ion implantation layer 204 of the first conductivity type, and a fourth ion implantation layer of p+ type is formed therein. Next, a laser annealing process is performed on the fourth ion implantation layer to form the contact structure 226. Preferably, the process temperature for executing the laser annealing process is 800-1200 ℃. The laser annealing process is adopted instead of the conventional high-temperature furnace tube annealing process, so that impurity activation can be realized at a lower temperature, and the quality and reliability of the formed silicon carbide device are improved.
Referring to fig. 25, in the embodiment of the present application, a conductive layer 228 is formed, and the conductive layer 228 is connected to the contact structure 226. In particular, the conductive layer 228 may be formed by depositing a metal layer.
Accordingly, embodiments of the present application also provide a silicon carbide device, including: a base structure 200, the base structure 200 comprising: a silicon carbide substrate (not shown), a silicon carbide epitaxial layer 202 on the silicon carbide substrate, a first ion implantation layer 204 of a first conductivity type on the silicon carbide epitaxial layer 202, and a second ion implantation layer 206 of a second conductivity type on the first ion implantation layer 204; a gate structure 218 formed in the base structure 200; a second patterned mask structure 220 formed over the second ion implantation layer 206; a contact structure 226 formed in the first ion implantation layer 204 on the second patterned mask structure 220 side; and a conductive layer 228 connected to the contact structure 226; wherein the first conductivity type and the second conductivity type are opposite in conductivity type, i.e., one of the two conductivity types is a P-type conductivity type and the other is an N-type conductivity type.
[ example III ].
Referring to fig. 26 to 38, schematic cross-sectional views of structures formed by performing the method for fabricating a silicon carbide device according to the third embodiment of the present invention are shown.
As shown in fig. 26, in an embodiment of the present application, a base structure 300 is provided, the base structure 300 including: a silicon carbide substrate (not shown), a silicon carbide epitaxial layer 302 on the silicon carbide substrate, a first ion implantation layer 304 of a first conductivity type on the silicon carbide epitaxial layer 302, and a second ion implantation layer 306 of a second conductivity type on the first ion implantation layer 304. With continued reference to fig. 26, in one embodiment of the present application, a silicon carbide substrate (not shown) may be provided; then, an epitaxial process is performed on the silicon carbide substrate, thereby forming the silicon carbide epitaxial layer 302. Then, an ion implantation process is performed on the silicon carbide epitaxial layer 302 to obtain the first ion implantation layer 304, and a P-type ion implantation is performed on the silicon carbide epitaxial layer 302 to obtain the P-type first ion implantation layer 304. Next, an ion implantation process is performed on the first ion implantation layer 304 to obtain the second ion implantation layer 306, where N-type heavy doping is performed on the first ion implantation layer 304 to obtain an n+ type second ion implantation layer 306. In other embodiments of the present application, the doping types of the first ion implantation layer 304 and the second ion implantation layer 306 may be opposite.
Next, as shown in fig. 27, a first patterned mask structure 308 is formed on the second ion implantation layer 306 using a photolithography process. Here, the first patterned mask structure 308 is a hard mask layer, and may be a silicon oxide material. Specifically, a silicon oxide layer may be formed on the second ion implantation layer 306; then, an exposure process is performed on the silicon oxide layer by using a mask plate, and in this embodiment, an etching process is performed on the exposed silicon oxide layer to obtain the first patterned mask structure 308. The first patterned masking structure 308 exposes a portion of the second ion implantation layer 306.
Referring to fig. 28, a trench 310 is then formed in the base structure 300 using the first patterned mask structure 308. Specifically, the trench 310 is formed by etching the second ion implantation layer 306, the first ion implantation layer 304, and a portion of the thickness of the silicon carbide epitaxial layer 302. Here, the trench 310 communicates with an opening in the first patterned mask structure 308, whereby the trench 310 extends from the surface of the first patterned mask structure 308 into the silicon carbide epitaxial layer 302.
In an embodiment of the present application, a gate structure is then formed in the trench 310. Specifically, as shown in fig. 29 and 30, first, an ion implantation process is performed on the bottom of the trench 310 to form a third ion implantation layer 312 of the first conductivity type at the bottom of the trench 310. Here, P-type ion implantation is performed on the bottom of the trench 310 to form a P-type third ion implantation layer 312 at the bottom of the trench 310. Next, a dielectric layer 314 is formed, the dielectric layer 314 covering the inner walls of the trenches 310 and extending over the surface of the first patterned mask structure 308. The material of the dielectric layer 314 may be the same as that of the first patterned mask structure 308, for example, silicon oxide. A polysilicon layer 316 is formed on the dielectric layer 314, the polysilicon layer 316 filling the trench 310. With continued reference to fig. 30, the polysilicon layer 316 and the dielectric layer 314 on the first patterned mask structure 308 are then removed to form the gate structure 318 in the trench 310. Specifically, the polysilicon layer 316 and the dielectric layer 314 on the first patterned mask structure 308 may be removed by an etching process or a chemical mechanical polishing process.
Here, the silicon carbide epitaxial layer 302 between the first ion implantation layer 304 and the third ion implantation layer 312 may form a depletion region, so that the performance of the formed silicon carbide device may be improved.
As shown in fig. 31 to 35, in the embodiment of the present application, a second patterned mask structure 320 is formed on the second ion implantation layer 306 by using the gate structure 318.
Specifically, referring to fig. 31, first, the first patterned mask structure 308 is removed to expose the second ion implantation layer 306.
Next, as shown in fig. 32, a fourth oxide layer 322 is formed, and the fourth oxide layer 322 covers the gate structure 318 and the second ion implantation layer 306. Here, the fourth oxide layer 322 may be formed by a deposition process.
Next, as shown in fig. 33, the fourth oxide layer 322 is etched to form third sidewall structures 324 on both sides of the gate structure 318, where the third sidewall structures 324 expose a portion of the second ion implantation layer 306. Here, the fourth oxide layer 322 may be etched by a vertical dry etching process to form the second patterned mask structure 320 having a square shape, thereby enabling better control of the distance between the gate structure 318 and a subsequently formed contact structure.
Further, as shown in fig. 34, in an embodiment of the present application, an oxidation process is further performed to form a fifth oxide layer 326 on the exposed surface of the second ion implantation layer 306 and the surface of the gate structure 318. In the embodiment of the present application, the portions of the gate structure 318 above the surface of the two ion implantation layers 306 are oxidized as a part of the fifth oxide layer 326. Wherein the ratio of the oxidation rate of the gate structure 318 to the oxidation rate of the second ion implantation layer 306 is between (3:1) - (15:1), for example, the ratio of the oxidation rate of the gate structure 318 to the oxidation rate of the second ion implantation layer 306 is 7:1, 10:1 or 12:1, etc. Thus, the oxidation rate of the gate structure 318 will be substantially faster than the oxidation rate of the second ion implantation layer 306, such that the thickness of the fifth oxide layer 326 on the gate structure 318 will be substantially greater than the thickness of the fifth oxide layer 326 on the second ion implantation layer 306. In the embodiment of the present application, the thickness of the fifth oxide layer 326 on the gate structure 318 is 3000 a-10000 a, and the thickness of the fifth oxide layer 326 on the second ion implantation layer 306 is 200 a-2000 a.
In this embodiment, as shown in fig. 35, the fifth oxide layer 326 is etched to form the second patterned mask structure 320, where the second patterned mask structure 320 includes the third sidewall structure 324 and the remaining fifth oxide layer 326. Specifically, the fifth oxide layer 326 may be etched by a vertical dry etching process. Here, etching is stopped to expose the second ion implantation layer 306. Because the thickness of the fifth oxide layer 326 on the second ion implantation layer 306 is relatively thin, when etching to expose the second ion implantation layer 306, a portion of the thickness of the fifth oxide layer 326 remains on the gate structure 318. The remaining fifth oxide layer 326 and the third sidewall structure 324 serve as the second patterned mask structure 320. I.e., the third sidewall structure 324 is formed using the gate structure 318 and the fifth oxide layer 326 is formed with a height difference, thereby forming the second patterned mask structure 320.
Next, as shown in fig. 36, an opening 328 is formed in the second ion implantation layer 306 using the second patterned mask structure 320, and the opening 328 exposes a portion of the first ion implantation layer 304. Specifically, an etching process is performed on the second ion implantation layer 306 using the second patterned mask structure 320 as a mask, so as to form the opening 328 in the second ion implantation layer 306, where the opening 328 extends from the surface of the second ion implantation layer 306 to the surface of the first ion implantation layer 304, so as to expose the first ion implantation layer 304.
In an embodiment of the present application, a contact structure 330 is then formed in the exposed first ion implantation layer 304 using the opening 328, as shown in fig. 37. Specifically, an ion implantation process is performed on the first ion implantation layer 304 to form a fourth ion implantation layer (not shown) of a first conductivity type, where the first conductivity type is P-type. The ion implantation concentration of the fourth ion implantation layer is higher than that of the first ion implantation layer 304 of the first conductivity type, and a fourth ion implantation layer of p+ type is formed therein. Next, a laser annealing process is performed on the fourth ion implantation layer to form the contact structure 330. Preferably, the process temperature for executing the laser annealing process is 800-1200 ℃. The laser annealing process is adopted instead of the conventional high-temperature furnace tube annealing process, so that impurity activation can be realized at a lower temperature, and the quality and reliability of the formed silicon carbide device are improved.
Referring to fig. 38, in the embodiment of the present application, a conductive layer 332 is formed, and the conductive layer 332 is connected to the contact structure 330. Specifically, the conductive layer 332 may be formed by depositing a metal layer.
Accordingly, embodiments of the present application also provide a silicon carbide device, including: a base structure 300, the base structure 300 comprising: a silicon carbide substrate (not shown), a silicon carbide epitaxial layer 302 on the silicon carbide substrate, a first ion implantation layer 304 of a first conductivity type on the silicon carbide epitaxial layer 302, and a second ion implantation layer 306 of a second conductivity type on the first ion implantation layer 304; a gate structure 318 formed in the base structure 300; a second patterned mask structure 320 formed on the second ion implantation layer 306; a contact structure 330 formed in the first ion implantation layer 304 on the second patterned mask structure 320 side; and a conductive layer 332 connected to the contact structure 330; wherein the first conductivity type and the second conductivity type are opposite in conductivity type, i.e., one of the two conductivity types is a P-type conductivity type and the other is an N-type conductivity type.
In summary, in the silicon carbide device and the method for manufacturing the same provided in the embodiments of the present application, only one photolithography process is needed in the process of forming the gate structure and the contact structure, specifically, a trench is formed by one photolithography process to form the gate structure in the trench, and then the contact structure is formed by a self-aligned process. Therefore, the problem of overlay accuracy difference between two photoetching processes can be avoided. Further, the contact structure is formed through a self-aligned process, so that the distance between the gate structure and the contact structure is better controlled.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (11)
1. The preparation method of the silicon carbide device is characterized by comprising the following steps of:
providing a base structure, the base structure comprising: a silicon carbide substrate, a silicon carbide epitaxial layer on the silicon carbide substrate, a first ion implantation layer of a first conductivity type on the silicon carbide epitaxial layer, and a second ion implantation layer of a second conductivity type on the first ion implantation layer;
forming a first patterned mask structure on the second ion implantation layer by using a photoetching process;
forming a trench in the base structure using the first patterned mask structure;
forming a gate structure in the trench;
forming side wall structures on two sides of the grid structure, and forming a second graphical mask structure on the second ion implantation layer by utilizing the grid structure and the side wall structures;
forming an opening in the second ion implantation layer by using the second patterned mask structure, wherein the opening exposes a part of the first ion implantation layer;
Forming a contact structure in the exposed first ion implantation layer by using the opening; and
forming a conductive layer, wherein the conductive layer is connected with the contact structure;
wherein the first conductivity type is opposite to the second conductivity type.
2. The method of manufacturing a silicon carbide device of claim 1, wherein forming a second patterned mask structure on the second ion implantation layer using the gate structure comprises:
etching the first patterned mask structure, forming a first side wall structure on two sides of the grid structure and exposing part of the second ion implantation layer;
performing an oxidation process to form a first oxide layer on the surface of the second ion implantation layer and the surface of the gate structure; and
and etching the first oxide layer to form a second patterned mask structure, wherein the second patterned mask structure comprises the first side wall structure and the rest of the first oxide layer.
3. The method of manufacturing a silicon carbide device of claim 1, wherein forming a second patterned mask structure on the second ion implantation layer using the gate structure comprises:
Removing the first patterned mask structure;
forming a second oxide layer, wherein the second oxide layer covers the gate structure and the second ion implantation layer; and
and etching the second oxide layer to form second side wall structures on two sides of the grid electrode structure, wherein the second side wall structures serve as the second graphical mask structures.
4. The method of manufacturing a silicon carbide device of claim 3, wherein after forming an opening in the second ion implanted layer using the second patterned mask structure, the opening exposing a portion of the first ion implanted layer, the method of manufacturing a silicon carbide device further comprising, prior to forming a contact structure in the exposed first ion implanted layer using the opening:
performing an oxidation process to form a third oxide layer on the inner wall of the opening, the upper surface of the second ion implantation layer and the surface of the grid structure; and
and etching to remove the third oxide layer on the surface of the first ion implantation layer.
5. The method of manufacturing a silicon carbide device of claim 1, wherein forming a second patterned mask structure on the second ion implantation layer using the gate structure comprises:
Removing the first patterned mask structure;
forming a fourth oxide layer, wherein the fourth oxide layer covers the gate structure and the second ion implantation layer;
etching the fourth oxide layer to form a third side wall structure on two sides of the grid structure;
performing an oxidation process to form a fifth oxide layer on the surface of the second ion implantation layer and the surface of the gate structure; and
and etching the fifth oxide layer to form a second patterned mask structure, wherein the second patterned mask structure comprises the third side wall structure and the rest of the fifth oxide layer.
6. The method of any one of claims 1 to 5, wherein the first patterned mask structure is made of silicon oxide.
7. The method of any of claims 1-5, wherein forming a trench in the base structure using the first patterned mask structure comprises:
and performing an etching process on the substrate structure by taking the first patterned mask structure as a mask to form the groove, wherein the groove extends from the surface of the first patterned mask structure into the silicon carbide epitaxial layer.
8. The method of manufacturing a silicon carbide device according to any of claims 1-5, wherein forming a gate structure in the trench comprises:
performing an ion implantation process on the bottom of the trench to form a third ion implantation layer of the first conductivity type at the bottom of the trench;
forming a dielectric layer, wherein the dielectric layer covers the inner wall of the groove; and
and filling the groove with a polysilicon layer to form the grid structure.
9. The method of manufacturing a silicon carbide device of claim 8, wherein a ratio of an oxidation rate of the gate structure to an oxidation rate of the second ion implanted layer is between (3:1) and (15:1).
10. The method of manufacturing a silicon carbide device according to any of claims 1 to 5, wherein forming a contact structure in the exposed first ion implantation layer using the opening comprises:
performing an ion implantation process on the first ion implantation layer to form a fourth ion implantation layer; and
and performing a laser annealing process on the fourth ion implantation layer to form the contact structure.
11. The method of manufacturing a silicon carbide device according to claim 10, wherein the process temperature at which the laser annealing process is performed is between 800 ℃ and 1200 ℃.
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