CN105895671A - Semiconductor power device with ultralow power consumption and preparation method - Google Patents
Semiconductor power device with ultralow power consumption and preparation method Download PDFInfo
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- CN105895671A CN105895671A CN201610296901.9A CN201610296901A CN105895671A CN 105895671 A CN105895671 A CN 105895671A CN 201610296901 A CN201610296901 A CN 201610296901A CN 105895671 A CN105895671 A CN 105895671A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000002360 preparation method Methods 0.000 title description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 99
- 230000001413 cellular effect Effects 0.000 claims abstract description 71
- 230000007704 transition Effects 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 238000001259 photo etching Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 7
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 7
- 230000005611 electricity Effects 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000001459 lithography Methods 0.000 claims description 6
- 238000009825 accumulation Methods 0.000 claims description 5
- 238000007667 floating Methods 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 238000011084 recovery Methods 0.000 abstract description 5
- 238000005192 partition Methods 0.000 abstract 3
- 238000000407 epitaxy Methods 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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Abstract
The invention discloses a semiconductor power device with ultralow power consumption, wherein the quantity of photo-etching layers is small, and reverse recovery time is short. The device comprises a semiconductor baseplate, wherein a cellular area and a terminal protection area are disposed on the semiconductor base plate; and cells are disposed in the cellular area. The structure of the cellular area comprises a cellular groove, wherein upper conductive polycrystalline silicon layers and lower conductive polycrystalline silicon layers are disposed in the cellular groove; two sides of the upper conductive polycrystalline silicon layers are symmetrically disposed at extension parts which are located on two sides of the lower conductive polycrystalline silicon layers so as to form a cap-shaped structure. At least two voltage partition rings and at least one stop ring are disposed in the terminal protection area. The conductive polycrystalline silicon layer close to a voltage partition groove of the cellular area is electrically connected to a source electrode of the device; the rest conductive polycrystalline silicon layers in the voltage partition groove are suspended; and a Schottky diode is disposed in a transition area which is located between the cellular area and the terminal protection area. The invention also discloses a method which can be used for manufacture of the semiconductor power device with the ultralow power consumption.
Description
Technical field
The present invention relates to semiconductor power device and preparation method thereof, refer more particularly to a kind of super low-power consumption and partly lead
Body power device and preparation method thereof.
Background technology
Current super low-power consumption semiconductor power device is as common semiconductor power device, the most solid inside it
There is a parasitic diode connected in parallel, the body district of the anode of parasitic diode and power device and source electrode phase
Even, negative electrode is connected with the drain electrode of power device, and therefore power device is frequently used to afterflow, Clamping voltages exists
When afterflow or Clamping voltages, parasitic diode forward conduction, power device is also switched on, the source of power device
Pole (anode of parasitic diode) voltage ratio drain electrode (negative electrode of parasitic diode) voltage slightly higher, electric current from
Source electrode flows to drain electrode；When reversely ending, drain electrode (negative electrode of parasitic diode) the voltage ratio source of power device
Pole (anode of parasitic diode) voltage is high, and device only has the least electric leakage.This parasitic diode is with general
Logical diode is the same, minority carrier participate in conduction, therefore have reverse recovery time, thus reduce out
Close speed, add switching loss.
It addition, insider both knows about, groove power device has high integration, conducting resistance is low, switch is fast
The feature that degree is fast and switching loss is little, be widely used in all kinds of power management and conversion switch it
In.Along with energy-saving and emission-reduction are increasingly paid attention to by China, loss and conversion efficiency to power device require also
More and more higher.Wherein, conduction loss is mainly affected by conducting resistance, and specific on-resistance is the least, conducting
It is lost the least；And switching loss is mainly affected by gate charge, gate charge is the least, and switching loss is also more
Little.Therefore, reduce conducting resistance and gate charge is two effective ways reducing power device power consumption, logical
The power consumption crossing reduction power device can use the energy more efficiently.Additionally, at semiconductor power device
In preparation process, reducing specific on-resistance generally has two kinds of methods: one is by improving Cell density, increases
Add total effective width of unit cell.But, after Cell density improves, corresponding grid electric charge can increase, it is impossible to does
To not only reducing conducting resistance but also drop low gate charge；Two is by improving epitaxial wafer doping content, reducing epitaxial layer
Thickness realizes, but can reduce the breakdown voltage between source-drain electrode.United States Patent (USP): US20080042172A and
A kind of groove type double-layer grid power field effect transistor (Split Gate disclosed in Chinese patent 201110241526.5
MOSFET) more successfully solving the problems referred to above, this groove type double-layer grid power field effect transistor is passed through
Integrated one of lower trench improves breakdown voltage with the field plate effect of the shield grid of source shorted so that in phase
Under same breakdown voltage, the electric conduction of power device can be reduced by the doping content increasing silicon epitaxy layer
Resistance, thus conducting power consumption when reducing work.So, this groove type double-layer grid power field effect transistor is reducing
While conducting resistance (RDSON), gate charge can be reduced again, thus reduce switching loss.But, beautiful
In unfortunately owing to introducing the field plate structure of shield grid, device architecture and technique in the device structure more
Complexity, causes technique level to increase, and is presently mainly and uses 7 layer photoetching techniques to realize.And, it is eventually
Take dhield grid to be connected with source electrode on end protection ring, reverse pressure time electric field be concentrated mainly on close cellular
Inside first protection ring in district, cause pressure on the low side.
Summary of the invention
The technical problem to be solved is: provide a kind of photoetching number of plies few and reverse recovery time
Short super low-power consumption semiconductor power device.
For solving above-mentioned technical problem, the technical solution used in the present invention is: a kind of super low-power consumption quasiconductor merit
Rate device, including: semiconductor substrate, semiconductor substrate includes the first conductivity type substrate and is arranged on first
The first conductive type epitaxial layer in conductivity type substrate, the surface of the first conductive type epitaxial layer is the first master
Face, the surface of the first conductivity type substrate is the second interarea；First interarea includes: be provided with the cellular of cellular
District and be positioned at the terminal protection district that cellular region is peripheral；
The concrete structure of described cellular includes: be opened in the first groove i.e. cellular groove of cellular region, cellular ditch
Groove is provided with top conductive polycrystalline silicon floor and bottom conductive polycrystalline silicon floor, the both sides of top conductive polycrystalline silicon floor
For being symmetricly set on the extension of conductive polycrystalline silicon floor both sides, bottom, form cap-like structure；Upper and lower part is conducted electricity
The second insulated gate oxide layer, the side of conductive polycrystalline silicon floor both sides, top and cellular it is provided with between polysilicon layer
The first insulated gate oxide layer, the bottom surface of conductive polycrystalline silicon floor both sides, top and cellular groove it is provided with between groove
Between be provided with insulating oxide；
It is provided with at least two potential dividing ring in described terminal protection district and is positioned at peripheral at least one of potential dividing ring
Cut-off ring, the concrete structure of described potential dividing ring includes: the first groove i.e. dividing potential drop being opened in terminal protection district
Groove, is provided with conductive polycrystalline silicon floor and for by this conductive polycrystalline silicon floor and dividing groove in dividing groove
The insulating oxide of isolation, the first interarea that the end face of this conductive polycrystalline silicon floor is the most described, near cellular
Conductive polycrystalline silicon floor in first dividing groove in district is electrical connected with the source electrode of described device, remaining point
Conductive polycrystalline silicon floor in pressure groove is floating；
Transition region between cellular region and terminal protection district is provided with Schottky diode.
As a kind of preferred version, in described super low-power consumption semiconductor power device, described Schottky two
The structure of pole pipe includes: be opened in the first groove 3 i.e. transition groove of transition region, described transition groove and phase
The cellular groove correspondence connection answered, is provided with conductive polycrystalline silicon floor and for by many for this conduction in transition groove
Crystal silicon layer and the insulating oxide of transition trench isolations.
As a kind of preferred version, in described super low-power consumption semiconductor power device, described cellular groove
Width more than the half of corresponding cellular size.
To be solved by this invention another technical problem is that: the photoetching number of plies is few, technique is simple to provide one
The preparation method of super low-power consumption semiconductor power device.
For solving another above-mentioned technical problem, the technical solution used in the present invention is: a kind of super low-power consumption
The manufacture method of semiconductor power device, the steps include:
1) in the first conductivity type substrate, grow the first conductive type epitaxial layer, form semiconductor substrate；
2) on the first interarea, deposit hard mask layer, make hard mask etching region by lithography, and etch hard mask layer,
Form the hard mask for etching groove；
3) etch the first interarea, form the first groove in cellular region and terminal protection ring region, then, remove hard
Mask；
4) by deposit or one layer of insulating oxide of thermally grown formation on the first interarea and in the first groove；
5) deposit conductive polycrystalline silicon, then etching conductive polysilicon on the first interarea and in the first groove, go
Except the conductive polycrystalline silicon on the first interarea and above the first groove so that the conductive polycrystalline silicon floor in the first groove
Top end face be not higher than the surface of the first interarea that is first conductive type epitaxial layer；
6) with photoresist as mask, the conductive polycrystalline silicon of part in the first groove of etching cellular region；
7) etching insulating oxide, the both sides shape of the conductive polycrystalline silicon stayed in the first groove of cellular region respectively
Become the second groove and the 3rd groove；
8) photoresist, then, conductive polycrystalline silicon floor on the first interarea, in the first groove of cellular region are removed
Grown on interior walls the first insulated gate oxide layer of top and second, third described groove, in cellular region
The second insulated gate oxide layer is grown on the conductive polycrystalline silicon stayed in first groove；
9) conductive polycrystalline silicon is deposited on the first interarea and in the first groove, the second groove, the 3rd groove, so
After, the conductive polycrystalline silicon that deposited of etching, remove the conductive polycrystalline silicon on the first interarea, retain second, the
Conductive polycrystalline silicon floor and the end face of this conductive polycrystalline silicon floor in three grooves are not higher than the first interarea；
10) on the first interarea, inject the second conductive type impurity ion, form the second conduction by heat treatment
Type layer；
11) on the first interarea, inject the first conductive type impurity ion, form the first conduction by heat treatment
Type implanted layer；
12) accumulation insulating medium layer on the first interarea；
13) photoetching fairlead region, etching forms fairlead, and wherein, the fairlead of transition region is square
Hole, injects the second conductive type impurity sheath according to the inclination angle, direction corresponding with the four edges of fairlead；
14) deposit the first metal layer on the first interarea and in fairlead, make lead areas by lithography, etch shape
Become metal lead wire；
15) on the second interarea, carry out substrate grinding and deposit the second metal level, forming described quasiconductor merit
The backplate of rate device.
As a kind of preferred version, in the manufacture method of described super low-power consumption semiconductor power device,
Described the 12nd) after step, it may be assumed that on the first interarea after accumulation insulating medium layer, by insulating medium layer
Surface rubbing.
The invention has the beneficial effects as follows:
1, comparing existing 7 photoetching techniques, the present invention uses 4 photoetching techniques, saves 3 photoetching
Operation, technological process is the simplest, and compatible strong, stability is high, is suitable for volume production, and flow cost reduces
About 20%, greatly reduce manufacturing cost.
2, the super low-power consumption semiconductor power device that manufacture method of the present invention obtains, its upper guide are used
Electricity polysilicon layer forms cap-like structure, has lower switching loss and faster switching speed；Its terminal is protected
Protect the conductive polycrystalline silicon in the dividing groove of cellular region of the potential dividing ring in district with the source electrode of device electrical phase
Even, the conductive polycrystalline silicon floor in remaining dividing groove is floating, has the most both saved area, has improve again device
Part pressure；Additionally, due at the embedded Schottky diode of transition region so that described semiconductor power
Device has lower forward voltage drop, lower reverse recovery loss and milder Reverse recovery curve, device
Afterflow loss and reliability be improved；And, it is not necessary to increase extra chip area so that quasiconductor
The structure of device is compacter, reduces cost.
Accompanying drawing explanation
Fig. 1 to Figure 18 is that super low-power consumption semiconductor power device of the present invention is through of the present invention
The cross-sectional view in each stage formed after the correlation step of manufacture method.
Wherein: Fig. 2 to Figure 18 cuts open along A-A and the B-B hatching shown in Fig. 1, and Fig. 1 is along figure
C-C hatching shown in 15 is cut open.
Reference in Fig. 1 to Figure 18: 1, N-type substrate, 2, N-type epitaxy layer, the 21, first interarea,
22, the second interarea, 23, bar shaped fairlead, 24, square fairlead, 25, first annular fairlead, 26,
Second annular fairlead, the 3, first groove, the 31, second groove, the 32, the 3rd groove, 5, conductive polycrystalline
Silicon, 51, bottom conductive polycrystalline silicon floor, 52, conductive polycrystalline silicon floor, 53, conductive polycrystalline silicon floor, 54, lead
Electricity polysilicon layer, 6, photoresist, 7, conductive polycrystalline silicon, 71, top conductive polycrystalline silicon floor, 72, stretch out
Portion, the 8, second insulated gate oxide layer, the 9, first insulated gate oxide layer, 10, insulating oxide, 13, absolutely
Edge dielectric layer, 14, P-sheath, 15, N+ sheath, 16, the first metal layer, 161, metal lead wire,
162, metal lead wire, 17, P+ sheath, the 18, second metal level.
Detailed description of the invention
First, in conjunction with accompanying drawing 18, as a example by N-channel structure, describe the ultralow merit of one of the present invention in detail
The specific embodiments of consumption semiconductor power device.
As shown in figure 18, a kind of super low-power consumption semiconductor power device of the present invention, including: quasiconductor
Substrate, semiconductor substrate includes: N-type substrate 1 (also referred to as N+ substrate) and being arranged in N-type substrate 1
N-type epitaxy layer 2 (also referred to as N-epitaxial layer), the surface of N-type epitaxy layer 2 is the first interarea 21, N
The surface of type substrate 1 is the second interarea 22--shown in Figure 2；First interarea 21 includes: be provided with unit
The cellular region of born of the same parents and be positioned at the terminal protection district that cellular region is peripheral；
The concrete structure of described cellular includes: be opened in the first groove 3 i.e. cellular groove, the cellular of cellular region
Being provided with top conductive polycrystalline silicon floor 71 and bottom conductive polycrystalline silicon floor 51 in groove, wherein, top conduction is many
The both sides of crystal silicon layer 71 are the extension 72 being symmetricly set on bottom conductive polycrystalline silicon floor 51 both sides, form cap
Shape structure；The second insulated gate oxide layer 8, top it is provided with between upper and lower part conductive polycrystalline silicon floor 71 and 51
It is provided with the first insulated gate oxide layer 9, top between side and the cellular groove of conductive polycrystalline silicon floor 71 both sides
It is provided with insulating oxide 10 between bottom surface and the cellular groove of conductive polycrystalline silicon floor 71 extension 72；Described
The both sides of cellular groove are provided with P-well i.e. P-sheath 14, and P-sheath 14 is shallower than top conductive polycrystalline silicon floor
The bottom surface of the extension 72 of 71, the both sides of cellular groove are injected at the N+ that is provided above of P-sheath 14
Layer i.e. N+ sheath 15；It is provided with two potential dividing rings in described terminal protection district and is positioned at potential dividing ring periphery
One cut-off ring, the concrete structure of described potential dividing ring includes: be positioned in terminal protection district two near cellular region
The individual first i.e. dividing groove of groove 3, is provided with conductive polycrystalline silicon floor 52 and for this being led in dividing groove
The insulating oxide 10 that electricity polysilicon layer 52 is isolated with dividing groove, the end face of this conductive polycrystalline silicon floor 52 is not
Higher than the first described interarea 21, the conductive polycrystalline silicon floor 52 in first dividing groove of cellular region with
The source electrode of described super low-power consumption semiconductor power device is electrical connected, the conductive polycrystalline in remaining dividing groove
Silicon layer 52 is floating；The concrete structure of described cut-off ring includes: is opened in terminal protection district and is positioned at outside potential dividing ring
The first groove 3 enclosed i.e. ends groove, is provided with conductive polycrystalline silicon floor 53 and for should in cut-off groove
Conductive polycrystalline silicon floor 53 and the insulating oxide 10 ending trench isolations, the end face of this conductive polycrystalline silicon floor 53
The first the most described interarea 21；Transition region between cellular region and terminal protection district is provided with Schottky
Diode, its structure includes: be opened in the first groove 3 i.e. transition groove of transition region, transition groove and phase
The cellular groove correspondence connection answered, is provided with conductive polycrystalline silicon floor 54, conductive polycrystalline silicon floor 54 in transition groove
And it is provided with insulating oxide 10 between transition groove--shown in Figure 1.In the present embodiment, described
The width L2 of cellular groove is more than the half of corresponding cellular size L1--and shown in Figure 16.
The present embodiment uses two potential dividing rings and a cut-off ring, and the quantity of potential dividing ring should be according to actual needs
Determine.
It follows that combine accompanying drawing 1 to 18, as a example by N-channel, describe one of the present invention in detail surpass
The manufacture method of low-power consumption semiconductor power device, the steps include:
1) in N-type substrate 1, grow N-type epitaxy layer 2, form the semiconductor substrate shown in Fig. 2；
2) on the first interarea 21 i.e. surface of N-type epitaxy layer 2, deposit hard mask layer, make hard mask by lithography
Etch areas, and etch hard mask layer, form the hard mask for etching groove, belong to the usual of this area
Technology, the most reinflated narration at this；
3) etch the first interarea 21, form the first groove 3 in cellular region and terminal protection ring region, then, go
Except hard mask--shown in Figure 3；
4) by deposit or one layer of insulating oxide of thermally grown formation on the first interarea 21 and in the first groove 3
Layer 10--shown in Figure 4；
5) conductive polycrystalline silicon 5 is deposited on the first interarea 21 and in the first groove 3--shown in Figure 5,
Then, etching conductive polysilicon 5, remove on the first interarea 21 and conductive polycrystalline silicon above the first groove 3
5 so as to get the first groove 3 in the top end face all not higher than the of conductive polycrystalline silicon floor 51,52 and 53
The surface of the one i.e. N-type epitaxy layer of interarea 21, then, arranges photoresist 6, and by the region needing etching
Photoresist remove--shown in Figure 6；
6) with photoresist 6 as mask, the conductive polycrystalline silicon of part in etching cellular region the first groove 3, will
Top in conductive polycrystalline silicon floor 51 etches away--and shown in Figure 7；
7) etching insulating oxide, the conductive polycrystalline silicon floor 51 stayed in the first groove of cellular region respectively
Both sides form the second groove 31 and the 3rd groove 32--and shown in Figure 8；
8) photoresist 6, conductive polycrystalline silicon floor on the first interarea 21, in cellular region the first groove 3 are removed
The top of 51 and grown on interior walls the first insulated gate oxidation of second, third described groove 31 and 32
Layer 9, the conductive polycrystalline silicon floor 51 stayed in cellular region the first groove 3 grows the second insulated gate oxide layer
8--shown in Figure 9；
9) on the first interarea 21 and in first groove the 3, second groove the 31, the 3rd groove 32 of cellular region
Deposit conductive polycrystalline silicon 7--shown in Figure 10, then, the conductive polycrystalline silicon 7 that etching is deposited, goes
Except the conductive polycrystalline silicon 7 on the first interarea 21, retain first groove the 3, second groove 31 and in cellular region
Conductive polycrystalline silicon floor 71 and the end face of conductive polycrystalline silicon floor 71 in 3rd groove 32 are not higher than the first interarea
21--shown in Figure 11；
10) implanting p-type foreign ion on the first interarea 21, and form P-sheath 14 by heat treatment
--shown in Figure 12；
11) on the first interarea 21, inject N-type impurity ion, and form N+ sheath 15 by heat treatment
--shown in Figure 13；
12) accumulation insulating medium layer 13 on the first interarea 21--shown in Figure 14, then will insulation
The surface rubbing of dielectric layer 13, it is true that owing to the thickness of the first insulated gate oxide layer 9 is the least, the most not
Polish process；
13) photoetching fairlead region, etching insulating medium layer 13 and N-type epitaxy layer 2, outside etching N-type
When prolonging layer 2, etch into P-sheath 14 so that cellular fairlead i.e. bar shaped fairlead 23 extend into always
P-sheath 14--shown in Figure 15, form the square fairlead including bar shaped fairlead 23, transition region
24, the first annular fairlead 25 in terminal protection district and the second annular fairlead 26 drawing in interior each region
Portalling, wherein, the square fairlead 24 of transition region is square--shown in Figure 1, according to square
Inclination angle, the direction implanting p-type foreign ion layer that the four edges of fairlead 24 is corresponding, at square fairlead 24
Four sides formed P+ sheaths 17--shown in Figure 16；
If: the degree of depth of square fairlead 24 is H, width is W, and the thickness of described insulating medium layer 13 is
D1, the thickness of the exhausted oxide layer of edge 10 is D2, minimum angle-of-incidenceInclination maximumThat is: control inclination angle between minimum angle-of-incidence α and inclination maximum β to
Implanting p-type foreign ion layer in the square fairlead 24 of transition region, the position of injection is at this square fairlead 24
Insulating oxide 10 and the base of this square fairlead 24 respective side walls between；
14) on the first interarea 21 and include bar shaped fairlead 23, square fairlead 24, first annular
Fairlead 25 and the second annular fairlead 26 deposit the first metal layer 16 in each interior fairlead--ginseng
As shown in Figure 17, making lead areas by lithography, etching forms metal lead wire 161 and 162--see Figure 18 institute
Showing, metal lead wire 161 is connected with the source electrode of described device, and metal lead wire 162 is floating；
15) on the second interarea 22, carry out substrate grinding, and deposit the second metal level 18, formed and described partly lead
The backplate of body power device--shown in Figure 18.
In sum, only presently preferred embodiments of the present invention, not it is used for limiting the model that the present invention implements
Enclose, all impartial changes made according to the shape described in scope of the invention as claimed, structure, feature and spirit
With modification, all should be included in scope of the presently claimed invention.
Claims (5)
1. super low-power consumption semiconductor power device, including: semiconductor substrate, semiconductor substrate includes that first leads
Electricity type substrates and the first conductive type epitaxial layer being arranged in the first conductivity type substrate, the first conductive-type
The surface of type epitaxial layer is the first interarea, and the surface of the first conductivity type substrate is the second interarea；First interarea
Including: it is provided with the cellular region of cellular and is positioned at the terminal protection district that cellular region is peripheral；It is characterized in that:
The concrete structure of described cellular includes: be opened in the first groove i.e. cellular groove of cellular region, cellular ditch
Groove is provided with top conductive polycrystalline silicon floor and bottom conductive polycrystalline silicon floor, the both sides of top conductive polycrystalline silicon floor
For being symmetricly set on the extension of conductive polycrystalline silicon floor both sides, bottom, form cap-like structure；Upper and lower part is conducted electricity
The second insulated gate oxide layer, the side of conductive polycrystalline silicon floor both sides, top and cellular it is provided with between polysilicon layer
The first insulated gate oxide layer, the bottom surface of conductive polycrystalline silicon floor both sides, top and cellular groove it is provided with between groove
Between be provided with insulating oxide；
It is provided with at least two potential dividing ring in described terminal protection district and is positioned at peripheral at least one of potential dividing ring
Cut-off ring, the concrete structure of described potential dividing ring includes: the first groove i.e. dividing potential drop being opened in terminal protection district
Groove, is provided with conductive polycrystalline silicon floor and for by this conductive polycrystalline silicon floor and dividing groove in dividing groove
The insulating oxide of isolation, the first interarea that the end face of this conductive polycrystalline silicon floor is the most described, near cellular
Conductive polycrystalline silicon floor in first dividing groove in district is electrical connected with the source electrode of described device, remaining point
Conductive polycrystalline silicon floor in pressure groove is floating；
Transition region between cellular region and terminal protection district is provided with Schottky diode.
Super low-power consumption semiconductor power device the most according to claim 1, it is characterised in that: described Xiao
The structure of special based diode includes: be opened in the first groove i.e. transition groove of transition region, described transition ditch
Groove connection corresponding with corresponding cellular groove, is provided with conductive polycrystalline silicon floor and for should in transition groove
Conductive polycrystalline silicon floor and the insulating oxide of transition trench isolations.
Super low-power consumption semiconductor power device the most according to claim 1 and 2, it is characterised in that: institute
State the width half more than corresponding cellular size of cellular groove.
4. a manufacture method for super low-power consumption semiconductor power device, the steps include:
1) in the first conductivity type substrate, grow the first conductive type epitaxial layer, form semiconductor substrate；
2) on the first interarea, deposit hard mask layer, make hard mask etching region by lithography, and etch hard mask layer,
Form the hard mask for etching groove；
3) etch the first interarea, form the first groove in cellular region and terminal protection ring region, then, remove hard
Mask；
4) by deposit or one layer of insulating oxide of thermally grown formation on the first interarea and in the first groove；
5) deposit conductive polycrystalline silicon, then etching conductive polysilicon on the first interarea and in the first groove, go
Except the conductive polycrystalline silicon on the first interarea and above the first groove so that the conductive polycrystalline silicon floor in the first groove
Top end face be not higher than the surface of the first interarea that is first conductive type epitaxial layer；
6) with photoresist as mask, the conductive polycrystalline silicon of part in the first groove of etching cellular region；
7) etching insulating oxide, the both sides shape of the conductive polycrystalline silicon stayed in the first groove of cellular region respectively
Become the second groove and the 3rd groove；
8) photoresist, then, conductive polycrystalline silicon floor on the first interarea, in the first groove of cellular region are removed
Grown on interior walls the first insulated gate oxide layer of top and second, third described groove, in cellular region
The second insulated gate oxide layer is grown on the conductive polycrystalline silicon stayed in first groove；
9) conductive polycrystalline silicon is deposited on the first interarea and in the first groove, the second groove, the 3rd groove, so
After, the conductive polycrystalline silicon that deposited of etching, remove the conductive polycrystalline silicon on the first interarea, retain second, the
Conductive polycrystalline silicon floor and the end face of this conductive polycrystalline silicon floor in three grooves are not higher than the first interarea；
10) on the first interarea, inject the second conductive type impurity ion, form the second conduction by heat treatment
Type layer；
11) on the first interarea, inject the first conductive type impurity ion, form the first conduction by heat treatment
Type implanted layer；
12) accumulation insulating medium layer on the first interarea；
13) photoetching fairlead region, etching forms fairlead, and wherein, the fairlead of transition region is square
Hole, injects the second conductive type impurity sheath according to the inclination angle, direction corresponding with the four edges of fairlead；
14) deposit the first metal layer on the first interarea and in fairlead, make lead areas by lithography, etch shape
Become metal lead wire；
15) on the second interarea, carry out substrate grinding and deposit the second metal level, forming described quasiconductor merit
The backplate of rate device.
The manufacture method of a kind of super low-power consumption semiconductor power device the most according to claim 4, it is special
Levy and be: the described the 12nd) after step, it may be assumed that on the first interarea after accumulation insulating medium layer, will
The surface rubbing of insulating medium layer.
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| CN107968115A (en) * | 2016-10-20 | 2018-04-27 | 丰田自动车株式会社 | Semiconductor device |
| CN110036565A (en) * | 2016-12-08 | 2019-07-19 | 株式会社村田制作所 | Composite component and its mounting structure |
| CN112164652A (en) * | 2020-08-14 | 2021-01-01 | 江苏东海半导体科技有限公司 | Diagonal through-flow square cell IGBT and manufacturing method thereof |
| CN112234056A (en) * | 2020-09-03 | 2021-01-15 | 深圳市汇德科技有限公司 | Semiconductor device with a plurality of transistors |
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| CN107968115A (en) * | 2016-10-20 | 2018-04-27 | 丰田自动车株式会社 | Semiconductor device |
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| CN112164652B (en) * | 2020-08-14 | 2022-05-20 | 江苏东海半导体科技有限公司 | Diagonal through-current square cell IGBT and manufacturing method thereof |
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