CN109920838B - Groove type silicon carbide MOSFET device and preparation method thereof - Google Patents
Groove type silicon carbide MOSFET device and preparation method thereof Download PDFInfo
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Abstract
The invention provides a groove type silicon carbide MOSFET device and a preparation method thereof, wherein the device comprises a source electrode ohmic contact region, a drain electrode ohmic contact region, a silicon carbide N + substrate, a silicon carbide N-drift region, a Pbase region, an N + source region, a P + source region and a gate groove region‑The drift region and the ohmic contact current path from the silicon carbide N + substrate to the drain realize low-voltage opening, the device keeps the characteristics of low on-resistance and high off-voltage, the performance of the third quadrant of the device is improved, the parasitic inductance and the system loss of the device are reduced, and the power density is further improved.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a trench type silicon carbide MOSFET device structure of an integrated diode.
Background
Silicon Carbide (Silicon Carbide) material is one of the representatives of the third generation wide bandgap semiconductor material, has the characteristics of large forbidden bandwidth, high critical breakdown electric field, high thermal conductivity, high electronic saturation drift velocity and the like, and has wide application prospect in the fields of high power, high temperature and high frequency power electronics.
Silicon carbide power MOSFET device structures have evolved from LDMOS (lateral planar double diffused MOSFET), VVMOS (V-groove MOSFET), to planar VDMOS (vertical double diffused MOSFET), to trench MOSFET (trench MOSFET). The LDMOS has a simple structure, but the diffusion region and the channel region are arranged on the surface of the wafer, so that the utilization rate of the area of the chip is not high. The VVMOS is formed by forming a drain electrode on the back surface of a wafer, so that the conduction current of a chip can be greatly improved, but the V-shaped groove sharp prick can cause electric field concentration to reduce the breakdown voltage characteristic. Compared with a VDMOS device, the silicon carbide trench MOSFET has the advantages that the conducting channel is located in the vertical direction, parasitic JFET resistance of the planar VDMOS is eliminated, the cell size is reduced, the current density is obviously improved, meanwhile, the on-resistance is also reduced, and the problem that gate oxide of the silicon carbide trench MOSFET is easy to break down is solved. The novel SiC groove MOSFET device is of an asymmetric structure, an MOS channel is prepared in an ideal crystal orientation, so that higher channel mobility is obtained, and the bottom of a gate groove is partially wrapped by a P + region, so that a peak electric field at the bottom of gate oxide can be effectively relieved.
The silicon carbide has a wide forbidden band width, and the turn-on voltage of a body diode of the silicon carbide is very high (2.5-3V at room temperature) and much higher than that of a body diode of a silicon-based power device (0.7-0.8V at room temperature), so that the loss of the body diode of the silicon carbide MOSFET as a freewheeling diode is large. And more importantly, the body diode consisting of the Pbase region and the N-drift region is likely to cause bipolar degradation, and such degradation problem brings severe test to the long-term stable operation of the silicon carbide MOSFET and also brings challenge to the safety design of the whole power electronic system. In the current advanced power electronic application field, an anti-parallel silicon carbide diode is generally adopted as a freewheeling diode, and current is ensured to flow through the silicon carbide diode when a system is in a dead zone state, so that dead zone loss is effectively reduced and the reliability of the system is improved. Although the design and optimization of a full silicon carbide module, namely a plurality of silicon carbide MOSFETs and silicon carbide diodes which are connected in anti-parallel to the silicon carbide MOSFETs and realize different functions, have been greatly improved in recent years, because one power switch is always connected in anti-parallel to one diode, the external diode introduces extra parasitic capacitance, and meanwhile, a bonding wire connected with the external diode introduces stray inductance, so that the silicon carbide module is high in frequency and is always restricted in miniaturization. Therefore, in recent two years, top enterprises in the field represented by american universal electrical and japanese lom want to fully utilize the performance of the third quadrant of the SiC MOSFET, apply the synchronous rectification technology, abandon the antiparallel diode, and use the integrated schottky diode, because the barrier height of the schottky contact is lower than that of the ohmic contact, the turn-on voltage can be effectively reduced, but the process needs an additional schottky metal contact process and is incompatible with the existing silicon carbide MOSFET process. The silicon carbide groove MOSFET device provided by the invention adopts ohmic contact, simplifies the process flow, is compatible with the existing silicon carbide MOSFET device manufacturing process, improves the third quadrant performance of the device, further reduces the parasitic inductance and the device loss, and improves the power density and other performances of the power electronic module.
Disclosure of Invention
The invention aims to solve the problems and provides a trench type silicon carbide MOSFET device integrating lower conduction voltage than a Schottky tube diode and a preparation method thereof. The device not only realizes low on-resistance and high blocking voltage, but also improves the third quadrant performance of the device, so that the parasitic inductance of the device is further reduced, the system loss is further reduced, the power density is further improved, the process flow is simplified, and the device is compatible with the existing silicon carbide MOSFET device process.
In order to achieve the purpose, the invention adopts the following technical scheme:
a trench-type silicon carbide MOSFET device comprising: a drain metal 12, an N + substrate 11 above the drain metal 12, and an N-drift region 6 above the N + substrate 11; an N + ohmic contact region 10 is arranged in the middle of the upper part inside the N-drift region 6; a first P + region 9 is arranged on the left side of the N + ohmic contact region 10, and a second P + region 91 is arranged on the right side of the N + ohmic contact region 10; a first source metal 1 is arranged above the N + ohmic contact region 10, on the right side above the first P + region 9 and on the left side above the second P + region 91; a first N + source region 4 is arranged above the left side of the first P + region 9, and a second N + source region 41 is arranged above the right side of the second P + region 91; a first P + source region 3 is arranged on the left side of the first N + source region 4, and a second P + source region 31 is arranged on the right side of the second N + source region 41; a second source metal 2 is arranged above the first P + source region 3, and a third source metal 21 is arranged above the second P + source region 31; a first Pbase region 5 is arranged below the first N + source region 4 and the first P + source region 3, and a second Pbase region 51 is arranged below the second N + source region 41 and the second P + source region 31; a first trench gate dielectric region 7 is arranged between the right sides of the first N + source region 4 and the first Pbase region 5 and the first P + region 9, the first trench gate dielectric region 7 extends to the left side inside the first P + region 9, a second trench gate dielectric region 71 is arranged between the left sides of the second N + source region 41 and the second Pbase region 51 and the second P + region 91, and the second trench gate dielectric region 71 extends to the right side inside the second P + region 91; a first polysilicon gate 8 is arranged in the middle of the inside of the first trench gate dielectric region 7, and a second polysilicon gate 81 is arranged in the middle of the inside of the second trench gate dielectric region 71.
Preferably, high-energy ion implantation is used for both the first P + region 9 and the second P + region 91.
Preferably, the N + ohmic contact region 10, the first N + source region 4 and the second N + source region 41 are formed by simultaneous implantation.
Preferably, the depth of the first trench gate dielectric region 7 is smaller than the depth of the first P + region 9, and the depth of the second trench gate dielectric region 71 is smaller than the depth of the second P + region 91.
Preferably, the first source metal 1 is a source ohmic contact region, and is formed simultaneously with the second source metal 2 and the third source metal 21.
In order to achieve the above object, the present invention further provides a method for manufacturing the trench type silicon carbide MOSFET device, including the following steps:
the first step is as follows: growing an N-drift region 6 on an N-type substrate 11;
the second step is that: the first P + region 9 and the second P + region 91 are implanted together by using a mask and high-energy particle implantation with a doping concentration of 1 × 1019cm-3；
The third step: the first Pbase area 5 and the second Pbase area 51 are injected by adopting masks;
the fourth step: the first N + source region 4, the second N + source region 41 and the N + ohmic contact region 10 are implanted together with a mask, and the doping concentration is 1 × 1019cm-3；
The fifth step: mask implantation is carried out on the first P + source region 3 and the second P + source region 31;
and a sixth step: performing groove gate etching among the N + source region, the Pbase region and the P + region, wherein the depth of the groove gate is lower than that of the surrounding region;
the seventh step: carrying out gate oxide growth;
eighth step: depositing a polysilicon layer on the gate oxide, and performing surface planarization treatment on the polysilicon layer by adopting a CMP method to form a polysilicon gate structure;
the ninth step: and depositing an interlayer medium, forming a source end ohmic contact by opening a hole in the interlayer medium, and depositing a metal layer on the lower surface of the device to form a drain electrode metal contact.
The invention has the beneficial effects that: the diode is integrated in the silicon carbide groove MOSFET device, so that an external diode is prevented from being introduced, the cell size is reduced, the current density is obviously improved, and the on-resistance is reduced. On the other hand, the groove structure adopts an ideal crystal orientation to prepare the MOS channel, thereby obtaining higher channel mobility. When the device works in a third quadrant, positive voltage is applied to the source electrode, the depletion layer of the P + region and the N-drift region is reduced, and an N + ohmic contact region and an N + are formed-And a current path from the drift region and the silicon carbide N + substrate to the drain ohmic contact realizes low-voltage starting. The chip area is smaller compared to an antiparallel silicon carbide diode device; compared with a Schottky diode device integrated in a body, the Schottky diode device has lower third quadrant conduction voltage drop, is simple in process, is compatible with the existing silicon carbide MOSFET device preparation process, and does not need to add an additional Schottky metal contact preparation process. The device not only keeps low on-resistance and high off-voltage, but also improves the third quadrant performance of the device, reduces the parasitic inductance and system loss of the device, and further improves the power density.
Drawings
FIG. 1 is a schematic diagram of a conventional silicon carbide trench MOSFET device structure;
FIG. 2 is a schematic diagram of a Schottky diode integrated silicon carbide MOSFET device structure;
FIG. 3 is a schematic view of a trench type silicon carbide MOSFET device provided in accordance with the present invention;
FIGS. 4(a) -4 (i) are flow charts of the present invention for fabricating a trench type silicon carbide MOSFET device;
1 is a first source metal, 2 is a second source metal, 3 is a first P + source region, 4 is a first N + source region, 5 is a first Pbase region, 6 is an N-drift region, 7 is a first trench gate dielectric region, 8 is a first polysilicon gate, 9 is a first P + region, 10 is an N + ohmic contact region, 11 is an N + substrate, 12 is a drain metal, 21 is a third source metal, 31 is a second P + source region, 41 is a second N + source region, 51 is a second Pbase region, 71 is a second trench gate dielectric region, 81 is a second polysilicon gate, and 91 is a second P + region.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As shown in fig. 3, a trench type silicon carbide MOSFET device includes: a drain metal 12, an N + substrate 11 above the drain metal 12, and an N-drift region 6 above the N + substrate 11; an N + ohmic contact region 10 is arranged in the middle of the upper part inside the N-drift region 6; a first P + region 9 is arranged on the left side of the N + ohmic contact region 10, and a second P + region 91 is arranged on the right side of the N + ohmic contact region 10; a first source metal 1 is arranged above the N + ohmic contact region 10, on the right side above the first P + region 9 and on the left side above the second P + region 91; a first N + source region 4 is arranged above the left side of the first P + region 9, and a second N + source region 41 is arranged above the right side of the second P + region 91; a first P + source region 3 is arranged on the left side of the first N + source region 4, and a second P + source region 31 is arranged on the right side of the second N + source region 41; a second source metal 2 is arranged above the first P + source region 3, and a third source metal 21 is arranged above the second P + source region 31; a first Pbase region 5 is arranged below the first N + source region 4 and the first P + source region 3, and a second Pbase region 51 is arranged below the second N + source region 41 and the second P + source region 31; a first trench gate dielectric region 7 is arranged between the right sides of the first N + source region 4 and the first Pbase region 5 and the first P + region 9, the first trench gate dielectric region 7 extends to the left side inside the first P + region 9, a second trench gate dielectric region 71 is arranged between the left sides of the second N + source region 41 and the second Pbase region 51 and the second P + region 91, and the second trench gate dielectric region 71 extends to the right side inside the second P + region 91; a first polysilicon gate 8 is arranged in the middle of the inside of the first trench gate dielectric region 7, and a second polysilicon gate 81 is arranged in the middle of the inside of the second trench gate dielectric region 71.
The first P + region 9 and the second P + region 91 both adopt high-energy ion implantation.
The N + ohmic contact region 10, the first N + source region 4 and the second N + source region 41 are formed by simultaneous implantation.
The depth of the first trench gate dielectric region 7 is smaller than that of the first P + region 9, and the depth of the second trench gate dielectric region 71 is smaller than that of the second P + region 91.
The first source metal 1 is a source ohmic contact region, and is formed simultaneously with the second source metal 2 and the third source metal 21.
The embodiment also provides a preparation method of the trench type silicon carbide MOSFET device, which comprises the following steps:
the first step is as follows: growing an N-drift region 6 on an N-type substrate 11;
the second step is that: the first P + region 9 and the second P + region 91 are implanted together by using a mask and high-energy particle implantation with a doping concentration of 1 × 1019cm-3(ii) a As shown in fig. 4 (a);
the third step: the first Pbase area 5 and the second Pbase area 51 are injected by adopting masks; as shown in FIG. 4 (b);
the fourth step: a first N + source region 4 and a second N + source region41. The N + ohmic contact region 10 is implanted together with a mask having a doping concentration of 1 × 1019cm-3(ii) a As shown in FIG. 4 (c);
the fifth step: mask implantation is carried out on the first P + source region 3 and the second P + source region 31; as shown in FIG. 4 (d);
and a sixth step: performing groove gate etching among the N + source region, the Pbase region and the P + region, wherein the depth of the groove gate is lower than that of the surrounding region; as shown in fig. 4 (e);
the seventh step: carrying out gate oxide growth; as shown in fig. 4 (f).
Eighth step: depositing a polysilicon layer on the gate oxide, and performing surface planarization treatment on the polysilicon layer by adopting a CMP method to form a polysilicon gate structure; as shown in FIG. 4 (g);
the ninth step: and depositing an interlayer medium, forming a source end ohmic contact by opening a hole in the interlayer medium, and depositing a metal layer on the lower surface of the device to form a drain electrode metal contact. As shown in fig. 4 (h).
The resulting trench-type silicon carbide MOSFET device is shown in fig. 4 (i).
Claims (6)
1. A trench-type silicon carbide MOSFET device, comprising: a drain metal (12), an N + substrate (11) above the drain metal (12), and an N-drift region (6) above the N + substrate (11); an N + ohmic contact region (10) is arranged in the middle of the upper part inside the N-drift region (6); a first P + region (9) is arranged on the left side of the N + ohmic contact region (10), and a second P + region (91) is arranged on the right side of the N + ohmic contact region (10); a first source metal (1) is arranged above the N + ohmic contact region (10), on the right side above the first P + region (9) and on the left side above the second P + region (91); a first N + source region (4) is arranged above the left side of the first P + region (9), and a second N + source region (41) is arranged above the right side of the second P + region (91); a first P + source region (3) is arranged on the left side of the first N + source region (4), and a second P + source region (31) is arranged on the right side of the second N + source region (41); a second source metal (2) is arranged above the first P + source region (3), and a third source metal (21) is arranged above the second P + source region (31); a first Pbase region (5) is arranged below the first N + source region (4) and the first P + source region (3), and a second Pbase region (51) is arranged below the second N + source region (41) and the second P + source region (31); a first trench gate dielectric region (7) is arranged between the right sides of the first N + source region (4) and the first Pbase region (5) and the first P + region (9), the first trench gate dielectric region (7) extends to the left side inside the first P + region (9), a second trench gate dielectric region (71) is arranged between the left sides of the second N + source region (41) and the second Pbase region (51) and the second P + region (91), and the second trench gate dielectric region (71) extends to the right side inside the second P + region (91); a first polysilicon gate (8) is arranged in the middle of the inside of the first trench gate dielectric region (7), and a second polysilicon gate (81) is arranged in the middle of the inside of the second trench gate dielectric region (71).
2. The trench silicon carbide MOSFET device of claim 1, wherein: the first P + region (9) and the second P + region (91) are both implanted by high-energy ions.
3. The trench silicon carbide MOSFET device of claim 1, wherein: the N + ohmic contact region (10), the first N + source region (4) and the second N + source region (41) are formed by simultaneous implantation.
4. The trench silicon carbide MOSFET device of claim 1, wherein: the depth of the first trench gate dielectric region (7) is smaller than that of the first P + region (9), and the depth of the second trench gate dielectric region (71) is smaller than that of the second P + region (91).
5. The trench silicon carbide MOSFET device of claim 1, wherein: the first source metal (1) is a source ohmic contact region and is formed simultaneously with the second source metal (2) and the third source metal (21).
6. A method of fabricating a trench silicon carbide MOSFET device as claimed in any one of claims 1 to 5, comprising the steps of:
the first step is as follows: growing an N-drift region (6) on an N + substrate (11);
the second step is that: a first P + region (9) and a second P + region (9)1) Adopting mask implantation and high-energy particle implantation with doping concentration of 1 × 1019cm-3；
The third step: the first Pbase area (5) and the second Pbase area (51) are injected by adopting a mask;
the fourth step: the first N + source region (4), the second N + source region (41) and the N + ohmic contact region (10) are implanted together with a mask, and the doping concentration is 1 multiplied by 1019cm-3；
The fifth step: mask implantation is carried out on a first P + source region (3) and a second P + source region (31);
and a sixth step: performing groove gate etching among the N + source region, the Pbase region and the P + region, wherein the depth of the groove gate is lower than that of the surrounding region;
the seventh step: carrying out gate oxide growth;
eighth step: depositing a polysilicon layer on the gate oxide, and performing surface planarization treatment on the polysilicon layer by adopting a CMP method to form a polysilicon gate structure;
the ninth step: and depositing an interlayer medium, forming a source end ohmic contact by opening a hole in the interlayer medium, and depositing a metal layer on the lower surface of the device to form a drain electrode metal contact.
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| CN116825828A (en) * | 2022-03-21 | 2023-09-29 | 苏州东微半导体股份有限公司 | Silicon carbide device and method for manufacturing same |
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| CN103839943A (en) * | 2012-11-26 | 2014-06-04 | 英飞凌科技奥地利有限公司 | Semiconductor device |
| JP5939448B2 (en) * | 2013-04-30 | 2016-06-22 | 日産自動車株式会社 | Semiconductor device and manufacturing method thereof |
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| CN105633168A (en) * | 2015-12-31 | 2016-06-01 | 国网智能电网研究院 | SiC grooved metal oxide semiconductor field effect transistor (MOSFET) with integration of Schottky diode and fabrication method of SiC grooved MOSFET |
| CN108183131A (en) * | 2017-12-05 | 2018-06-19 | 中国电子科技集团公司第五十五研究所 | A kind of unilateral MOS type device preparation method of integrated SBD structures |
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