CN111370476B - IEGT with hole current carrying path and method of construction thereof - Google Patents

IEGT with hole current carrying path and method of construction thereof Download PDF

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CN111370476B
CN111370476B CN201811595355.4A CN201811595355A CN111370476B CN 111370476 B CN111370476 B CN 111370476B CN 201811595355 A CN201811595355 A CN 201811595355A CN 111370476 B CN111370476 B CN 111370476B
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region
base region
emitter
collector
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CN111370476A (en
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樱井建弥
吴磊
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Shanghai Ruiqu Microelectronics Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
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Abstract

The invention discloses an IEGT with a hole current-carrying path, comprising: the transistor comprises an emitter, an n + type emitter region, a grid, a base region, a p-type MOSFET, an n-type drift region, an n + type buffer region, a p + type collector region and a collector; a base region and a gate are arranged above the n-type drift region at intervals, a p-type MOSFET is arranged in the base region, the p-type MOSFET is turned off during the on-time of the main trench gate of the IEGT and turned on during the off-time of the main trench gate; an n + type emitting region is arranged on two sides of the surface of the other base region except the base region provided with the p-type MOSFET, and an emitting electrode connected with the n + type emitting region is arranged above the n + type emitting region; an n + -type buffer region is arranged below the n-type drift region, a p + -type collector region is arranged below the n + -type buffer region, and a collector is connected below the p + -type collector region. The IEGT with the hole current-carrying path has lower on-state voltage and turn-off loss.

Description

IEGT with hole current carrying path and method of construction thereof
Technical Field
The present invention relates to the field of semiconductors, and in particular, to an injection enhanced type insulated gate transistor (IEGT) with a hole current carrying path and a method for constructing the same.
Background
Insulated Gate Bipolar Transistors (IGBTs) are the most widely used power devices in power electronics applications such as household appliances, industry, renewable energy, UPS, rail, motor drive, Electric Vehicle (EV) and Hybrid Electric Vehicle (HEV) applications. Due to the presence of the bipolar junction transistor, it has a very high current handling capability. In its structure, about several hundred amperes, the blocking voltage is 6500V, so that the IGBT can control a load of several hundred kilowatts, useful for many applications. The IGBT is particularly suitable for failure work periods, low frequencies, high voltages and load changes, and can be used for locomotives, electric automobiles and hybrid electric automobiles. The growth in the area of renewable energy sources such as solar and wind power has led to increased demand.
High power IGBTs motors for wind turbines are of the variable speed type and require the use of high power IGBTs to improve efficiency. With the growth of infrastructure activities in developing countries, the demand for high voltage machinery is expected to grow, thus driving the market demand for high power IGBTs. IGBT applications in electric and hybrid electric vehicles include their use in powertrains and chargers for delivering and controlling electric motors. EV/HEV sales are expected to grow at a robust rate of around 35%, and battery manufacturing capacity is expected to increase by a factor of two at the end of the prediction period due to increased carbon dioxide regulation. According to market demands, the IGBT technology has been developed for 30 years, and the current technology development trend is continued. In the last decade, there has been intense competition among leading manufacturers worldwide and development of more advanced IGBT technology, and the latest IGBT technology has been completed in the progress of electric vehicles and hybrid vehicles. In short, the rapid growth of EV and HEV applications is the primary driving force for the development of IGBT technology.
The cross-sections of the existing IGBTs and IEGTs are shown in fig. 1a and 1 b. The IEGT has a floating p-layer, as shown in fig. 1a, and since there is no emitter region, this region cannot operate as an active region. However, the p-floating region is also unable to flow hole carriers out through the p-floating region to the emitter, since there is no contact with the emitter electrode. The IEGT device structure results in an accumulated hole carrier region under the floating p-base region, and the hole accumulation region in the drift layer results in heavy hole accumulation in the drift layer near the emitter region side. As a result, the device architecture results in heavy carrier modulation in the n-drift region, thus achieving a significant reduction in Vce (sat). However, the device operation results in a slow turn-off operation due to excessive carrier storage in the n-drift layer. In short, the IEGT may significantly reduce Vce (sat), but slowly turn off the switching time for large carrier storage in the drift region, and no carrier path in the pbo region.
Disclosure of Invention
In view of the above, the present invention is directed to an injection enhanced insulated gate transistor (IEGT) with a hole current carrying path and a method for constructing the same, so as to achieve a low on-state voltage and a low turn-off loss.
In particular, the present invention provides an injection enhanced insulated gate transistor, IEGT, having a hole carrier path, comprising: the transistor comprises an emitter, an n + type emitter region, a grid, a base region, a p-type MOSFET, an n-type drift region, an n + type buffer region, a p + type collector region and a collector; the base region and the gate are spaced above the n-type drift region, the p-type MOSFET is disposed in the base region, the p-type MOSFET is turned off during an on-time of a main trench gate of the IEGT and turned on during an off-time of the main trench gate; the n + type emitter region is arranged on two sides of the surface of the base region except the base region provided with the p-type MOSFET, and the emitter connected with the n + type emitter region is arranged above the n + type emitter region;
the n + -type buffer region is arranged below the n-type drift region, the p + -type collector region is arranged below the n + -type buffer region, and the collector is connected below the p + -type collector region.
Further, the IEGT having a hole carrying path further comprises: a p + type base region; the p + type base region is arranged between the n + type emitter regions on the two sides of each base region; and the emitting electrode connected with the n + type emitting region is arranged above the n + type emitting region and the p + type base region.
Further, the doping concentration of the base region is limited to 7E 15-1E 16cm3And limiting the depth of the n layer of the base region to 0.7 to 1 μm.
Further, no n + -type emitter region is provided above the base region where the p-type MOSFET tube is located, a p + -type base region is provided, the p-type MOSFET tube and the accumulation region of the hole carriers function during an on period of the main trench gate of the IEGT, and a hole carrier path flows out to the emitter electrode during an off period.
The present invention also provides a method of constructing an injection enhanced insulated gate transistor having a hole current carrying path, wherein the injection enhanced insulated gate transistor comprises: an emitter, an n + -type emitter region, a gate, a base region, a p-type MOSFET tube, an n-type drift region, an n + -type buffer region, a p + -type collector region, and a collector, the method comprising:
disposing the base region and gate spaced above the n-type drift region, disposing the p-type MOSFET tube at the base region, wherein the p-type MOSFET tube is off during an on-time of a main trench gate of the IEGT and on during an off-time of the main trench gate;
providing said n + -type emitter region on both sides of the surface of the base region other than said base region where said p-type MOSFET tube is provided, said emitter electrode connected to said n + -type emitter region being provided above said n + -type emitter region; and
and arranging the n + -type buffer region below the n-type drift region, arranging the p + -type collector region below the n + -type buffer region, and connecting the collector below the p + -type collector region.
Further, the injection enhancement type insulated gate transistor further comprises: a p + type base region;
the p + type base region is arranged between the n + type emitter regions on the two sides of each base region; and the emitting electrode connected with the n + type emitting region is arranged above the n + type emitting region and the p + type base region.
Further, the doping concentration of the base region is limited to 7E 15-1E 16cm3And limiting the depth of the n layer of the base region to 0.7 to 1 μm.
Further, it is characterized in that not an n + -type emitter region but a p + -type base region is provided above a base region where the p-type MOSFET tube is located, the p-type MOSFET tube and an accumulation region of hole carriers act during an on period of the main trench gate of the IEGT, and a hole carrier path flows out to the emitter electrode during an off period.
The IEGT of the invention having a hole carrier path, a p-type MOSFET tube is arranged in a base region which, during turn-on of the main IEGT, functions as a p-floating region, the p-type MOSFET tube being equivalently located in the p-floating region, and the p-MOSFET is turned off during the on-time of the main trench gate and turned on during the off-time of the main trench gate, the p-MOSFET in the p-floating region being turned off when the main n-MOSFET is turned on and the p-MOSFET in the p-base region being turned on when the main n-MOSFET is turned off depending on operation so that, during turn-off, a hole path to the emitter electrode is formed in the p-base region. As a result, during turn-off, the storage hole carriers can flow out through the p-MOSFET channel and result in faster turn-off without sacrificing vce (sat), thereby achieving a lower on-state voltage vce (sat) and lower turn-off loss Eoff.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention. In the drawings, like reference numerals are used to indicate like elements. The drawings in the following description are directed to some, but not all embodiments of the invention. For a person skilled in the art, other figures can be derived from these figures without inventive effort.
Fig. 1a and 1b are cross-sectional views of a conventional IEGT;
fig. 2 is a cross-sectional view of an IEGT having hole current carrying paths in accordance with an embodiment of the present invention; and
fig. 3 is a flow chart of a method of constructing an IEGT having a hole carrier path according to an embodiment of the invention.
Detailed Description
The exemplary embodiments of the present invention will now be described with reference to the accompanying drawings, however, the present invention may be embodied in many different forms and is not limited to the embodiments described herein, which are provided for complete and complete disclosure of the present invention and to fully convey the scope of the present invention to those skilled in the art. The terminology used in the exemplary embodiments illustrated in the accompanying drawings is not intended to be limiting of the invention. In the drawings, the same units/elements are denoted by the same reference numerals.
Unless otherwise defined, terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Further, it will be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.
Referring to fig. 2, as a preferred embodiment of an IEGT with a hole current carrying path of the present invention, the IEGT with a hole current carrying path comprises: the transistor comprises an emitter, an n + type emitter region, a grid, a base region, a p-type MOSFET, an n-type drift region, an n + type buffer region, a p + type collector region and a collector;
the base region and the gate are spaced above the n-type drift region, the p-type MOSFET is disposed in the base region, the p-type MOSFET is turned off during an on-time of a main trench gate of the IEGT and turned on during an off-time of the main trench gate; the n + type emitter region is arranged on two sides of the surface of the base region except the base region provided with the p-type MOSFET, and the emitter connected with the n + type emitter region is arranged above the n + type emitter region;
the n + -type buffer region is arranged below the n-type drift region, the p + -type collector region is arranged below the n + -type buffer region, and the collector is connected below the p + -type collector region.
Further, the IEGT having a hole carrying path further comprises: a p + type base region; the p + type base region is arranged between the n + type emitter regions on the two sides of each base region; and the emitting electrode connected with the n + type emitting region is arranged above the n + type emitting region and the p + type base region.
Further, the doping concentration of the base region is limited to 7E 15-1E 16cm3And limiting the depth of the n layer of the base region to 0.7 to 1 μm.
Further, no n + -type emitter region is provided above the base region where the p-type MOSFET tube is located, a p + -type base region is provided, the p-type MOSFET tube and the accumulation region of the hole carriers function during an on period of the main trench gate of the IEGT, and a hole carrier path flows out to the emitter electrode during an off period.
The p-base region of the present embodiment may operate as a multi-carrier path in a region during off-periods and may be used to store carriers in an n-region during on-periods. In short, during the turn-on of the main IEGT, the p-base region acts as a p-floating region and stores heavy hole carriers near the n-drift layer. The p-MOSFET is arranged in the p-floating region, and the p-MOSFET is turned off during an on-time of the main trench gate and turned on during an off-time of the main trench gate. In accordance with operation, when the main n-MOSFET is turned on, the p-MOSFET in the p-floating region is turned off, and when the main n-MOSFET is turned off, the p-MOSFET in the p-floating region is turned on so that a hole path is formed in the p-base region during turn-off. As a result, during turn-off, the stored hole carriers can flow out to the emitter electrode through the p-MOSFET channel and cause a fast turn-off without sacrificing vce (sat). The manufacturing process is almost the same as conventional. Devices such as IEGT and IGBT can be easily produced with only small changes in Mask settings.
The invention provides an IEGT with a hole current carrying path, in that a p-type MOSFET tube is arranged in a base region, which base region acts as a p-floating region during the turn-on of the main IEGT, the p-type MOSFET tube is equivalently located in the p-floating region, and the p-MOSFET is turned off during the turn-on time of the main trench gate and turned on during the turn-off time of the main trench gate, according to the operation, the p-MOSFET in the p-floating region is turned off when the main n-MOSFET is turned on, and the p-MOSFET in the p-base region is turned on when the main n-MOSFET is turned off so that a hole path to the emitter electrode is formed in the p-base region during the turn-off. As a result, during turn-off, the storage hole carriers can flow out through the p-MOSFET channel and result in faster turn-off without sacrificing vce (sat), thereby achieving a lower on-state voltage vce (sat) and lower turn-off loss Eoff.
Fig. 3 is a flow chart of a method 300 of constructing an IEGT having a hole carrier path according to an embodiment of the invention. Wherein the injection enhanced insulated gate transistor comprises: an emitter, an n + -type emitter region, a gate, a base region, a p-type MOSFET, an n-type drift region, an n + -type buffer region, a p + -type collector region, and a collector.
As shown in fig. 3, method 300 begins at step 301. At step 301, the base region and gate are spaced above the n-type drift region, the p-type MOSFET tube is disposed in the base region, wherein the p-type MOSFET tube is off during the on-time of the main trench gate of the IEGT and on during the off-time of the main trench gate.
In step 302, the n + -type emitter is disposed on both sides of the surface of the base region other than the base region where the p-type MOSFET tube is disposed, and the emitter connected to the n + -type emitter is disposed above the n + -type emitter.
In step 303, the n + -type buffer region is disposed below the n-type drift region, the p + -type collector region is disposed below the n + -type buffer region, and the collector is connected below the p + -type collector region.
The injection enhanced insulated gate transistor further comprises: a p + type base region; the p + type base region is arranged between the n + type emitter regions on the two sides of each base region; and the emitting electrode connected with the n + type emitting region is arranged above the n + type emitting region and the p + type base region. Limiting the doping concentration of the base region to 7E 15-1E 16cm3And limiting the depth of the n layer of the base region to 0.7 to 1 μm.
An n + -type emitter region is not provided above a base region where the p-type MOSFET is located, but a p + -type base region is provided, the p-type MOSFET and an accumulation region of hole carriers function during an on period of a main trench gate of the IEGT, and a hole carrier path flows out to the emitter electrode during an off period.
The invention has been described with reference to a few embodiments. However, other embodiments of the invention than the one disclosed above are equally possible within the scope of the invention, as would be apparent to a person skilled in the art from the appended patent claims.
Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise herein. All references to "a/an/the [ device, component, etc ]" are to be interpreted openly as referring to at least one instance of said device, component, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated.

Claims (6)

1. An injection enhanced insulated gate transistor having a hole current carrying path, comprising: the transistor comprises an emitter, an n + type emitter region, a grid, a base region, a p-type MOSFET, an n-type drift region, an n + type buffer region, a p + type collector region and a collector;
the base region and the gate are arranged above the n-type drift region at intervals, the p-type MOSFET is arranged at the base region, and the p-type MOSFET is turned off during the turn-on time of a main trench gate of an injection enhanced insulated gate transistor (IEGT) and is turned on during the turn-off time of the main trench gate; the n + type emitter region is arranged on two sides of the surface of the base region except the base region provided with the p-type MOSFET, and the emitter connected with the n + type emitter region is arranged above the n + type emitter region;
the n + -type buffer region is arranged below the n-type drift region, the p + -type collector region is arranged below the n + -type buffer region, and the collector is connected below the p + -type collector region;
no n + -type emitter region is provided above the base region where the p-type MOSFET tube is located, a p + -type base region is provided, the p-type MOSFET tube and an accumulation region of hole carriers function during an on period of the main trench gate of the IEGT, and a hole carrier path flows out to the emitter electrode during an off period.
2. The implant-enhanced insulated gate transistor of claim 1, further comprising: a p + type base region;
the p + type base region is arranged between the n + type emitter regions on the two sides of each base region; and the emitting electrode connected with the n + type emitting region is arranged above the n + type emitting region and the p + type base region.
3. The implant-enhanced insulated gate transistor of claim 1, wherein a doping concentration of the base region is limited to 7E 15-1E 16cm3And limiting the depth of the n layer of the base region to 0.7 to 1 μm.
4. A method of constructing an injection enhanced insulated gate transistor having a hole current carrying path, wherein the injection enhanced insulated gate transistor, IEGT, comprises: an emitter, an n + -type emitter region, a gate, a base region, a p-type MOSFET tube, an n-type drift region, an n + -type buffer region, a p + -type collector region, and a collector, the method comprising:
disposing the base region and gate spaced above the n-type drift region, disposing the p-type MOSFET tube at the base region, wherein the p-type MOSFET tube is off during an on-time of a main trench gate of the IEGT and on during an off-time of the main trench gate;
providing said n + -type emitter region on both sides of the surface of the base region other than said base region where said p-type MOSFET tube is provided, said emitter electrode connected to said n + -type emitter region being provided above said n + -type emitter region; and
arranging the n + -type buffer region below the n-type drift region, arranging the p + -type collector region below the n + -type buffer region, and connecting the collector below the p + -type collector region;
an n + -type emitter region is not provided above a base region where the p-type MOSFET is located, but a p + -type base region is provided, the p-type MOSFET and an accumulation region of hole carriers function during an on period of a main trench gate of the IEGT, and a hole carrier path flows out to the emitter electrode during an off period.
5. The method of claim 4, wherein the implant-enhanced insulated gate transistor further comprises: a p + type base region;
the p + type base region is arranged between the n + type emitter regions on the two sides of each base region; and the emitting electrode connected with the n + type emitting region is arranged above the n + type emitting region and the p + type base region.
6. The method as claimed in claim 4, wherein the doping concentration of the base region is limited to 7E 15-1E 16cm3And limiting the depth of the n layer of the base region to 0.7 to 1 μm.
CN201811595355.4A 2018-12-25 2018-12-25 IEGT with hole current carrying path and method of construction thereof Active CN111370476B (en)

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US5973359A (en) * 1997-11-13 1999-10-26 Fuji Electric Co., Ltd. MOS type semiconductor device
CN102201439A (en) * 2011-05-10 2011-09-28 电子科技大学 Trench-type insulated gate bipolar transistor (Trench IGBT) with enhanced internal conductivity modulation
CN205159332U (en) * 2015-09-30 2016-04-13 深圳市可易亚半导体科技有限公司 Horizontal slot insulated electrode bars bipolar transistor of shunt structural type
CN107623027A (en) * 2017-10-20 2018-01-23 电子科技大学 A kind of trench gate electric charge memory type insulated gate bipolar transistor and its manufacture method
CN108807505A (en) * 2018-08-28 2018-11-13 电子科技大学 A kind of silicon carbide MOSFET device and its manufacturing method

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Publication number Priority date Publication date Assignee Title
JP4371521B2 (en) * 2000-03-06 2009-11-25 株式会社東芝 Power semiconductor device and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5973359A (en) * 1997-11-13 1999-10-26 Fuji Electric Co., Ltd. MOS type semiconductor device
CN102201439A (en) * 2011-05-10 2011-09-28 电子科技大学 Trench-type insulated gate bipolar transistor (Trench IGBT) with enhanced internal conductivity modulation
CN205159332U (en) * 2015-09-30 2016-04-13 深圳市可易亚半导体科技有限公司 Horizontal slot insulated electrode bars bipolar transistor of shunt structural type
CN107623027A (en) * 2017-10-20 2018-01-23 电子科技大学 A kind of trench gate electric charge memory type insulated gate bipolar transistor and its manufacture method
CN108807505A (en) * 2018-08-28 2018-11-13 电子科技大学 A kind of silicon carbide MOSFET device and its manufacturing method

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