CN108231904A - 薄膜晶体管及其驱动方法、显示装置和晶体管电路 - Google Patents
薄膜晶体管及其驱动方法、显示装置和晶体管电路 Download PDFInfo
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- CN108231904A CN108231904A CN201711190146.7A CN201711190146A CN108231904A CN 108231904 A CN108231904 A CN 108231904A CN 201711190146 A CN201711190146 A CN 201711190146A CN 108231904 A CN108231904 A CN 108231904A
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Abstract
本发明涉及薄膜晶体管及其驱动方法、显示装置和晶体管电路。一种氧化物半导体薄膜晶体管包括:源极电极及漏极电极;沟道层,其由氧化物半导体形成;第一绝缘膜;第一栅极电极,其形成在与形成于沟道层和第一绝缘膜之间的界面上的第一沟道区域相对的面侧;第二绝缘膜;以及第二栅极电极,其形成在与形成于沟道层和第二绝缘膜之间的界面上的第二沟道区域相对的面侧,在将第一沟道区域的在源极电极和漏极电极的并排设置方向上的长度设为第一沟道长度,第二沟道区域的在并排设置方向上的长度设为第二沟道长度的情况下,第二沟道长度比第一沟道长度短,且施加于第二栅极电极的电位大于或等于源极电极和漏极电极的电位中的较低的电位。
Description
技术领域
本发明涉及薄膜晶体管、显示装置、晶体管电路及薄膜晶体管的驱动方法。
背景技术
近年来,使用氧化物半导体作为沟道层的薄膜晶体管(thin film transistor,TFT)、所谓的氧化物TFT已被广泛使用。氧化物TFT相对于现有的非晶硅(a-Si)TFT具有高迁移度的特征。因此,在显示装置中,采用氧化物TFT作为驱动电路,由此能够实现电路的小型化和配线的微型化。
在显示装置中,驱动电路的小型化和配线的微型化有助于像素的开口率的提高。因此,能够实现显示装置的高分辨率。
在使用氧化物TFT作为采用了液晶显示器(LCD)或有机发光二极管(OLED)的显示器的例如像素开关、垂直移位寄存器(VSR)等的周边驱动电路的情况下,要求良好的初始特性和长期的稳定性。
对于这样的要求,提出了在对底栅型氧化物TFT添加顶栅电极的双栅型氧化物TFT中对顶栅电极施加负电位的驱动方法(例如,日本专利申请特开No.2012-19206)。对顶栅电极施加负电位,由此氧化物TFT的阈值电压移动到正侧。其结果是,实现氧化物TFT的常关,因此获得良好的初始特性。
发明内容
然而,在氧化物TFT中,与氢化非晶硅(a-Si:H)TFT相比,底栅型氧化物TFT特别容易被存在于TFT上的非预期的电荷影响。这被称作顶栅效应。由于顶栅效应,底栅型氧化物TFT易于呈现较差的初始特性和长期稳定性。
本发明的一个方面的目的是提供能够相对于TFT上的电荷产生使特性稳定的薄膜晶体管等。
本发明的一个方面的薄膜晶体管包括:源极电极和漏极电极;由氧化物半导体形成的沟道层,所述沟道层与所述源极电极和所述漏极电极连接;第一绝缘膜,所述第一绝缘膜形成在所述沟道层的第一面侧上;第一栅极电极,所述第一栅极电极形成在与形成于所述沟道层和所述第一绝缘膜之间的第一界面上的第一沟道区域相对的面侧;第二绝缘膜,所述第二绝缘膜形成在所述沟道层的第二面侧;以及第二栅极电极,所述第二栅极电极形成在与形成于所述沟道层和所述第二绝缘膜之间的第二界面上的第二沟道区域相对的面侧,其中,所述源极电极和所述漏极电极空出间隙地并排设置,在将所述第一沟道区域的在所述源极电极和所述漏极电极的并排设置方向上的长度设为第一沟道长度,所述第二沟道区域的在所述并排设置方向上的长度设为第二沟道长度的情况下,所述第二沟道长度比所述第一沟道长度短,且施加于所述第二栅极电极的电位大于或等于所述源极电极和所述漏极电极的电位中的较低电位。
根据本发明的一个方面,能够相对于电荷产生使特性稳定。
上面的和进一步的目的和特征通过下面结合附图的详细说明将变得更清楚。
应该理解的是,上面的概述和下面的详述是示例性和说明性的,而不旨在限制本发明。
附图说明
图1是示出根据第一实施方式的氧化物TFT的结构示例的剖视图;
图2是示出根据第一实施方式的氧化物TFT的结构示例的俯视图;
图3是示出根据第二实施方式的氧化物TFT的结构示例的剖视图;
图4是示出根据第二实施方式的氧化物TFT的结构示例的俯视图;
图5是示出根据第三实施方式的氧化物TFT的结构示例的剖视图;
图6是示出根据第三实施方式的氧化物TFT的结构示例的俯视图;
图7是示出栅极驱动器的输出级的一示例的电路图;
图8是示出像素电路的一示例的电路图;
图9是示出像素电路的一示例的电路图;
图10是示出顶栅电极的电位的控制示例的图;
图11是示出根据第四实施方式的氧化物TFT的结构示例的俯视图;
图12A和图12B是示出根据第五实施方式的氧化物TFT的结构示例的说明图;
图13A和图13B是示出根据第六实施方式的氧化物TFT的结构示例的说明图;
图14A和图14B是示出根据第七实施方式的氧化物TFT的结构示例的说明图;
图15A和图15B是示出使用氧化物TFT的电路示例的电路图;以及
图16是示出驱动电路的一示例的电路图。
具体实施方式
下文将参照附图对实施方式进行详细说明。
此外,为了限定要素之间的关系并防止要素之间的混淆,说明书和权利要求书中应用诸如“第一”和“第二”的序数。因此,这些序数并不限定要素的数量。
另外,各图中的各要素的大小或比例为了确保图的可视性而被适当变更地示出。另外,各图中的阴影是为了区分各构成要素,不一定表示剖面。
另外,“电极”或“配线”和“端子”等术语并不在功能上限定这些构成要素。例如,“端子”和“配线”可用作”电极”的一部分。另外,相反,“电极”和“端子”可用作“配线”的一部分。另外,反之,“电极”和“配线”可用作“端子”的一部分。
第一实施方式
图1是示出根据第一实施方式的氧化物TFT 1的结构示例的剖视图。氧化物TFT 1包括基板11、底栅电极12、栅极绝缘膜13、氧化物半导体层14、蚀刻终止膜15、源极及漏极电极16、钝化膜17以及顶栅电极18。图2是示出根据第一实施方式的氧化物TFT 1的结构示例的俯视图。在图2中,示出了底栅电极12、氧化物半导体层14、蚀刻终止膜15、源极及漏极电极16以及顶栅电极18。此外,源极及漏极电极16、顶栅电极18、底栅电极12通过接触孔(图未示)连接到外部电路。
如图1所示,在氧化物TFT 1中,底栅电极12、栅极绝缘膜13、氧化物半导体层14、蚀刻终止膜15、源极及漏极电极16、钝化膜17以及顶栅电极18依次层压在基板11上。
基板11为矩形板状。基板11是玻璃基板等绝缘基板。
底栅电极12由诸如钼(Mo)、铌(Nb)、钨(W)、铝(Al)、铬(Cr)、铜(Cu)或银(Ag)的金属形成。底栅电极12可通过层压这些金属而形成。另外,底栅电极12可通过使用铜合金、铝合金或银合金形成。顶栅电极18也与底栅电极12同样地形成。
栅极绝缘膜13例如由氧化硅(SiO2)或氮化硅(Si3N4)形成。栅极绝缘膜13可通过层压氧化硅和氮化硅形成。另外,栅极绝缘膜13可通过使用氧化铝或氧化钽形成。蚀刻终止膜15和钝化膜17也与栅极绝缘膜13同样地形成。
氧化物半导体层14是由例如IGZO的氧化物半导体形成的层。IGZO是铟(In)、镓(Ga)、锌(Zn)和氧(O)的化合物。氧化物半导体层14可以由铟、锌和氧的化合物(In-Zn-O)、铟、镓和氧的化合物(In-Ga-O)或铟、硅和氧的化合物(In-Si-O)形成。
源极及漏极电极16包括电极161和电极162这两个电极。根据氧化物TFT 1的操作状态,电极161和电极162这两个电极中的一个电极用作源极电极,另一个电极用作漏极电极。即,存在电极161用作源极电极、电极162用作漏极电极的情况、以及电极161用作漏极电极、电极162用作源极电极的情况。在下面的说明中,为了简单,将电极161称作源极电极161,将电极162称作漏极电极162。源极电极161和漏极电极162具有大致相同的形状。如图1和图2所示,源极电极161和漏极电极162空出间隙地并排设置。源极及漏极电极16可由钼、钛、钨或铝等形成。源极及漏极电极16可由钼合金、钛合金、铝合金、铜合金等形成。源极及漏极电极16可通过将多个单体金属或合金层压而形成。
如图1所示,在本实施方式的氧化物TFT 1中,蚀刻终止膜15的在纸面上的横向的长度(以下,称作横向宽度)比氧化物半导体层14的横向宽度小。源极电极161和漏极电极162之间的间隙的横向宽度比蚀刻终止膜15的横向宽度小。因此,如图1所示,源极电极161和漏极电极162在剖面图中为台阶状。因此,本实施方式的氧化物TFT 1为蚀刻终止型TFT。在氧化物TFT 1中,在氧化物半导体层14上形成沟道层。此外,在图1中,栅极电极12的横向宽度比氧化物半导体层14的横向宽度窄,但是不限于此。栅极电极12的横向宽度可以比氧化物半导体层14的横向宽度宽。
另外,在氧化物TFT 1中,顶栅电极18的横向宽度比源极电极161和漏极电极162之间的间隙的横向宽度宽。底栅电极12的横向宽度比蚀刻终止膜15的横向宽度宽。在氧化物半导体层14中,在相对于栅极绝缘膜13的界面的一部分中形成第一沟道区域141。更具体地,在俯视图中,该界面上的与蚀刻终止膜15重叠的区域为第一沟道区域141。第一沟道区域141是这样的区域:载流子密度能够根据底栅电极12的电压而受控制。另外,在氧化物半导体层14中,在相对于蚀刻终止膜15的界面的一部分中形成第二沟道区域142。更具体地,在俯视图中,该界面上的与源极电极161和漏极电极162之间的间隙重叠的区域为第二沟道区域142。第二沟道区域142是这样的区域:载流子密度能够根据顶栅电极18的电压而受控制。在第一沟道区域141中,图1和图2的纸面上的横向的长度LB将被称作第一沟道长度。在第二沟道区域142中,图1和图2中的纸面中的横向的长度LT将被称作第二沟道长度。如图1和图2所示,在本实施方式的氧化物TFT 1中,第二沟道长度LT比第一沟道长度LB短。
在本实施方式中,当驱动如上构造的氧化物TFT 1时,对顶栅电极18施加大于或等于源极电极161的电位Vs和漏极电极162的电位Vd中的较低电位的电位。顶栅电极18的电位由Vtg表示。该实施方式的氧化物TFT 1的特性由下面的式(1)和式(2)或下面的式(1)和式(3)表示。
LB>LT…(1)
其中,
LB:第一沟道长度
LT:第二沟道长度
Vtg≥Vs且Vs<Vd…(2)
Vtg≥Vd且Vs>Vd…(3)
其中,
Vtg:顶栅电极18的电位
Vs:源极电极161的电位
Vd:漏极电极162的电位
在氧化物TFT 1中,沟道层的第一表面与第一绝缘膜接触。沟道层形成在氧化物半导体层14的界面上。第一绝缘膜的一示例是栅极绝缘膜13。另外,沟道层的第二表面与第二绝缘膜接触。第二绝缘膜的一示例是蚀刻终止膜15。第二绝缘膜的另一示例是形成为与蚀刻终止膜15接触、尤其与蚀刻终止膜15的上表面接触的钝化膜17。另外,当氧化物TFT 1操作时,通过第一栅极电极,在第一绝缘膜的相对于沟道层的第一界面上形成第一沟道区域。第一栅极电极的一示例是底栅电极12。另外,通过第二栅极电极,在第二绝缘膜的相对于沟道层的第二界面上形成第二沟道区域。第二栅极电极的一示例是顶栅电极18。
在本实施方式中,获得以下的效果。驱动氧化物TFT 1,使得顶栅电极18的电位Vtg大于或等于源极电极161的电位Vs和漏极电极162的电位Vd中的较低的电位。由此,即使在氧化物TFT 1上产生电荷的情况下,初始特性也稳定。具体而言,能够抑制氧化物TFT 1从断开切换到接通的栅极电压的波动,即阈值电压的波动(有时称作由于顶栅电极的电位引起的阈值电压偏移)。
在诸如平板显示器和传感器的电子设备中的氧化物TFT的操作中,使该氧化物TFT的栅极电极相对于源极电极正偏置一定时间量(有时也被称为正栅极应力)。当对氧化物TFT 1施加正栅极应力时,在顶栅电极18的电位Vtg小于源极电极161的电位Vs和漏极电极162的电位Vd中的较低电位的情况下,阈值电压的波动具有加速的倾向。然而,在本实施方式中,Vtg大于或等于Vs和Vd中的较低电位,因此能够抑制阈值电压的波动(有时也被称为由于正栅极应力引起的阈值电压偏移)。即,氧化物TFT 1的操作可靠性提高。
正栅极应力表示大于或等于源极电极或漏极电极的电位的电位施加于栅极电极的状态(偏置状态)。例如,偏置状态是高电平的电压施加于栅极电极并且低电平的电压施加于源极电极或漏极电极的状态。已知由于正栅极应力使阈值电压偏移。
第二实施方式
图3是示出根据第二实施方式的氧化物TFT 1的结构示例的剖视图。氧化物TFT 1包括基板11、底栅电极12、栅极绝缘膜13、氧化物半导体层14、源极及漏极电极16、钝化膜17以及顶栅电极18。图4是示出根据第二实施方式的氧化物TFT 1的结构示例的俯视图。在图4中,示出了底栅电极12、氧化物半导体层14、源极及漏极电极16及顶栅电极18。在图3和图4中,对具有与第一实施方式相同功能的构成元件应用相同的附图标记。在以下的说明中,主要对与第一实施方式的不同点进行说明。
如图3所示,在氧化物TFT 1中,底栅电极12、栅极绝缘膜13、氧化物半导体层14、源极及漏极电极16、钝化膜17以及顶栅电极18依次层压在基板11上。
源极及漏极电极16包括电极161和电极162这两个电极。与第一实施方式相同,为了简化,将电极161称作源极电极161,将电极162称作漏极电极162。源极电极161和漏极电极162为大致相同的形状。如图3和图4所示,源极电极161和漏极电极162空出间隙地并排设置。
如图3所示,在本实施方式的氧化物TFT 1中,底栅电极12的横向宽度(纸面上的横向方向的长度)比氧化物半导体层14的横向宽度小。顶栅电极18的横向宽度比源极电极161和漏极电极162之间的间隙的横向宽度小。换言之,顶栅电极18的长度比源极电极161的边缘和漏极电极162的边缘之间的长度短。因此,本实施方式的氧化物TFT 1是沟道蚀刻型TFT。在氧化物TFT 1中,氧化物半导体层14是沟道层。钝化膜17是第二绝缘膜的一示例。在本实施方式中,第二绝缘膜是在单个工序中形成的单层膜。此外,在图3中,栅极电极12的横向宽度比氧化物半导体层14的横向宽度窄,但不限于此。栅极电极12的横向宽度可以比氧化物半导体层14的横向宽度大。
在氧化物半导体层14中,在相对于栅极绝缘膜13的界面的一部分中形成第一沟道区域141。更具体地,在俯视图中,该界面上的与源极电极161和漏极电极162之间的间隙重叠的区域是第一沟道区域141。另外,在氧化物半导体层14中,在相对于钝化膜17的界面的一部分中形成第二沟道区域142。更具体地,在俯视图中,该界面上的与顶栅电极18重叠的区域为第二沟道区域142。
与第一实施方式相同,将第一沟道区域的沟道长度设为第一沟道长度LB,将第二沟道区域的沟道长度设为第二沟道长度LT。在本实施方式中,第一沟道长度LB与源极电极161和漏极电极162之间的间隙的横向宽度相等。第二沟道长度LT与顶栅电极18的横向宽度相等。与第一实施方式相同,在本实施方式的氧化物TFT 1中,第二沟道长度LT比第一沟道长度LB短。
另外,在本实施方式中,当驱动氧化物TFT 1时,与第一实施方式相同,对顶栅电极18施加大于或等于源极电极161的电位Vs和漏极电极162的电位Vd中的较低电位的电位。
在本实施方式中,采用与第一实施方式相同的下面的两个结构。即,采用1)第二沟道长度LT比第一沟道长度LB短的结构、以及2)驱动时对顶栅电极18施加大于或等于Vs和Vd中的较低电位的电位的结构。因此,获得与第一实施方式相同的效果。
第三实施方式
图5是示出根据第三实施方式的氧化物TFT 2的结构示例的剖视图。氧化物TFT 2包括基板21、底栅电极22、栅极绝缘膜23、氧化物半导体层24、层间绝缘膜25、顶栅电极26、钝化膜27以及源极及漏极电极28。
图6是示出根据第三实施方式的氧化物TFT 2的结构示例的俯视图。在图6中,示出了底栅电极22、氧化物半导体层24、顶栅电极26以及源极及漏极电极28。
如图5所示,在氧化物TFT 2中,底栅电极22、栅极绝缘膜23、氧化物半导体层24、层间绝缘膜25、顶栅电极26、钝化膜27以及源极及漏极电极28依次层压在基板21上。
基板21为矩形板状。基板21是玻璃基板等绝缘基板。
底栅电极22和顶栅电极26由与第一实施方式的底栅电极12和顶栅电极18的材料相同的材料形成。栅极绝缘膜23、层间绝缘膜25、及钝化膜27由与第一实施方式的栅极绝缘膜13的材料相同的材料形成。氧化物半导体层24由与第一实施方式的氧化物半导体层14的材料相同的材料形成。
源极及漏极电极28包括电极281和电极282这两个电极。根据氧化物TFT 2的操作状态,电极281和电极282这两个电极中的一个电极用作源极电极,另一个电极用作漏极电极。即,在电极281用作源极电极、电极282用作漏极电极的情况下,存在电极281用作漏极电极、电极282用作源极电极的情况。在以下的说明中,为了简便,将电极281称作源极电极281,将电极282称作漏极电极282。源极电极281和漏极电极282为大致相同的形状。
如图5和图6所示,源极电极281和漏极电极282空出间隙地并排设置。源极及漏极电极28由与第一实施方式的源极及漏极电极16的材料相同的材料形成。
如图5所示,在本实施方式的氧化物TFT 2中,底栅电极22的在纸面上的横向方向上的长度(以下,称作横向宽度)比顶栅电极26的横向宽度小。源极电极281和漏极电极282之间的间隙的横向宽度比顶栅电极26的横向宽度大。而且,氧化物半导体层24的横向宽度比源极电极281和漏极电极282之间的间隙大。层间绝缘膜25和钝化膜27中设置有两个接触孔。利用两个接触孔中的一个接触孔,源极电极281相应地电连接到氧化物半导体层24,利用两个接触孔中的另一接触孔,漏极电极282相应地电连接到氧化物半导体层24。因此,本实施方式的氧化物TFT 2是顶栅型TFT。在氧化物TFT 2中,在氧化物半导体层24上形成沟道层。
在氧化物半导体层24中,在相对于层间绝缘膜25的界面的一部分中形成第一沟道区域241。更具体地,在俯视图中,该界面上的与顶栅电极26重叠的区域为第一沟道区域241。第一沟道区域241是这样的区域:载流子密度能够根据顶栅电极26的电压而受控制。另外,在氧化物半导体层24中,在相对于栅极绝缘膜23的界面的一部分中形成第二沟道区域242。更具体地,在俯视图中,该界面上的与底栅电极22重叠的区域为第二沟道区域242。第二沟道区域242是这样的区域:载流子密度能够根据底栅电极22的电压而受控制。
在第一沟道区域241中,将源极电极281和漏极电极282的并排设置方向上的长度、即图5和图6的纸面上的横向方向上的长度LT称作第一沟道长度。在第二沟道区域142中,将该并排设置方向上的长度LB称作第二沟道长度。如图5和图6所示,在本实施方式的氧化物TFT 2中,第二沟道长度LB比第一沟道长度LT短。
在本实施方式中,当驱动如上构造的氧化物TFT 2时,对底栅电极22施加大于或等于源极电极281的电位Vs和漏极电极282的电位Vd中的较低电位的电位。底栅电极22的电位由Vbg表示。如上所述的该实施方式的氧化物TFT 2的特性由下面的式(4)和式(5)或下面的式(4)和式(6)表示。
LT>LB…(4)
其中,
LT:第一沟道长度
LB:第二沟道长度
Vbg≥Vs且Vs<Vd…(5)
Vbg≥Vd且Vs>Vd…(6)
其中,
Vbg:底栅电极22的电位
Vs:源极电极281的电位
Vd:漏极电极282的电位
在本实施方式中,通过1)第二沟道长度LB比第一沟道长度LT短的结构、以及2)驱动氧化物TFT 2以使底栅电极22的电位Vbg大于或等于源极电极281的电位Vs和漏极电极282的电位Vd中的较低电位的结构,获得以下的效果。即使在氧化物TFT 2上产生电荷的情况下,初始特性稳定。具体地,能够抑制氧化物TFT 2从断开切换到接通的栅极电压的波动、即阈值电压的波动。
另外,当对氧化物TFT 2施加正栅极应力时,在底栅电极22的电位Vbg小于源极电极281的电位Vs和漏极电极282的电位Vd中的较低电位的情况下,阈值电压的波动具有加速的倾向。然而,在本实施方式中,Vbg大于或等于Vs和Vd中的较低电位,由此能够抑制阈值电压的波动。即,氧化物TFT 2的操作可靠性提高。
电路示例1
下面对使用上述的氧化物TFT的电路的几个例子进行说明。图7是示出栅极驱动器的输出级的一示例的电路图。栅极驱动器在显示装置等中生成栅极信号(扫描信号)。在图7中,使用第一实施方式或第二实施方式中描述的底栅型氧化物TFT 1作为Tr1和Tr2。第一薄膜晶体管Tr1将第一时钟信号CLK1连接到输出端子OUT1。第二薄膜晶体管Tr2将输出端子OUT1连接到电源VL。
在图7中,例如,在使用两相时钟的情况下,对Tr2的底栅电极施加占空比为50%的正电压。因此,需要针对正栅极应力的稳定性。另外,由于自举效应,Tr1的底栅电极被施加高电压,因此正栅极压力变得更严重。然而,将第一实施方式或第二实施方式中所述的氧化物TFT 1用作Tr1和Tr2,并且对顶栅施加的电位设为比源极电位大,因此,能够获得针对正栅极应力的稳定性。
电路示例2
图8是示出像素电路的一示例的电路图。图8示出了其中的有机发光二极管(OLED)是发光元件的显示装置的像素电路。OLED是包括有机发光层的发光元件。像素电路包括开关TFT(SW TFT)和驱动TFT(DRIVE TFT)。开关TFT根据通过扫描线(SCAN)供给的扫描信号接通和断开。驱动TFT控制流入到OLED中的电流。在开关TFT的阈值电压波动的情况下,存在OLED发光的时刻偏移的担忧。另外,在驱动TFT的阈值电压波动的情况下,存在OLED的亮度产生误差的担忧。这引起显示的闪烁或不均等显示质量的下降。在开关TFT和驱动TFT中使用第一实施方式或第二实施方式中所述的氧化物TFT 1,因此能够有助于像素电路的操作稳定性并防止显示质量的下降。
电路示例3
图9是示出像素电路的一示例的电路图。图9示出液晶显示器(LCD)中的像素电路的示例。在LCD中,多个像素以二维方式布置、更具体地布置成矩阵状。为了确保图的可视性,示出了纵向3个像素乘以横向3个像素共计9个像素的电路。配置在各像素中的TFT S11至S33根据从扫描线G1至G3供给的扫描信号接通和断开。即,TFT是开关元件的一示例。当TFT接通时,与从数据线D1至D3供给的数据信号相对应的电荷被保持于存储电容C1至C33。在LCD中,在各像素的TFT的阈值电压波动的情况下,电荷相对于存储电容的储存变得不充足(写入不充足)。该存储电容的写入不充足引起例如闪烁和显示不均的显示质量的下降。
因此,将第一实施方式或第二实施方式中所述的氧化物TFT 1用作配置于各像素中的TFT。然后,通过将顶栅电极18的电位Vtg设为大于源极电极161的电位Vs,进行控制。图10是示出顶栅电极18的电位的控制示例的图。横轴表示时间,纵轴表示电位。标记有Vcom的图表示共同电位的移位。标记有Vg的图表示顶栅电极18的电位Vtg的移位。标记有Vs的图表示源极电极161的电位Vs的移位。标记有Vpix的图表示在存储电容中的连接到TFT的一侧的端子的电位的移位。Vtg1及Vtg2表示对顶栅电极18施加的电位的控制示例。
标记有Vtg1的图是顶栅电极18的电位Vtg追随源极电极的电位Vs的示例。Vtg可以大于或等于Vs,因此Vtg可以追随Vs。标记有Vtg2的图是顶栅电极18的电位Vtg保持恒定的例子。在将Vtg保持为源极电位Vs的最大值的情况下,Vtg大于或等于Vs。Vs的最大值可以通过计算设计上的理论值来求出或者通过实际测量来求出。另外,考虑误差,也可以将比求出的电位略大的电位用作Vtg。
在LCD的像素电路中使用第一实施方式或第二实施方式所述的氧化物TFT 1,因此能够有助于像素电路的操作稳定性,并防止显示质量的下降。
在电路示例1至电路示例3中,仅说明了使用底栅型TFT的电路示例,但是该示例不限于此。可在使用顶栅型TFT的电路示例中使用第三实施方式中所述的氧化物TFT 2。该情况下,获得的效果与上述获得的效果相同。
第四实施方式
在本实施方式中,对第一实施方式所述的氧化物TFT 1添加设计条件。图11是示出根据第四实施方式的氧化物TFT 1的结构示例的俯视图。在图11中,对与第一实施方式相同的结构标注与第一实施方式的附图标记相同的附图标记。本实施方式的氧化物TFT 1是蚀刻终止型TFT。其与第一实施方式的不同之处在于,设定了第一沟道长度LB为10微米(μm)、沟道宽度W小于或等于10微米的条件。
已知作为表示晶体管的特性的参数之一的W/L。W是沟道宽度,L是沟道长度。在本实施方式中,沟道长度为第一沟道长度LB。制作将第一沟道长度LB设为10微米并且改变沟道宽度W的多个氧化物TFT 1。在沟道宽度W不同的该多个氧化物TFT中,测量由于正栅极应力引起的阈值电压的波动,由此随着W减小,获得良好的结果。因此,随着沟道宽度W减小,获得操作稳定性。即,将第一沟道长度LB设为10微米的情况下,期望沟道宽度W设为小于或等于10微米。
根据本实施方式,对沟道宽度W添加该条件,由此,能够在氧化物TFT 1中更可靠地获得相对于正栅极应力的操作稳定性。此外,将沟道宽度W设定得更小的条件是对于驱动OLED的TFT有利的条件。
第五实施方式
在本实施方式中,对第一实施方式所述的氧化物TFT 1添加了设计条件。图12A和图12B是示出根据第五实施方式的氧化物TFT 1的结构示例的说明图。图12A是示出氧化物TFT 1的结构示例的俯视图。图12B是示出氧化物TFT 1的结构示例的剖视图。在图12A和图12B中,对与第一实施方式相同的结构应用与第一实施方式相同的附图标记。本实施方式的氧化物TFT 1是蚀刻终止型TFT。其与第一实施方式的不同之处在于,设定了这样的条件:在俯视图中第一沟道区域与源极电极161重叠的区域的宽度(以下,重叠宽度)LOVL大于或等于1.5微米。这也适用于第一沟道区域与漏极电极162重叠的区域的宽度。换言之,重叠宽度是蚀刻终止膜15与源极电极161重叠的沟道长度方向上的长度、以及蚀刻终止膜15与漏极电极162重叠的沟道长度方向上的长度。
可认为,氧化物TFT 1的操作稳定性是根据第一沟道长度LB和第二沟道长度LT之间的差值获得的。因此,随着该差值增大,获得效果。在重叠宽度LOVL增大的情况下,第二沟道长度LT减小。在重叠宽度LOVL增大的情况下,第一沟道长度LB不变化。因此,可认为,第一沟道长度LB和第二沟道长度LT之间的差值增大,由此氧化物TFT 1的操作稳定性提高。在氧化物TFT 1中,在第一沟道长度LB设为10微米的情况下,理想的是将重叠宽度LOVL设为大于或等于1.5微米。
根据本实施方式,对重叠宽度LOVL添加该条件,由此能够在氧化物TFT 1中更可靠地获得针对正栅极应力的操作稳定性。此外,将重叠宽度LOVL设定为更大的条件是对于需要增大沟道宽度W的TFT有利的条件。
第六实施方式
在本实施方式中,对第二实施方式所述的氧化物TFT 1添加了设计条件。图13A和图13B是示出根据第六实施方式的氧化物TFT 1的结构示例的说明图。图13A是示出氧化物TFT 1的结构示例的俯视图。图13B是示出氧化物TFT 1的结构示例的剖视图。在图13A和图13B中,对与第二实施方式相同的结构应用与第二实施方式相同的附图标记。本实施方式的氧化物TFT 1是沟道蚀刻型TFT。其与第二实施方式的不同之处在于,设定了以下这样的条件:在俯视图中源极电极161和顶栅电极18之间的间隙的距离(以下,间隙宽度)LOFF以及漏极电极162和顶栅电极18之间的间隙的距离大于或等于1.5微米。
可认为,氧化物TFT 1的操作稳定性是根据第一沟道长度LB和第二沟道长度LT之间的差值获得的。因此,随着该差值越大,获得效果。在源极电极161和漏极电极162之间的间隙的距离不变的限制的基础上,在间隙宽度LOFF增大的情况下,第二沟道长度LT减小。在间隙宽度LOFF增大的情况下,第一沟道长度LB不变。因此,可认为,第一沟道长度LB和第二沟道长度LT之间的差值增大,由此氧化物TFT 1的操作稳定性提高。在氧化物TFT 1中,在第一沟道长度LB设为10微米的情况下,理想的是将间隙宽度LOFF设为大于或等于1.5微米。
根据本实施方式,对间隙宽度LOFF添加了该条件,由此,能够在氧化物TFT 1中更可靠地获得针对正栅极应力的操作稳定性。此外,将间隙宽度LOFF设定为更大的条件是对于需要增大沟道宽度W的TFT有利的条件。
第七实施方式
在本实施方式的氧化物TFT 1中,对第一实施方式的氧化物TFT 1添加了设计条件。图14A和图14B是示出根据第七实施方式的氧化物TFT 1的结构示例的说明图。图14A是示出氧化物TFT 1的结构示例的俯视图。图14B是沿图14A的线XIV-XIV剖开的剖视图。在图14A和图14B中,对与第一实施方式相同的结构应用与第一实施方式相同的附图标记。本实施方式的氧化物TFT 1是蚀刻终止型TFT。其与第一实施方式的不同之处在于设定了以下这样的条件:在俯视图中第一沟道区域与源极电极161重叠的区域的宽度(以下,源极卷绕宽度)LSOVL比第一沟道区域与漏极电极162重叠的区域的宽度(以下,漏极卷绕宽度)LDOVL大的条件。
另外,在本实施方式中,形成这样的部分,在该部分中,在俯视图中,构成底栅电极12的层与构成源极电极161的层重叠,由此在底栅电极12和源极电极161之间构成了电容器Cst。图14A和14B示出了氧化物TFT 1和电容器Cst这两个元件。端子tm1表示与栅极电极12和电容器Cst连接的端子,端子tm2表示与漏极电极连接的端子。
图15A和图15B是示出使用氧化物TFT 1的电路示例的电路图。图15A示出栅极驱动器的输出级的电路示例。图15B示出OLED的像素电路的示例。可通过图14A和图14B所示的结构实现图15A所示的Tr3和电容器Cst。另外,图15B所示的Tr4和电容器Cst也可以通过图14A和图14B所示的结构实现。图15A和图15B所示的端子tm1和tm2对应于图14A和图14B所示的端子tm1和tm2。在使用本实施方式的氧化物TFT 1作为Tr3和Tr4的情况下,根据图14A和图14B所示的结构,能够有效地制作氧化物TFT 1和电容器Cst。
另外,在氧化物TFT 1中,通过增大连接到电容器Cst的源极侧上的源极卷绕宽度LSOVL,获得以下的效果。与上述的其他的实施方式相同,针对正栅极应力的操作稳定性提高。另外,源极卷绕宽度LSOVL增大,由此用作电容器Cst的区域增大。因此,能够减小电容器Cst的结构所需的平面面积,因此能够减小氧化物TFT 1与电容器Cst组合的结构所需的平面面积。
在用于OLED的像素电路的情况下氧化物TFT 1与电容器Cst组合的结构所需的平面面积减小,由此开口率提高。另外,能够减小各像素,由此能够提高显示器的清晰度。
驱动电路示例
接下来,对氧化物TFT 1的驱动电路进行说明。图16是示出驱动电路100的一示例的电路图。驱动电路100包括TFT电路101和施加电路102。TFT电路101是包括氧化物TFT 1的电路。TFT电路101的结构根据氧化物TFT 1的用途适当地设计。另外,可对氧化物TFT 2的驱动电路应用相同的结构。
施加电路102是产生施加于氧化物TFT 1的顶栅电极18的电位的电路。施加电路102包括比较器1021、开关1022以及缓冲器1023。比较器1021判断Vs和Vd之间的大小关系。Vs是氧化物TFT 1的源极电极161的电位。Vd是氧化物TFT 1的漏极电极162的电位。开关1022是切换开关。Vs和Vd输入到开关1022,Vs和Vd之一从开关1022输出。开关1022的切换根据比较器1021的输出进行控制。根据比较器1021的控制,开关1022输出Vs和Vd中的较低的电位。缓冲器1023将开关1022的输出输入到TFT电路101。该输入被施加到氧化物TFT 1的顶栅电极18。另外,缓冲器1023可以用放大器替换。
在各氧化物TFT 1上设置一个施加电路102,但是施加电路102的数量不限于此。在电路包括多个氧化物TFT 1、但是所述多个氧化物TFT 1不同时操作的情况下,可设置一个施加电路102。另外,在所述多个氧化物TFT 1同时操作的情况下,在设计上,在操作条件相同的情况下,可以设置一个施加电路102。即,存在要对操作的氧化物TFT 1的顶栅电极18施加的所有的电位可以在设计上为相同电位的情况。该情况下,对于同时操作的氧化物TFT 1中的一个氧化物TFT 1,将Vs和Vd设为施加电路102的输入。施加电路102的输出被施加到操作的所有的氧化物TFT的顶栅电极。另外,在能够在设计上唯一确定要对氧化物TFT 1的顶栅电极18施加的电位的情况下,将施加电路102设为恒定电压源。该情况下,将恒定电位施加于顶栅电极18。
另外,在上面的描述中参照的剖视图是为了说明各层的层压顺序,各层的厚度或大小、各层间的厚度的尺寸(大小关系)不限于图示的方式。
各实施方式中所述的技术特征(结构要求)能够相互组合,根据该组合,能够形成新的技术特征。
在此公开的实施方式在所有的方面是示例,而不必认为是限制性的。本发明的范围不限于上述描述,而由权利要求书表示,并且旨在包括权利要求书的所有等同物和权利要求书内的所有变更。
Claims (15)
1.一种薄膜晶体管,包括:
源极电极及漏极电极;
由氧化物半导体形成的沟道层,所述沟道层与所述源极电极和所述漏极电极接触;
第一绝缘膜和第一栅极电极,所述第一绝缘膜和所述第一栅极电极形成在所述沟道层的第一面侧上,所述第一面侧不与所述源极电极和所述漏极电极接触;
第一沟道区域,所述第一沟道区域在所述沟道层和所述第一绝缘膜之间的第一界面上,从所述源极电极和所述沟道层彼此接触的边缘到所述漏极电极和所述沟道层彼此接触的边缘而形成;
第二绝缘膜和第二栅极电极,所述第二绝缘膜和所述第二栅极电极形成在所述沟道层的第二面侧上,所述第二面侧与所述源极电极和所述漏极电极接触;以及
第二沟道区域,所述第二沟道区域在所述沟道层和所述第二绝缘膜之间的第二界面上,形成于从所述第二栅极电极与所述沟道层重叠的区域中除去所述源极电极及所述漏极电极与所述沟道层重叠的区域得到的区域,
其中,所述源极电极和所述漏极电极空出间隙地并排设置,
在将所述第一沟道区域的在所述源极电极和所述漏极电极的并排设置方向上的长度设为第一沟道长度、将所述第二沟道区域的在所述并排设置方向上的长度设为第二沟道长度的情况下,
所述第二沟道长度比所述第一沟道长度短,并且
施加于所述第二栅极电极的电位大于或等于所述源极电极和所述漏极电极的电位中的较低电位。
2.根据权利要求1所述的薄膜晶体管,其中,
所述薄膜晶体管是蚀刻终止型晶体管,其中,所述第二绝缘膜由与所述沟道层的所述第二面侧接触的蚀刻终止膜和与所述蚀刻终止膜的上表面接触的钝化膜组成。
3.根据权利要求2所述的薄膜晶体管,其中,
在沟道长度方向上所述蚀刻终止膜与所述源极电极重叠的长度、以及在所述沟道长度方向上所述蚀刻终止膜与所述漏极电极重叠的长度均大于或等于1.5微米。
4.根据权利要求2或3所述的薄膜晶体管,其中,
在所述沟道长度方向上所述蚀刻终止膜与所述源极电极重叠的长度比在所述沟道长度方向上所述蚀刻终止膜与所述漏极电极重叠的长度长。
5.根据权利要求1所述的薄膜晶体管,其中,
所述薄膜晶体管是沟道蚀刻型晶体管,其中,所述第二绝缘膜为与所述沟道层的所述第二面侧接触的钝化膜,以及
所述第二栅极电极的长度比所述源极电极的边缘和所述漏极电极的边缘之间的长度短。
6.根据权利要求5所述的薄膜晶体管,其中,
从所述源极电极的所述边缘和所述漏极电极的所述边缘到所述第二栅极电极的边缘的长度大于或等于1.5微米。
7.一种薄膜晶体管,包括:
依次形成的第一栅极电极、第一绝缘膜、由氧化物半导体组成的沟道层、第二绝缘膜、第二栅极电极、钝化膜、源极电极及漏极电极,
第一沟道区域,在所述第一沟道区域中,在所述沟道层和所述第一绝缘膜之间的第一界面上,所述第一栅极电极和所述沟道层重叠;以及
第二沟道区域,在所述第二沟道区域中,在所述沟道层和所述第二绝缘膜之间的第二界面上,所述第二栅极电极和所述沟道层重叠;
其中,所述源极电极和所述漏极电极与不包括所述第二沟道区域的沟道层区域接触并空出间隙并排设置,
在将所述第一沟道区域的在所述源极电极和所述漏极电极的并排设置方向上的长度设为第一沟道长度、所述第二沟道区域的在所述并排设置方向上的长度设为第二沟道长度的情况下,
所述第二沟道长度比所述第一沟道长度长,并且
对所述第一栅极电极施加的电位大于或等于所述源极电极和所述漏极电极的电位中的较低电位。
8.根据权利要求1至7中任一项所述的薄膜晶体管,其中,
沟道宽度小于或等于10微米。
9.一种显示装置,包括:
多个像素,所述多个像素分别包括具有根据权利要求1至8中任一项所述的薄膜晶体管的开关元件、以及显示元件,并且所述多个像素以二维方式设置;以及
施加电路,所述施加电路对所述开关元件的第二栅极电极施加所述开关元件的源极电极和漏极电极的电位中的较低电位。
10.一种晶体管电路,包括多个薄膜晶体管,其中,所述多个薄膜晶体管中的每一个薄膜晶体管是根据权利要求1至8中任一项所述的薄膜晶体管。
11.根据权利要求10所述的晶体管电路,包括:
由所述薄膜晶体管构成的第一薄膜晶体管将第一时钟信号连接到输出端子;以及
由所述薄膜晶体管构成的第二薄膜晶体管将所述输出端子连接到电源。
12.根据权利要求10所述的晶体管电路,还包括:
发光元件,所述发光元件包括有机发光层;
电容;
其中:
由所述薄膜晶体管构成的驱动晶体管使与所述电容的电压相对应的电流流入所述发光元件中;以及
由所述薄膜晶体管构成的开关晶体管控制所述驱动晶体管的操作。
13.一种薄膜晶体管的驱动方法,包括:
检测根据权利要求1至8中任一项所述的薄膜晶体管的源极电极的电位和漏极电极的电位;
确定检测到的所述源极电极的电位和检测到的所述漏极电极的电位中的较低电位,
生成大于或等于所确定的电位的电位;以及
对所述薄膜晶体管的第二栅极电极施加生成的所述电位。
14.根据权利要求13所述的薄膜晶体管的驱动方法,还包括:
驱动由将第一时钟信号连接到输出端子的所述薄膜晶体管构成的第一薄膜晶体管和由将所述输出端子连接到电源的所述薄膜晶体管构成的第二薄膜晶体管。
15.根据权利要求13所述的薄膜晶体管的驱动方法,还包括:
驱动电容、由所述薄膜晶体管构成的驱动晶体管和由所述薄膜晶体管构成的开关晶体管,所述驱动晶体管使与所述电容的电压相对应的电流流入有机发光层中,以及所述开关晶体管控制所述驱动晶体管的操作。
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