JP2018098364A - 薄膜トランジスタ、表示装置、トランジスタ回路及び薄膜トランジスタの駆動方法 - Google Patents
薄膜トランジスタ、表示装置、トランジスタ回路及び薄膜トランジスタの駆動方法 Download PDFInfo
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- JP2018098364A JP2018098364A JP2016241604A JP2016241604A JP2018098364A JP 2018098364 A JP2018098364 A JP 2018098364A JP 2016241604 A JP2016241604 A JP 2016241604A JP 2016241604 A JP2016241604 A JP 2016241604A JP 2018098364 A JP2018098364 A JP 2018098364A
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- thin film
- film transistor
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Abstract
【解決手段】酸化物半導体薄膜トランジスタは、ソース電極及びドレイン電極と、酸化物半導体から成るチャネル層と、第1の絶縁膜と、第1の絶縁膜のチャネル層との界面に形成される第1のチャネル領域に対向する面側に形成された第1のゲート電極と、第2の絶縁膜と、第2の絶縁膜のチャネル層との界面に形成される第2のチャネル領域に対向する面側に形成された第2のゲート電極とを備え、第1のチャネル領域におけるソース電極及びドレイン電極の並置方向の長さを第1のチャネル長とし、第2のチャネル領域における並置方向の長さを第2のチャネル長とした場合、第2のチャネル長が、第1のチャネル長よりも短く、かつ、第2のゲート電極に印加される電位が、ソース電極又はドレイン電極の電位のうちの低い方の電位以上である。
【選択図】図1
Description
表示装置において、駆動回路の小型化と配線の微細化は、画素の開口率の向上に貢献する。その結果、表示装置の高解像度化が可能となる。
本開示の一側面は、TFT上の電荷発生に対して特性を安定化可能な薄膜トランジスタ等を提供することを目的とする。
図1は酸化物TFT1の第1の実施の形態に係る構成例を示す断面図である。酸化物TFT1は基板11、ボトムゲート電極12、ゲート絶縁膜13、酸化物半導体層14、エッチストップ膜15、ソース及びドレイン電極16、パッシベーション膜17、並びにトップゲート電極18を含む。図2は酸化物TFT1の第1の実施の形態に係る構成例を示す平面図である。図2においては、ボトムゲート電極12、酸化物半導体層14、エッチストップ膜15、ソース及びドレイン電極16、並びにトップゲート電極18を示している。なお、ソース及びドレイン電極16、トップゲート電極18、ボトムゲート電極12は、図示しないコンタクトホールを通し外部の回路と接続している。
但し、
LB:第1のチャネル長
LT:第2のチャネル長
Vtg≦Vd かつ Vs>Vd … (3)
但し
Vtg:トップゲート電極18の電位
Vs:ソース電極161の電位
Vd:ドレイン電極162の電位
図3は酸化物TFT1の第2の実施の形態に係る構成例を示す断面図である。酸化物TFT1は基板11、ボトムゲート電極12、ゲート絶縁膜13、酸化物半導体層14、ソース及びドレイン電極16、パッシベーション膜17、並びにトップゲート電極18を含む。図4は酸化物TFT1の第2の実施の形態に係る構成例を示す平面図である。図4においては、ボトムゲート電極12、酸化物半導体層14、ソース及びドレイン電極16、及びトップゲート電極18を示している。図3及び図4において、実施の形態1と同様な機能を持つ構成要素には同一の符号を付与している。以下の説明においては、実施の形態1と異なる点を主に説明する。
図5は酸化物TFT1の第3の実施の形態に係る構成例を示す断面図である。酸化物TFT2は基板21、ボトムゲート電極22、ゲート絶縁膜23、酸化物半導体層24、層間絶縁膜25、トップゲート電極26、パッシベーション膜27、並びにソース及びドレイン電極28を含む。
図6は酸化物TFT1の第3の実施の形態に係る構成例を示す平面図である。図6においては、ボトムゲート電極22、酸化物半導体層24、トップゲート電極26、並びにソース及びドレイン電極28を示している。
但し、
LT:第1のチャネル長
LB:第2のチャネル長
Vbg≦Vd かつ Vs>Vd … (6)
但し
Vbg:ボトムゲート電極22の電位
Vs:ソース電極281の電位
Vd:ドレイン電極282の電位
上述の酸化物TFTを用いた回路について、幾つかの例を以下に示す。図7はゲートドライバの出力段の一例を示す回路図である。ゲートドライバは表示装置などにおいて、ゲート信号(走査信号、スキャン信号)を生成する。図7において、Tr1及びTr2は実施の形態1又は2で示したボトムゲート型の酸化物TFT1を用いている。Tr1(第1の薄膜トランジスタ)は第1のクロック信号CLK1と出力端子OUT1とを接続する。Tr2(第2の薄膜トランジスタ)は出力端子OUT1と電源VLとを接続する。
図8は画素回路の一例を示す回路図である。図8はOLED(Organic Light Emitting Diode:有機発光ダイオード)を発光素子とする表示装置の画素回路を示している。OLEDは有機発光層を有する発光素子である。画素回路はスイッチングTFT(SW TFT)と駆動TFT(DRIVE TFT)とを含む。スイッチングTFTは走査線(SCAN)により供給される走査信号によりオン・オフされる。駆動TFTはOLEDに流れる電流を制御する。スイッチングTFTの閾値電圧が変動するとOLEDの発光するタイミングにずれが生じるおそれがある。また、駆動TFTの閾値電圧が変動すると、OLEDの輝度に誤差が発生するおそれがある。これらは表示のちらつきやムラなどの表示品位の低下につながる。スイッチングTFTと駆動TFTとに実施の形態1又は2に示した酸化物TFT1を用いることにより、画素回路の動作安定性に寄与し、表示品位の低下を防ぐことが可能となる。
図9は画素回路の一例を示す回路図である。図9はLCD(Liquid Crystal Display:液晶ディスプレイ)における画素回路の例を示している。LCDにおいては複数の画素が2次元的に、より詳しくはマトリクス状に配列している。図の視認性を確保するため、縦3画素×横3画素の計9画素分の回路を示している。各画素に配置されるTFT(S11からS33)は走査線(G1からG3)により供給される走査信号によりオン・オフされる。すなわち、TFTはスイッング素子の一例である。TFTがオンのときに、データ線(D1からD3)から供給されるデータ信号に応じた電荷が、蓄積容量(C1からC33)に保持される。LCDにおいて各画素のTFTの閾値電圧が変動すると、蓄積容量へ電荷の蓄積が不十分(書き込み不足)となる。この蓄積容量の書き込み不足は、ちらつき、表示ムラといって表示品位低下の原因となる。
本実施の形態は、実施の形態1に示した酸化物TFT1に設計条件を付加した形態である。図11は酸化物TFT1の第4の実施形態に係る構成例を示す平面図である。図11において、実施の形態1と同様な構成については、実施の形態1と同一の符号を付与した。本実施の形態の酸化物TFT1はエッチストップ型のTFTである。実施の形態1と異なるのは、第1のチャネル長LBが10ミクロン(μm)、チャネル幅Wが10ミクロン以下との条件が付されていることである。
本実施の形態は、実施の形態1に示した酸化物TFT1に設計条件を付加した形態である。図12は酸化物TFT1の第5の実施形態に係る構成例を示す説明図である。図12Aは酸化物TFT1の構成例を示す平面図である。図12Bは酸化物TFT1の構成例を示す断面図である。図12A及び図12Bにおいて、実施の形態1と同様な構成については、実施の形態1と同一の符号を付与した。本実施の形態の酸化物TFT1はエッチストップ型のTFTである。実施の形態1と異なるのは、平面視において、第1のチャネル領域とソース電極161とが重なる領域の幅(以下、オーバラップ幅)LOVLが、1.5ミクロン以上との条件が付されていることである。第1のチャネル領域とドレイン電極162とが重なる領域の幅も同様とする。オーバラップ幅は言い換えると、エッチストップ膜15とソース電極161とが重なり合うチャネル長方向の長さ、及びエッチストップ膜15とドレイン電極162とが重なり合うチャネル長方向の長さである。
本実施の形態は、実施の形態2に示した酸化物TFT1に設計条件を付加した形態である。図13は酸化物TFT1の第6の実施形態に係る構成例を示す説明図である。図13Aは酸化物TFT1の構成例を示す平面図である。図13Bは酸化物TFT1の構成例を示す断面図である。図13A及び図13Bにおいて、実施の形態2と同様な構成については、実施の形態2と同一の符号を付与した。本実施の形態の酸化物TFT1はチャネルエッチ型のTFTである。実施の形態2と異なるのは、平面視において、ソース電極161とトップゲート電極18との隙間及びドレイン電極162とトップゲート電極18との隙間の距離(以下、ギャップ幅)LOFFが、1.5ミクロン以上との条件が付されていることである。
本実施の形態の酸化物TFT1は実施の形態1に示した酸化物TFT1に設計条件を付加した形態である。図14は酸化物TFT1の第7の実施形態に係る構成例を示す説明図である。図14Aは酸化物TFT1の構成例を示す平面図である。図14Bは図14AのXIV−XIV線による断面図である。図14A及び14Bにおいて、実施の形態1と同様な構成については、実施の形態1と同一の符号を付与した。本実施の形態の酸化物TFT1は実施の形態1とエッチストップ型のTFTである。実施の形態1と異なるのは、平面視において、第1のチャネル領域とソース電極161とが重なる領域の幅(以下、ソースラップ幅)LSOVLが、第1のチャネル領域とドレイン電極162とが重なる領域の幅(以下、ドレインラップ幅)LDOVLよりも大きいとの条件が付されていることである。
次に、酸化物TFT1の駆動回路について、説明する。図16は駆動回路100の一例を示す回路図である。駆動回路100はTFT回路101及び印加回路102を含む。TFT回路101は酸化物TFT1を含む回路である。TFT回路101の構成は、酸化物TFT1の用途により、適宜設計する。また、酸化物TFT2の駆動回路についても、同様に構成可能である。
11 基板
12 ボトムゲート電極
13 ゲート絶縁膜
14 酸化物半導体層
141 第1のチャネル領域
142 第2のチャネル領域
LB 第1のチャネル長
LT 第2のチャネル長
15 エッチストップ膜
16 ソース及びドレイン電極
161 ソース電極
162 ドレイン電極
17 パッシベーション膜
18 トップゲート電極
2 酸化物TFT
21 基板
22 ボトムゲート電極
23 ゲート絶縁膜
24 酸化物半導体層
241 第1のチャネル領域
242 第2のチャネル領域
LT 第1のチャネル長
LB 第2のチャネル長
25 層間絶縁膜
26 トップゲート電極
27 パッシベーション膜
28 ソース及びドレイン電極
281 ソース電極
282 ドレイン電極
Cst キャパシタ
Claims (15)
- ソース電極及びドレイン電極と、
前記ソース電極及びドレイン電極が接続された酸化物半導体から成るチャネル層と、
前記チャネル層の第1の面側に形成された第1の絶縁膜と、
前記第1の絶縁膜の前記チャネル層との第1の界面に形成される第1のチャネル領域に対向する面側に形成された第1のゲート電極と、
前記チャネル層の第2の面側に形成された第2の絶縁膜と、
前記第2の絶縁膜の前記チャネル層との第2の界面に形成される第2のチャネル領域に対向する面側に形成された第2のゲート電極と
を備え、
前記ソース電極及びドレイン電極は間隙を間にして並置してあり、
前記第1のチャネル領域における前記ソース電極及びドレイン電極の並置方向の長さを第1のチャネル長とし、前記第2のチャネル領域における前記並置方向の長さを第2のチャネル長とした場合、
前記第2のチャネル長が、前記第1のチャネル長よりも短く、かつ、
前記第2のゲート電極に印加される電位が、前記ソース電極又は前記ドレイン電極の電位のうちの低い方の電位以上である
ことを特徴とする薄膜トランジスタ。 - 前記第2の絶縁膜が、前記チャネル層の上面に接するように形成されたエッチストップ膜と前記エッチストップ膜の上面に接するように形成されたパッシベーション膜とからなる、
エッチストップ型トランジスタである
ことを特徴とする請求項1に記載の薄膜トランジスタ。 - 前記エッチストップ膜と前記ソース電極とが重なり合うチャネル長方向の長さ、及び前記エッチストップ膜と前記ドレイン電極とが重なり合うチャネル長方向の長さが、共に1.5ミクロン以上である
ことを特徴とする請求項2に記載の薄膜トランジスタ。 - 前記エッチストップ膜と前記ソース電極とが重なり合うチャネル長方向の長さが、前記エッチストップ膜と前記ドレイン電極とが重なり合うチャネル長方向の長さよりも長い
こと特徴とする請求項2又は請求項3に記載の薄膜トランジスタ。 - 前記第2の絶縁膜は単一の工程で形成された単層膜であり、前記ソース電極及びドレイン電極は前記第1の絶縁膜又は前記チャネル層に接するように積層されたチャネルエッチ型トランジスタであり、
前記第2のゲート電極の長さが、前記ソース電極とドレイン電極のエッジ間の長さよりも短い
ことを特徴とする請求項1に記載の薄膜トランジスタ。 - 前記ソース電極とドレイン電極のエッジから前記第2のゲート電極のエッジまでの長さが1.5ミクロン以上である
ことを特徴とする請求項5に記載の薄膜トランジスタ。 - 前記ソース電極及びドレイン電極が前記チャネル層に対して、前記第1のゲート電極と同じ側に位置するトップゲート型トランジスタである
ことを特徴とする請求項1に記載の薄膜トランジスタ。 - チャネル幅が10ミクロン以下である
ことを特徴とする請求項1から請求項7のいずれか一項に記載の薄膜トランジスタ。 - 請求項1から請求項8のいずれか一項に記載の薄膜トランジスタを含むスイッチング素子及び表示素子をそれぞれ有し、2次元的に配列した複数の画素と、
前記スイッチング素子の第2のゲート電極に、前記スイッチング素子のソース電極又はドレイン電極の電位のうちの低い方の電位を印加する印加回路と
を備えることを特徴とする表示装置。 - 請求項1から請求項8のいずれか一項に記載の薄膜トランジスタを含み、
複数の薄膜トランジスタから構成されるトランジスタ回路。 - 第1のクロック信号と出力端子とを接続する前記薄膜トランジスタで構成した第1の薄膜トランジスタと、
前記出力端子と電源とを接続する前記薄膜トランジスタで構成した第2の薄膜トランジスタと
を備えることを特徴とする請求項10に記載のトランジスタ回路。 - 有機発光層を有する発光素子と、
容量と、
前記容量の電圧に応じた電流を前記発光素子に流す前記薄膜トランジスタで構成した駆動トランジスタと、
前記駆動トランジスタの動作を制御する前記薄膜トランジスタで構成したスイッチングトランジスタと
を備えることを特徴とする請求項10に記載のトランジスタ回路。 - 請求項1から請求項8のいずれか一項に記載の薄膜トランジスタのソース電極及びドレイン電極の電位を検出し、
検出したソース電極の電位及びドレイン電極の電位のうち、低い方の電位を特定し、
特定した電位以上の電位を生成し、
生成した電位を前記薄膜トランジスタの第2のゲート電極に印加する
ことを特徴とする薄膜トランジスタの駆動方法。 - 第1のクロック信号と出力端子とを接続する前記薄膜トランジスタで構成した第1の薄膜トランジスタと、前記出力端子と電源とを接続する前記薄膜トランジスタで構成した第2の薄膜トランジスタとを駆動する
ことを特徴とする請求項13に記載の薄膜トランジスタの駆動方法。 - 容量と、前記容量の電圧に応じた電流を備える有機発光層に流す前記薄膜トランジスタで構成した駆動トランジスタと、前記駆動トランジスタの動作を制御する前記薄膜トランジスタで構成したスイッチングトランジスタとを駆動する
こと特徴とする請求項13に記載の薄膜トランジスタの駆動方法。
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