CN202679313U - Multiplier circuit - Google Patents
Multiplier circuit Download PDFInfo
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- CN202679313U CN202679313U CN 201220370128 CN201220370128U CN202679313U CN 202679313 U CN202679313 U CN 202679313U CN 201220370128 CN201220370128 CN 201220370128 CN 201220370128 U CN201220370128 U CN 201220370128U CN 202679313 U CN202679313 U CN 202679313U
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Abstract
The utility model relates to a multiplier circuit. The multiplier circuit comprises a first signal input end, a second signal input end, an output end, a power supply end, a ground end, a main control circuit connected with the first signal input end, the second signal input end, the power supply end and the ground end, a reference circuit connected with the power supply end and the ground end, and a frequency synthesizer circuit connected with the main control circuit, the reference circuit, the output end, the power supply end and the ground end. The multiplier circuit has the characteristics of simple structure, easiness in cascade connection and accuracy in frequency doubling.
Description
Technical field
The utility model relates to a kind of frequency multiplier, espespecially a kind of simple in structure, be easy to accurately frequency multiplier circuit of cascade, frequency multiplication.
Background technology
Frequency multiplier is to make output signal frequency equal the circuit of frequency input signal integral multiple, be used for realizing frequency signal is doubled, usually as the work clock of digital circuit, require frequency multiplier to possess high accuracy, low noise characteristics, the multiple of the relative input clock of output clock is called the frequency multiplication number of times.
Existing frequency multiplier is generally selected phase-locked loop structures, and satisfying high accuracy, low noise requirement, but it is large to have the chip expense, the shortcomings such as difficult design, therefore be necessary to provide a kind of simple in structure, chip area is little, be easy to the frequency multiplier of cascade.
Summary of the invention
In view of above content, be necessary to provide a kind of simple in structure, be easy to cascade, frequency multiplication frequency multiplier circuit accurate and with low cost.
A kind of frequency multiplier circuit, comprise a first signal input, one secondary signal input, one output, one power end, one earth terminal, described frequency multiplier circuit also comprises a governor circuit that links to each other with described first signal input, described secondary signal input, described power end, described earth terminal, one reference circuit that links to each other with described power end, described earth terminal, a frequency synthesizer circuit that links to each other with described governor circuit, described reference circuit, described output, described power end, described earth terminal.Described governor circuit comprises first field effect transistor that links to each other with described first signal input, one the second field effect transistor that links to each other with described secondary signal input, one the 3rd field effect transistor that links to each other with described the first field effect transistor and described the second field effect transistor, one with described the first field effect transistor, the 4th field effect transistor that described the 3rd field effect transistor and described power end link to each other, one with described the second field effect transistor, described the 3rd field effect transistor, the 5th field effect transistor that described the 4th field effect transistor and described power end link to each other, described reference circuit comprises the 6th field effect transistor that links to each other with described earth terminal, one the 7th field effect transistor that links to each other with described the 6th field effect transistor, one with described the 6th field effect transistor, the 8th field effect transistor that described the 7th field effect transistor and described power end link to each other, described frequency synthesizer circuit comprise one with described the 3rd field effect transistor, described the 4th field effect transistor, described the 5th field effect transistor, described the 6th field effect transistor, described the 7th field effect transistor, the comparator that described the 8th field effect transistor and described output link to each other.
Relative prior art, frequency multiplier circuit of the present invention can be realized accurate two frequencys multiplication, has with characteristics roomy, simple in structure, that be easy to cascade.
Description of drawings
Fig. 1 is the Organization Chart of the utility model frequency multiplier circuit preferred embodiments.
Fig. 2 is the circuit diagram of the utility model frequency multiplier circuit preferred embodiments.
Embodiment
See also Fig. 1, the better implementation of the utility model frequency multiplier circuit comprises a first signal input Vin, one secondary signal input Vip, one output end vo ut, one power end VCC, one earth terminal GND, one with described first signal input Vin, described secondary signal input Vip, described power end VCC, the governor circuit that described earth terminal GND links to each other, one with described power end VCC, the reference circuit that described earth terminal GND links to each other, one with described governor circuit, described reference circuit, described output end vo ut, described power end VCC, the frequency synthesizer circuit that described earth terminal GND links to each other.
Please consult simultaneously Fig. 2, Fig. 2 is the circuit framework figure of frequency multiplier circuit preferred embodiments of the present invention.Wherein, this governor circuit comprises one first field effect transistor M1, one second field effect transistor M2, one the 3rd field effect transistor M3, one the 4th field effect transistor M4, one the 5th field effect transistor M5, this reference circuit comprises one the 6th field effect transistor M6, one the 7th field effect transistor M7, one the 8th field effect transistor M8, and this frequency synthesizer circuit comprises a comparator C MP.
The annexation of the utility model frequency multiplier circuit preferred embodiments is as follows: the grid of this first field effect transistor M1 links to each other with this first signal input Vin, the grid of this second field effect transistor M2 links to each other with this secondary signal input Vip, the source electrode of this first field effect transistor M1, the source electrode of this second field effect transistor M2, the grid of the 3rd field effect transistor M3 and drain electrode, the grid of the 4th field effect transistor M4, the grid of the 5th field effect transistor M5 links to each other jointly with the positive input V1 of this comparator C MP, the drain electrode of this first field effect transistor M1 links to each other with the drain electrode of the 4th field effect transistor M4, the drain electrode of this second field effect transistor M2 links to each other with the drain electrode of the 5th field effect transistor M5, the grid of the 6th field effect transistor M6 and drain electrode, the source electrode of the 7th field effect transistor M7, the grid of the 8th field effect transistor M8 links to each other jointly with the reverse input end V2 of this comparator C MP, the drain electrode of the 7th field effect transistor M7 links to each other with the drain electrode of the 8th field effect transistor M8, the source electrode of the 3rd field effect transistor M3, the source electrode of the 6th field effect transistor M6 connects earth terminal GND jointly, the source electrode of the 4th field effect transistor M4, the source electrode of the 5th field effect transistor M5, the grid of the 7th field effect transistor M7, the source electrode of the 8th field effect transistor M8 connects power end VCC jointly, and the output of this comparator C MP links to each other with output end vo ut.
The operation principle of the utility model frequency multiplier circuit is as described below: a pair of differential signal of the common input of this first signal input Vin and this secondary signal input Vip is to this governor circuit, obtain output voltage V 1 through after this master control current detecting, this output voltage V 1 enters frequency synthesizer circuit with the reference voltage V 2 of reference circuit and carries out frequency synthesis, obtains the double frequency signal and exports this output end vo ut to.
The breadth length ratio of the 3rd field effect transistor M3 at first is set greater than the 6th field effect transistor M6, as the breadth length ratio that the 3rd field effect transistor M3 is set is two times of the 6th field effect transistor M6, the breadth length ratio that this first field effect transistor M1, this second field effect transistor M2, the 7th field effect transistor M7 are set equates, the breadth length ratio that the 4th field effect transistor M4, the 5th field effect transistor M5, the 8th field effect transistor M8 are set equates, this first signal input Vin and a pair of differential signal of this secondary signal input Vip are set, and its signal swing is that power end VCC is to earth terminal GND.
Now divide three kinds of situations that the operation principle of frequency multiplier circuit is analyzed:
1, when the magnitude of voltage of this first signal input Vin equals the magnitude of voltage of this secondary signal input Vip, this first field effect transistor M1, this second field effect transistor M2, the 4th field effect transistor M4, the equal conducting of the 5th field effect transistor M5, the 3rd field effect transistor M3 flows through maximum current, and namely this moment, this output voltage V 1 was the highest;
2, when the magnitude of voltage of this first signal input Vin during gradually less than the magnitude of voltage of this secondary signal input Vip, the electric current that flows through the 3rd field effect transistor M3 reduces gradually, and namely this moment, this output voltage V 1 also reduced gradually; When the magnitude of voltage of the magnitude of voltage of this first signal input Vin and this secondary signal input Vip reaches maximum negative difference, this first field effect transistor M1, the 4th field effect transistor M4 close fully, this second field effect transistor M2, the 5th field effect transistor M5 keep conducting, the electric current that flows through the 3rd field effect transistor M3 reaches minimum, and namely this moment, this output voltage V 1 was minimum;
3, when the magnitude of voltage of this first signal input Vin during gradually greater than the magnitude of voltage of this secondary signal input Vip, the electric current that flows through the 3rd field effect transistor M3 reduces gradually, and namely this moment, output voltage V 1 also reduced gradually; When the magnitude of voltage of the magnitude of voltage of this first signal input Vin and this secondary signal input Vip reaches maximum positive difference, this first field effect transistor M1, the 4th field effect transistor M4 keep conducting, this second field effect transistor M2, the 5th field effect transistor M5 close fully, the electric current that flows through the 3rd field effect transistor M3 reaches minimum, and namely this moment, this output voltage V 1 was minimum;
By above analysis as seen, output voltage V 1 changes with the difference of the magnitude of voltage of the magnitude of voltage of this first signal input Vin and this secondary signal input Vip, and be inversely proportional to the absolute value of its difference, and in the one-period the inside, the difference of the magnitude of voltage of the magnitude of voltage of this first signal input Vin and this secondary signal input Vip has and reaches maximum twice, be the double frequency information that output voltage V 1 has reflected the magnitude of voltage of the magnitude of voltage of this first signal input Vin and this secondary signal input Vip, the 6th field effect transistor M6, the common reference voltage V 2 that produces of the 7th field effect transistor M7 and the 8th field effect transistor M8, its magnitude of voltage is arranged on the peak of output voltage V 1 and the midrange of minimum, with output voltage V 1, reference voltage V 2 compares by described comparator C MP, thereby output frequency is the double frequency signal of this first signal input Vin and this secondary signal input Vip institute input differential signal.
To sum up, the utility model can be realized accurate two double frequency functions, extracts double frequency information from input differential signal, and is translated into two times of outputs of frequency input signal, and this invention is simple, with low cost, and is easy to cascade.
Claims (3)
1. frequency multiplier circuit, it is characterized in that: comprise a first signal input, one secondary signal input, one output, one power end, one earth terminal, one governor circuit that links to each other with described first signal input, described secondary signal input, described power end, described earth terminal, one reference circuit that links to each other with described power end, described earth terminal, a frequency synthesizer circuit that links to each other with described governor circuit, described reference circuit, described output, described power end, described earth terminal.
2. frequency multiplier circuit as claimed in claim 1, it is characterized in that: described governor circuit comprises first field effect transistor that links to each other with described first signal input, one the second field effect transistor that links to each other with described secondary signal input, one the 3rd field effect transistor that links to each other with described the first field effect transistor and described the second field effect transistor, one with described the first field effect transistor, the 4th field effect transistor that described the 3rd field effect transistor and described power end link to each other, one with described the second field effect transistor, described the 3rd field effect transistor, the 5th field effect transistor that described the 4th field effect transistor and described power end link to each other, described reference circuit comprises the 6th field effect transistor that links to each other with described earth terminal, one the 7th field effect transistor that links to each other with described the 6th field effect transistor, one with described the 6th field effect transistor, the 8th field effect transistor that described the 7th field effect transistor and described power end link to each other, described frequency synthesizer circuit comprise one with described the 3rd field effect transistor, described the 4th field effect transistor, described the 5th field effect transistor, described the 6th field effect transistor, described the 7th field effect transistor, the comparator that described the 8th field effect transistor and described output link to each other.
3. frequency multiplier circuit as claimed in claim 1, it is characterized in that: the grid of described the first field effect transistor links to each other with described first signal input, the grid of described the second field effect transistor links to each other with described secondary signal input, the source electrode of described the first field effect transistor, the source electrode of described the second field effect transistor, the grid of described the 3rd field effect transistor and drain electrode, the grid of described the 4th field effect transistor, the grid of described the 5th field effect transistor links to each other jointly with the positive input of described comparator, the drain electrode of described the first field effect transistor links to each other with the drain electrode of described the 4th field effect transistor, the drain electrode of described the second field effect transistor links to each other with the drain electrode of described the 5th field effect transistor, the grid of described the 6th field effect transistor and drain electrode, the source electrode of described the 7th field effect transistor, the grid of described the 8th field effect transistor links to each other jointly with the reverse input end of described comparator, the drain electrode of described the 7th field effect transistor links to each other with the drain electrode of described the 8th field effect transistor, the source electrode of described the 3rd field effect transistor, the described earth terminal of the common connection of the source electrode of described the 6th field effect transistor, the source electrode of described the 4th field effect transistor, the source electrode of described the 5th field effect transistor, the grid of described the 7th field effect transistor, the described power end of the common connection of the source electrode of described the 8th field effect transistor, the output of described comparator links to each other with described output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220370128 CN202679313U (en) | 2012-07-30 | 2012-07-30 | Multiplier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220370128 CN202679313U (en) | 2012-07-30 | 2012-07-30 | Multiplier circuit |
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| Publication Number | Publication Date |
|---|---|
| CN202679313U true CN202679313U (en) | 2013-01-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201220370128 Expired - Fee Related CN202679313U (en) | 2012-07-30 | 2012-07-30 | Multiplier circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102790587A (en) * | 2012-07-30 | 2012-11-21 | 四川和芯微电子股份有限公司 | Frequency multiplier circuit and system thereof |
-
2012
- 2012-07-30 CN CN 201220370128 patent/CN202679313U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102790587A (en) * | 2012-07-30 | 2012-11-21 | 四川和芯微电子股份有限公司 | Frequency multiplier circuit and system thereof |
| CN102790587B (en) * | 2012-07-30 | 2015-04-08 | 四川和芯微电子股份有限公司 | Frequency multiplier circuit and system thereof |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP02 | Change in the address of a patent holder |
Address after: 610041 Sichuan city of Chengdu province high tech Zone Kyrgyzstan Road 33 block A No. 9 Patentee after: IPGoal Microelectronics (Sichuan) Co., Ltd. Address before: 402 room 7, building 610041, incubator Park, hi tech Zone, Sichuan, Chengdu Patentee before: IPGoal Microelectronics (Sichuan) Co., Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130116 Termination date: 20160730 |