CN105679771B - 阵列基板及其制作方法、包含其的显示面板 - Google Patents

阵列基板及其制作方法、包含其的显示面板 Download PDF

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CN105679771B
CN105679771B CN201610064991.9A CN201610064991A CN105679771B CN 105679771 B CN105679771 B CN 105679771B CN 201610064991 A CN201610064991 A CN 201610064991A CN 105679771 B CN105679771 B CN 105679771B
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array substrate
layer
metal routing
metal
passivation layer
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CN105679771A (zh
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陈彬彬
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Tianma Microelectronics Co Ltd
Xiamen Tianma Microelectronics Co Ltd
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Tianma Microelectronics Co Ltd
Xiamen Tianma Microelectronics Co Ltd
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Priority to US15/139,655 priority patent/US10054831B2/en
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    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • GPHYSICS
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    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • GPHYSICS
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    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
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    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • HELECTRICITY
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    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
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    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • HELECTRICITY
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    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
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    • H10K59/126Shielding, e.g. light-blocking means over the TFTs
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    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/1333Constructional arrangements; Manufacturing methods
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    • GPHYSICS
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    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • GPHYSICS
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Abstract

本申请公开了一种阵列基板及其制作方法、包含其的显示面板。其中,阵列基板包括基板、形成在基板上的第一导体层、形成在第一导体层上的第一钝化层、形成在第一钝化层上的遮光层、形成在遮光层上的第二钝化层以及形成在第二钝化层上的第一金属层;形成在遮光层上的第一金属走线通过至少一个形成在第一钝化层上的第一过孔与第一导体层电连接;形成在第一金属层的第二金属走线和与之对应的第一金属走线之间通过至少一个形成在第二钝化层上的第二过孔电连接。按照本申请的方案,可以避免静电荷在遮光层和第一金属层上积累可能导致的“天线效应”,防止“天线效应”对阵列基板中的各金属走线可能造成的破坏。

Description

阵列基板及其制作方法、包含其的显示面板
技术领域
本公开一般涉及显示技术领域,尤其涉及阵列基板及其制作方法、包含其的显示面板。
背景技术
静电击穿(ESD,Electro-Static Discharge)是显示面板制程中由于静电大量累积,在电荷转移过程中遇到较细的走线或者线线交叉的地方,瞬间电流过大,对电子器件的一种破坏现象。
随着对PPI(Pixel per Inch)提升的需求,器件的尺寸越来越小,金属的线宽以及金属与金属之间的距离越来越小,甚至连成一体。
参见图1所示,其示意性地示出了现有的显示面板中,与各像素电极分别对应连接的多个TFT(Thin Film Transistor,薄膜晶体管)的源漏极110、栅极线120和遮光层中的各遮光金属块130的位置关系。如图1所示,相邻的遮光金属块130之间的间距约为2μm,且随着PPI的提高,该间距将变得更小。由于刻蚀工艺的精度限制,当相邻遮光金属块的间距过小时,无法既保证相邻的二遮光金属块之间相互绝缘又保证遮光金属块能够完全地遮挡TFT器件的沟道。如图2所示,由于相邻二遮光金属块210之间的间隔区域211的宽度非常小,在实际制作时,将不再刻蚀间隔区域211,而是制作整条的遮光金属线以遮挡整行像素的所有TFT器件的沟道。
此外,随着后续金属层(例如,数据线所在的金属层等)的叠加,发生“天线效应”的可能性也越来越大。
现有技术中,可以通过一个或者多个TFT或者引线组成防静电器件。防静电器件中不同的引线可作为静电的输入端和输出端将静电导出,或者使得静电在引线上逐渐衰减,从而达到静电释放的目的。但是在这些防静电器件形成之前,不可避免地存在静电累积对走线的损伤。
发明内容
鉴于现有技术中的上述缺陷或不足,期望提供一种阵列基板及其制作方法、包含其的显示面板,以期解决现有技术中存在的技术问题。
第一方面,本申请实施例提供了一种阵列基板,包括基板、形成在基板上的第一导体层、形成在第一导体层上的第一钝化层、形成在第一钝化层上的遮光层、形成在遮光层上的第二钝化层以及形成在第二钝化层上的第一金属层;其中:遮光层包括多条平行的第一金属走线;第一金属层包括与每条第一金属走线一一对应的多条平行设置的第二金属走线;第一钝化层设有多个贯穿第一钝化层的第一过孔,各第一金属走线通过至少一个第一过孔与第一导体层电连接;各第二钝化层设有多个贯穿第二钝化层的第二过孔,各第二金属走线和与之对应的第一金属走线之间通过至少一个第二过孔电连接;阵列基板包括显示区和非显示区,第一过孔和第二过孔位于非显示区。
第二方面,本申请实施例还提供了一种显示面板,其包括如上所述的阵列基板,以及与阵列基板对置的彩膜基板,以及形成于阵列基板和彩膜基板之间的液晶层。
第三方面,本申请实施例还提供了一种阵列基板的制作方法,用于制作至少一个阵列基板,包括:在基板上形成第一导体层;在第一导体层上形成第一钝化层,并在第一钝化层上开设多个贯穿第一钝化层的第一过孔;在第一钝化层上形成遮光层,光层包括多条平行的第一金属走线,各第一金属走线通过至少一个第一过孔与第一导体层电连接;在遮光层上形成第二钝化层,并在第二钝化层上开设多个贯穿第二钝化层的第二过孔;以及在第二钝化层上形成第一金属层,第一金属层包括与每条第一金属走线一一对应的多条平行设置的第二金属走线,第二金属走线通过至少一个第二过孔和与之对应的第一金属走线电连接。
按照本申请实施例的方案,通过在阵列基板的制作过程中,在第一导体层和遮光层之间的第一钝化层上形成第一过孔,以使遮光层上积累的静电荷可通过这些第一过孔引至第一导体层进而消散,并在遮光层和第一金属层之间的第二钝化层上形成第二过孔,以使第一金属层上积累的静电荷通多第二过孔、第一过孔引至第一导体层进而消散。避免了静电荷在遮光层和第一金属层上积累可能导致的“天线效应”,防止“天线效应”对阵列基板中的各金属走线可能造成的破坏,进而可提高阵列基板的制作良率。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述,本申请的其它特征、目的和优点将会变得更明显:
图1示出了现有的显示面板的示意性结构图;
图2示出了现有的显示面板中,随着PPI的增大,相邻遮光金属块的位置关系;
图3A示出了本申请的阵列基板的一个实施例的示意性结构图;
图3B为图3A的沿A-A线的剖视图;
图4A示出了本申请的阵列基板的另一个实施例的示意性结构图;
图4B为图4A的沿B-B线的剖视图;
图5示出了本申请的阵列基板的制作方法的一个实施例的示意性流程图;
图6A示出了采用本申请的阵列基板的制作方法制成的阵列基板的示意性结构图;
图6B为图6A的沿C-C线的剖视图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是,此处所描述的具体实施例仅仅用于解释相关发明,而非对该发明的限定。另外还需要说明的是,为了便于描述,附图中仅示出了与发明相关的部分。
需要说明的是,在不冲突的情况下,本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
参见图3A所示,为本申请的阵列基板的一个实施例的示意性结构图,图3B为图3A的沿A-A线的剖视图。
下面,将结合图3A和图3B来对本实施例的阵列基板进行详细描述。需要说明的是,图3A和图3B中,相同的附图标记代表相同的结构。
本实施例的阵列基板包括基板310、形成在基板310上的第一导体层320、形成在第一导体层320上的第一钝化层330、形成在第一钝化层330上的遮光层、形成在遮光层上的第二钝化层350以及形成在第二钝化层350上的第一金属层。
遮光层包括多条平行的第一金属走线340。第一金属层包括与每条第一金属走线340一一对应的多条平行设置的第二金属走线360。第一钝化层330设有多个贯穿第一钝化层330的第一过孔331,各第一金属走线340通过至少一个第一过孔331与第一导体层320电连接。各第二钝化层350设有多个贯穿第二钝化层350的第二过孔351,各第二金属走线360和与之对应的第一金属走线340之间通过至少一个第二过孔351电连接。
此外,本实施例的阵列基板包括显示区30和非显示区,第一过孔331和第二过孔351均位于非显示区。图3A中,附图标记30所示的虚线框内的区域为阵列基板的显示区,而位于虚线框外的部分则为阵列基板的非显示区。
本实施例的阵列基板,通过形成在第一钝化层330上的第一过孔331,第一金属走线340可以与第一导体层320形成电连接,从而使得在阵列基板制程中累积于各第一金属走线340上的静电荷可以传递至第一导体层320。避免了累积在各条第一金属走线340上的静电荷导致各条第一金属走线340的尖端产生静电放电,进而损坏第一金属走线340和/或第一钝化层330。
类似地,通过形成在第二钝化层350上的第二过孔351,可以使各第二金属走线360对应连接至至少一条第一金属走线340。从而使得在阵列基板制程中累积于各第二金属走线360上的静电荷可以传递至第一金属走线340。又由于第一金属走线340通过第一过孔331连接至第一导体层320,在阵列基板制程中形成于第二金属走线360上的静电荷可经第二过孔351、第一过孔331传递至第一导体层320进而消散,避免了累积在各条第二金属走线360上的静电荷导致各条第二金属走线360的尖端产生静电放电,进而损坏第二金属走线360和/或第二钝化层350。
需要说明的是,尽管图3A和图3B中示意性地示出了每条第一金属走线340通过一个第一过孔331连接至第一导体层320,且每条第二金属走线360通过一个第二过孔351连接至遮光层上的第一金属走线340。然而,该第一过孔331和第二过孔351的数量仅是示意性的。在实际应用中,本领域技术人员可以根据具体应用场景的需求来设置形成于各条第一金属走线340和第一导体层320之间的第一过孔331的数量和形成于各条第二金属走线360和各条第一金属走线340之间的第二过孔351的数量。因此,无论连接各条第一金属走线340和第一导体层320的第一过孔331的数量是多少,也无论连接各条第二金属走线360和各条第一金属走线340的第二过孔351的数量是多少,只要各第一过孔331和第二过孔351形成于阵列基板的非显示区域,便视为落入了本实施例的保护范围之内。
在一些可选的实现方式中,如图3A和图3B所示,与同一条第一金属走线340连接的第一过孔331和第二过孔351沿垂直于阵列基板的方向向遮光层的投影无交叠。
或者,在另一些可选的实现方式中,与同一条第一金属走线340连接的其中至少一个第一过孔331和其中至少一个第二过孔351沿垂直于阵列基板的方向向遮光层的投影至少部分地交叠,例如,与同一条第一金属走线340连接的其中至少一个第一过孔331和其中至少一个第二过孔351沿垂直于阵列基板的方向向遮光层的投影可以相互重叠。
在这些可选的实现方式中,各第二金属走线360可包括至少一个与第二过孔351电连接的第一段361以及至少一个与第二过孔351绝缘的第二段362,其中,各第一段361位于非显示区。相应地,第二段362中的至少一部分位于阵列基板的显示区30内。
在一些应用场景中,在阵列基板的制程中,可以在较早的制作步骤中形成各条第一金属走线340和第二金属走线360,此时,每条第二金属走线360的任意一段均和与之对应的第二过孔351电连接,以使第二金属走线360上的静电荷可传递至与之对应的第一金属走线340上,进而引至第一导体层320。而在较晚的制作步骤中(例如,在形成TFT器件之后),再通过例如激光切割的方式将各条第二金属走线360分为与第二过孔351电连接的第一段361以及与第二过孔351绝缘的第二段362。这样一来,可以在完成阵列基板的制程之后,向各条第二金属走线360的第二段362施加电信号,从而使得包含该阵列基板的显示面板能够正常显示。
在一些应用场景中,在对各第二金属走线360进行激光切割时,可以将激光的光强设置得较大,以确保各第二金属走线的第一段361和第二段362之间绝缘。在这些应用场景中,例如,可以在激光切割时,将第一金属走线340切割形成于第一过孔331电连接的第三段和与第一过孔331绝缘的第四段。通过检测第一金属走线340的第三段和第四段是否绝缘良好,可以间接地确定第二金属走线360的第一段361和第二段362是否绝缘良好。
在一些应用场景中,各条第二金属走线360例如可以与一个第二过孔351对应连接。在这些应用场景中,该第二金属走线360可以包括一个第一段361和一个第二段362。
在另一些应用场景中,各条第二金属走线360例如可以与两个第二过孔351对应连接,例如,两个第二过孔351可以分别位于该第二金属走线360两端。在这些应用场景中,该第二金属走线360例如可以包括两个第一段361和一个第二段362。
在一些可选的实现方式中,第一导体层320可以为透明导体层,例如,可以是在玻璃上电镀可以导电的ITO(Indium tin oxide,氧化铟锡)膜形成的导电玻璃。
在这些可选的实现方式的一些应用场景中,第一导体层320例如可以是整面沉积在基板310上的。或者,在另一些应用场景中,第一导体层320可以根据实际应用的需求设计任意的图形。因此,无论第一导体层320是否为整面沉积,也无论第一导体层320具有何种图形,只要各第一过孔331可以使得各第一金属走线340与导体层320电连接,便视为落入了本实施例的保护范围。
参见图4A所示,为本申请的阵列基板的另一个实施例的示意性结构图,图4B为图4A的沿B-B线的剖视图。
与图3A和图3B所示的实施例类似,本实施例的阵列基板同样包括基板410、形成在基板上的第一导体层420、形成在第一导体层420上的第一钝化层430、形成在第一钝化层430上的遮光层、形成在遮光层上的第二钝化层450以及形成在第二钝化层450上的第一金属层。
遮光层包括多条平行的第一金属走线440。第一金属层包括与每条第一金属走线440一一对应的多条平行设置的第二金属走线460。第一钝化层430设有多个贯穿第一钝化层430的第一过孔431,各第一金属走线440通过至少一个第一过孔431与第一导体层420电连接。各第二钝化层450设有多个贯穿第二钝化层450的第二过孔451,各第二金属走线460和与之对应的第一金属走线440之间通过至少一个第二过孔451电连接。
此外,本实施例的阵列基板包括显示区40和非显示区,第一过孔431和第二过孔451均位于非显示区。图4A中,附图标记40所示的虚线框内的区域为阵列基板的显示区,而位于虚线框外的部分则为阵列基板的非显示区。
与图3A和图3B所示的实施例不同的是,本实施例中,第一导体层420仅位于阵列基板的非显示区内。
通过将第一导体层420仅沉积于基板410上的非显示区域,可以避免第一导体层420沉积在显示区域时对阵列基板的透过率的影响,进而可避免显示效果的劣化。此外,由于本实施例中第一过孔431位于非显示区,第一导体层420仅沉积于非显示区域不会影响各第一金属走线440通过第一过孔431与第一导体层420的电连接,因而也可以将第一金属走线440和第二金属走线460上积累的静电荷引至第一导体层420进而消散,避免“天线效应”的发生。
在本申请各实施例的阵列基板的一些可选的实现方式中,各第二金属走线360、460沿垂直于阵列基板方向向遮光层的投影与各第一金属走线340、440至少部分地交叠。
在一些应用场景中,可以采用具有较深颜色的金属(例如金属钼)来制作遮光层。例如,可以在第一钝化层330、430上沉积整面的金属钼,再对该整面的金属钼层进行蚀刻从而形成多条相互平行的第一金属走线340、440。由于第一金属走线340、440具有较深的颜色,其可以起到遮挡从下方向上传播的光线(例如,由显示面板的背光板发出的光)的作用。在这些应用场景中,第一金属线340、440可以遮挡在阵列基板的后续制程中制作的薄膜晶体管器件的沟道,避免薄膜晶体管器件因受到背光的照射而误动作,影响显示效果。因此,为了更好地达到遮挡背光的效果,可以在制作第二金属走线360、460时,使得第二金属走线360、460沿垂直于阵列基板方向向遮光层的投影与各第一金属走线340、440至少部分地交叠,甚至第二金属走线360、460沿垂直于阵列基板方向向遮光层的投影位于与之对应的第一金属走线340、440之内。
本申请还公开了一种显示面板,其包括如上所述的阵列基板、与阵列基板对置的彩膜基板,以及形成于阵列基板和彩膜基板之间的液晶层。
参见图5所示,其示出了本申请的阵列基板的制作方法的一个实施例的流程图。本实施例的阵列基板的制作方法可用于制作至少一个阵列基板。具体而言,本实施例的方法包括:
步骤510,在基板上形成第一导体层。
步骤520,在第一导体层上形成第一钝化层,并在第一钝化层上开设多个贯穿第一钝化层的第一过孔。
步骤530,在第一钝化层上形成遮光层。其中,遮光层包括多条平行的第一金属走线,各第一金属走线通过至少一个第一过孔与第一导体层电连接。
步骤540,在遮光层上形成第二钝化层,并在第二钝化层上开设多个贯穿第二钝化层的第二过孔。
步骤550,在第二钝化层上形成第一金属层。其中,第一金属层包括与每条第一金属走线一一对应的多条平行设置的第二金属走线,第二金属走线通过至少一个第二过孔和与之对应的第一金属走线电连接。
采用本实施例的阵列基板的制作方法,可以用于制作一个阵列基板,或者,还可以同时制作多个阵列排布的阵列基板。当用于制作多个阵列排布的阵列基板时,在完成各阵列基板的制作之后,可以对这些阵列排布的阵列基板进行切割,从而得到多个阵列基板。
采用本实施例的阵列基板的制作方法,通过形成在第一钝化层上的第一过孔,可以使第一金属走线可以与第一导体层形成电连接,从而使得在阵列基板制程中累积于各第一金属走线上的静电荷可以传递至第一导体层。避免了累积在各条第一金属走线上的静电荷导致各条第一金属走线之间产生静电击穿,进而损坏第一金属走线和/或第一钝化层。
类似地,通过形成在第二钝化层上的第二过孔,可以使各第二金属走线对应链接至至少一条第一金属走线。从而使得在阵列基板制成中累积于各第二金属走线上的静电荷可以传递至第一金属走线。又由于第一金属走线通过第一过孔连接至第一导体层,在阵列基板制程中形成于第二金属走线上的静电荷可经第二过孔、第一过孔传递至第一导体层进而消散,避免了累积在各条第二金属走线上的静电荷导致各条第二金属走线之间产生静电击穿,进而损坏第二金属走线和/或第二钝化层。
在一些可选的实现方式中,与同一条第一金属走线连接的其中至少一个第一过孔和其中至少一个第二过孔沿垂直于阵列基板的方向向遮光层的投影至少部分地交叠。
或者,在另一些可选的实现方式中,与同一条第一金属走线连接的第一过孔和第二过孔沿垂直于阵列基板的方向向遮光层的投影无交叠。
在一些可选的实现方式中,阵列基板包括显示区和非显示区;第一过孔和第二过孔位于非显示区。
在这些可选的实现方式中,本实施例的方法还可以包括:将各第二金属走线分割形成至少一个与第二过孔电连接的第一段以及至少一个与第二过孔绝缘的第二段,其中,各第一段位于非显示区。采用该可选的实现方式制作的阵列基板例如可以具有如图3A和图3B所示的结构,在此将不再赘述。
在这些可选的实现方式的一些应用场景中,例如可以通过激光切割的方式,来将各第二金属走线分割形成至少一个与第二过孔电连接的第一段以及至少一个与第二过孔绝缘的第二段。
在这些可选的实现方式中,当第一过孔和第二过孔形成于阵列基板的非显示区时,步骤510的在基板上形成第一导体层例如可以是仅在阵列基板的非显示区内形成第一导体层。
通过将第一导体层仅沉积于基板上的非显示区域,可以避免第一导体层沉积在显示区域时对阵列基板的透过率的影响,进而可避免显示效果的劣化。采用该可选的实现方式制作的阵列基板例如可以具有如图4A和图4B所示的结构,在此将不再赘述。
或者,在另一些可选的实现方式中,第一过孔和第二过孔形成于沿第二金属走线的延伸方向相邻的二阵列基板之间。在这些可选的实现方式中,本实施例的方法还可以包括:切割阵列基板,以使第一过孔、第二过孔与阵列基板绝缘。
在这些可选的实现方式中,当第一过孔和第二过孔形成于沿第二金属走线的延伸方向相邻的二阵列基板之间时,步骤510的在基板上形成第一导体层例如可以是仅在沿第二金属走线的延伸方向相邻的二阵列基板之间形成第一导体层。
参见图6A所示,为采用该可选的实现方式制作的阵列基板的示意性结构图,图6B为图6A的沿C-C线的剖视图。
图6A和图6B中示意性地示出了两个沿第二金属走线640延伸的方向相邻的阵列基板61和62,且相邻的二阵列基板61和62之间存在间隔区域63。
结合图6A和图6B可知,第一导体层620仅沉积在相邻二阵列基板61和62之间的间隔区域63中,这样一来,可以避免第一导体层620的存在导致制作完成的阵列基板的透过率下降,进而可避免显示效果的劣化。
第一过孔631和第二过孔651也相应地形成在相邻二阵列基板61和62之间的间隔区域63中。
在一些应用场景中,如图6A所示,相邻二阵列基板61和62的第一金属走线640可以同时一体成型,且相邻二阵列基板61和62的第二金属走线660也可以同时一体成型。也即是说,在这些应用场景中,各条第一金属走线640可以贯穿阵列基板61和阵列基板62之间的间隔区域63,且各条第二金属走线660也可以贯穿阵列基板61和阵列基板62之间的间隔区域63。这样一来,由于在阵列基板61和阵列基板62中位置相同的第一金属走线640和第二金属走线660分别电连接,其可以共用第一过孔631和第二过孔651。
在另一些应用场景中,阵列基板61中的任意一条第一金属线与阵列基板62中的任意一条第一金属线在遮光层上无电连接,且阵列基板61中的任意一条第二金属线与阵列基板62中的任意一条第二金属线在第一金属层上无电连接。在这些应用场景中,可以在阵列基板61和62之间的间隔区域63中分别形成与阵列基板61的各第一金属走线640和第二金属走线660对应的第一过孔631和第二过孔651,以及与阵列基板62的各第一金属走线640和第二金属走线660对应的第一过孔631和第二过孔651。
这样一来,在完成第二金属走线的制作之后,可以沿着图6A和图6B中的线64和线65进行切割,以切断各第一金属走线640和与之对应的第二金属走线660之间的电连接,以使制作完成的阵列基板中的各第一金属走线640可以正常地接收电信号。
在一些可选的实现方式中,第一导体层620可以为透明导体层。例如,可以是在玻璃上电镀可以导电的ITO(Indium tin oxide,氧化铟锡)膜形成的导电玻璃。
在一些可选的实现方式中,各第二金属走线660沿垂直于阵列基板方向向遮光层的投影与各第一金属走线640至少部分地交叠。
本领域技术人员应当理解,本申请中所涉及的发明范围,并不限于上述技术特征的特定组合而成的技术方案,同时也应涵盖在不脱离所述发明构思的情况下,由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (19)

1.一种阵列基板,其特征在于,包括基板、形成在所述基板上的第一导体层、形成在所述第一导体层上的第一钝化层、形成在所述第一钝化层上的遮光层、形成在所述遮光层上的第二钝化层以及形成在所述第二钝化层上的第一金属层;
其中:
所述遮光层包括多条平行的第一金属走线;
所述第一金属层包括与每条所述第一金属走线一一对应的多条平行设置的第二金属走线;
所述第一钝化层设有多个贯穿所述第一钝化层的第一过孔,各所述第一金属走线通过至少一个第一过孔与所述第一导体层电连接;
各所述第二钝化层设有多个贯穿所述第二钝化层的第二过孔,各所述第二金属走线和与之对应的所述第一金属走线之间通过至少一个所述第二过孔电连接;
所述阵列基板包括显示区和非显示区,所述第一过孔和所述第二过孔位于所述非显示区;所述第一金属走线的部分位于所述显示区。
2.根据权利要求1所述的阵列基板,其特征在于:
与同一条第一金属走线连接的其中至少一个所述第一过孔和其中至少一个所述第二过孔沿垂直于所述阵列基板的方向向所述遮光层的投影至少部分地交叠。
3.根据权利要求1所述的阵列基板,其特征在于:
与同一条第一金属走线连接的所述第一过孔和所述第二过孔沿垂直于所述阵列基板的方向向所述遮光层的投影无交叠。
4.根据权利要求2或3所述的阵列基板,其特征在于:
各所述第二金属走线包括至少一个与所述第二过孔电连接的第一段以及至少一个与所述第二过孔绝缘的第二段,其中,各所述第一段位于所述非显示区。
5.根据权利要求1所述的阵列基板,其特征在于:
所述第一导体层为透明导体层。
6.根据权利要求1所述的阵列基板,其特征在于:
所述第一导体层仅位于所述非显示区内。
7.根据权利要求1所述的阵列基板,其特征在于:
各所述第二金属走线沿垂直于所述阵列基板方向向所述遮光层的投影与各所述第一金属走线至少部分地交叠。
8.一种显示面板,包括如权利要求1-7任意一项所述的阵列基板,其特征在于,还包括:
与所述阵列基板对置的彩膜基板,以及形成于所述阵列基板和所述彩膜基板之间的液晶层。
9.一种阵列基板的制作方法,用于制作至少一个阵列基板,其特征在于,包括:
在基板上形成第一导体层;
在所述第一导体层上形成第一钝化层,并在所述第一钝化层上开设多个贯穿所述第一钝化层的第一过孔;
在所述第一钝化层上形成遮光层,所述遮光层包括多条平行的第一金属走线,各所述第一金属走线通过至少一个所述第一过孔与所述第一导体层电连接;
在所述遮光层上形成第二钝化层,并在所述第二钝化层上开设多个贯穿所述第二钝化层的第二过孔;以及
在所述第二钝化层上形成第一金属层,所述第一金属层包括与每条所述第一金属走线一一对应的多条平行设置的第二金属走线,所述第二金属走线通过至少一个第二过孔和与之对应的所述第一金属走线电连接;
所述阵列基板包括显示区和非显示区;所述第一金属走线的部分位于所述显示区。
10.根据权利要求9所述的方法,其特征在于:
与同一条第一金属走线连接的其中至少一个所述第一过孔和其中至少一个所述第二过孔沿垂直于所述阵列基板的方向向所述遮光层的投影至少部分地交叠。
11.根据权利要求9所述的方法,其特征在于:
与同一条第一金属走线连接的所述第一过孔和所述第二过孔沿垂直于所述阵列基板的方向向所述遮光层的投影无交叠。
12.根据权利要求10或11所述的方法,其特征在于:
所述第一过孔和所述第二过孔位于所述非显示区。
13.根据权利要求10或11所述的方法,其特征在于:
所述第一过孔和所述第二过孔形成于沿所述第二金属走线的延伸方向相邻的二阵列基板之间。
14.根据权利要求13所述的方法,其特征在于,还包括:
切割所述阵列基板,以使所述第一过孔、第二过孔与所述阵列基板绝缘。
15.根据权利要求12所述的方法,其特征在于,还包括:
将各所述第二金属走线分割形成至少一个与所述第二过孔电连接的第一段以及至少一个与所述第二过孔绝缘的第二段,其中,各所述第一段位于所述非显示区。
16.根据权利要求15所述的方法,其特征在于,所述将各所述第二金属走线分割形成至少一个与所述第二过孔电连接的第一段以及至少一个与所述第二过孔绝缘的第二段包括:
通过激光将各所述第二金属走线分割形成至少一个与所述第二过孔电连接的第一段以及至少一个与所述第二过孔绝缘的第二段。
17.根据权利要求9-11任意一项所述的方法,其特征在于:
所述第一导体层为透明导体层。
18.根据权利要求12所述的方法,其特征在于,所述在所述基板上形成第一导体层包括:
仅在所述阵列基板的所述非显示区内形成第一导体层。
19.根据权利要求18所述的方法,其特征在于:
各所述第二金属走线沿垂直于所述阵列基板方向向所述遮光层的投影与各所述第一金属走线至少部分地交叠。
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