M265639 八、新型說明： - 【新型所屬之技術領域】 本創作係有關一種分離靜電放電（ESD)線路之佈局架 構，針對尚於中片製程階段之ESD線路佈局架構，達到製 · 程時之ESD防護功能，與面板的單面板測試。 【先前技術】 薄膜電晶體液晶顯示器（TFT-LCD )是目前相當熱門 的產品，但因為TFT元件製作在玻璃絕緣面版上，經常發 生靜電放電（Electrostatic Discharge, ESD)相關問題，一旦面 _ 板中有元件遭受ESD傷害，該面板即無法使用，其良率損 失會相當嚴重。 在TFT製作量產產品過程中（矩陣陣列製程、單面板測 試與模組化製程），ESD的產生是非常顯而易見的現象，靜 電造成矩陣陣列之TFT元件閘極絕緣層被打穿與非常大的 漏電流，靜電的發生對產品良率影響極大。靜電防護設計 可預防外來因素產生靜電如：人為、機台設備，提升加強 靜電防護效果，將達到更妥善靜電防護。 春 對TFT製程而言，單面板功能測試（ceu test functi〇n) 過程是一道很重要的檢測步驟，目前單面板功能測試主要 分為二個方法。方法一，短接線（sh〇rting bar)法：先將所 有掃描線（Scan Lines)與資料線(Data Lines)分別以短接線 (Shorting bar)方式連接，再通電壓做顯示晝面的測試。但 一旦完成該測試，還必須以鐳射切割（Laser cut)機台將短接· 線（Shorting bar)與掃描線（Scan Lines)與資料線（Data [丨腦） 之連接線燒断’使每一條掃描線（gcail Line)與掃描線（Scan Line)間將各自獨立；且每一條資料線（Data Lines)與資料線 5 M265639 (Data Line)間將各自獨立。 方法二，TFT開關（TFT Switch)法：係在設置顯示晝素 之矩陣區10外，在每一掃描線與資料線之ESD元件11與 ‘ 矩陣區10間做一 TFT開關元件12 (請參閱「第1圖」所 -示），將掃描線與資料線所有的TFT開關元件12的閘極連 接在一個測試墊PDS、PSS，另也將所有的掃描線與資料線 連接在所屬測試墊PSE、PSO、PDR、PDG、PDB (分為奇 偶與R、G、B) 〇只要在測試墊PSE、PSO、PDR、PDG、 PDB加上顯示晝面電壓，與加上電壓在測試墊pDS、PSS 上使TFT開關元件12為”〇n”，即可達到測試功能，此方 < 法不需以鐳射切割機再進行切除動作，有效節省鐳射切割 機的支出成本。 但當吾人在製作顯示晝素之矩陣區1〇時，就有既之良 率困擾’倘若為了單面板測試（Cell test)，則需使用額外之 設計’如前述所題到使用短接線與TFT開關等。就短接線 而吕’其元成單面板測試後尚需添加鐳射切割的製程，如 此不只需增加鐳射切割成本與降低生產量。而就TFT開關 而言’除了需考慮原本顯示晝素之矩陣區10之製程良率《 外’仍需再過TFT開關元件12之良率，故常常造成顯示 面板整體良率之下降。 【新型内容] 妥是’為解決上述之缺失，本創作所提供一種分離靜 _ 電放電（ESD)線路之佈局架構，係將顯示面板内之ESD元 件接至獨立分開成若干群之共電極線，而該共電極線分別-引線至各外弓丨腳後，再使用外引腳外部來達到短接 6 M265639 (Shorting)，來達到ESD功能。 藉此，如此本創作之設計，將共電極獨立分開佈局至 外引腳後，將可同時擁有不僅擁有短接線之特性，亦保有 加入TFT開關元件之功能，增加非破壞性之單面板測試。 但卻不像短接線，於完成單面板測試後尚需添加鐳射切割 的製程，將可省下鐳射切割成本與提昇生產量。 亦不需加入TFT開關，所以本創作只需注意原本顯示 晝素之矩陣區之製程良率，不需特別去考量注意TFT開關 元件之良率。 【實施方式】 茲有關本創作之詳細内容及技術說明，現配合圖式說 明如下： 請參閱『第2圖』所示，係本創作之顯示面板示意圖。 本創作係一種分離靜電放電（ESD)線路之佈局架構，係用於 薄膜電晶體液晶顯示面板100之靜電放電線路，係於顯示 面板100尚為中片未模組化時，顯示晝素之矩陣區10外， 且每一掃描線與資料線上設有一 ESD元件11，其特徵在於 將每一掃描線與資料線之ESD元件接至獨立分開成若干群 之共電極線，而該共電極線獨立分開佈局，再分別引線至 各外引腳 PI、P2、P3、P4、P5。 請再參閱『第3圖』所示，係本創作之於中片製程時 線路共極佈局示意圖。針對前述之外引腳PI、P2、P3、P4、 P5於中片製程階段，可將中片上同一列之顯示面板100的 各外引腳PI、P2、P3、P4、P5再獨立分開引線成若干群到 中片外圍之測試墊PSE、PS0、PDR、PDG、PDB，只要在 測試墊PSE、PS0、PDR、PDG、PDB分別加上顯示晝面電 M265639 ，，可達到一般中片製程中的測試功能。且製造者只需. 肩K式墊PSE、PSO、PDR、PDG、PDB於中片製程階段利 短接環將測試墊PSE、PSO、PDR、PDG、PDB連接在一 ‘ 起形成一大共電極，就可達中片中各顯示面板1〇〇共電極 的目標，使中片於後續的製程中具ESD防護的功能。 針對各顯示面板100共電極之目標，於該外引腳P1、 P2、P3、P4、P5於中片製程階段，亦可利用一短接條21 =外引腳P卜P2、P3、P4、P5外部來做短接（Shorting)(如 『第4圖』所示），就可達中片中各顯示面板1〇〇具一共電 ，，目標，使中片於後續的製程中具ESD防護的功能可保 _ 護每一顯示面板100内顯示晝素之矩陣區1〇iTFT元不' 受靜電之影響。 請再參閱『第5圖』所示，係本創作之單一顯示面板 1〇〇之示意圖。經過前述中片製程階段，於經過小列片製程 後’單一顯示面板100之各外引腳P1、P2、P3、P4、Μ 因為其所對應的每一掃描線與資料線上之ESD元件為獨立 分開成若干群之共電極線，而該共電極線獨立分開，分別 引線至各外引腳PI、P2、P3、P4、P5，所以各外引腳^、 P2、P3、P4、P5此時也如同一種測試墊（功能如同前述的 測試塾PSE、PSO、、PDG、PDB)，使用者只需在各 引腳？1、？2、1>3、？4、1>5加上顯示晝面電壓，即可對顯示 面板100達到單面板測試之功能。 、y' 如『第6圖』本創作之顯示面板於產品之共極實施示 意圖。當本創作之顯示面板100於產品模組化應用時-對單一顯示面板100可利一外加電路，如可於連接導電用· 之軟式印刷電路板(FPC)22上設一短接條22a，利用此短 8 M265639 條22a上之共極線com (該共極線之設計依顯示模組，線 路將有所不同）將外引腳共接至產品之共接電極，使顯示 面板100上的靜電可與產品模組共極，使裝設該顯示面板 之顯示模組具ESD防護的功能。 綜合>以上所述，本創作之佈局架構，係將顯示面板内 之ESD兀件11接至獨立分開成若干群之共電極線，而該 共電極線分別引線至各外引腳PI、P2、P3、p4、P5後，再 使用外引腳P卜P2、P3、P4、P5外部來達到短接（Sh〇rti 來達到ESD功能。 藉此，本創作之佈局架構之優點在於，不僅可 電防制保護耐受能力，並且可做單面板功能測試。本 將共電極獨立分開佈局至外引腳ρι、p2、p3、p4、Μ 將可同_有補擁有短接狀特性，亦財加人門 關兀件12之功能，增加非破壞性之單面板測試。但： :短A法’於完成單面板測試後尚需添加鐳射切割的 I辛將可噌下鐳射切割成本與提昇生產量。 另本創作亦不需加入TFT開關，所以本 原本顯示書辛之拓pi F夕制和☆ t j下/、而 >主思 TFT Ημ Ι 製程良率’不需特別去考量注音 昇開關70件之良率，所以顯示面板_之良率將大^ 惟上述僅為本創作之較佳實施例而已，並非用 等Ϊ : I Ϊ之範圍、。即凡依本創作申請專利範圍所做的Ϊ $飾，皆為本創作專利範圍所涵蓋。 二 【圖式簡單說明】 習知具TFT開關之顯示面板示意圖。 圖，係本創作之顯示面板示意圖。 M265639 第3圖，係本創作之於中片製程時線路共極佈局示意圖。 第4圖，係本創作之顯示面板另一共極示意圖。 第5圖，係本創作之單一顯示面板之示意圖。 第6圖，係本創作之顯示面板於產品之共極實施示意圖。 【主要元件符號說明】 PI、P2、P3、P4、P5 :外引腳 PSE、PSO、PDR、PDG、PDB :測試墊 10 :矩陣區 11 ·· ESD 元件 12 : TFT開關元件 21、22a :短接條 22 :軟式印刷電路板 100 :顯示面板M265639 8. Description of the new type:-[Technical field to which the new type belongs] This creation is about a layout structure of the separation electrostatic discharge (ESD) circuit, which is aimed at the ESD circuit layout structure that is still in the middle-film process stage, and achieves ESD during the process. Protective function, single panel test with panel. [Previous technology] Thin film transistor liquid crystal display (TFT-LCD) is currently a very popular product, but because TFT elements are fabricated on glass insulation panels, Electrostatic Discharge (ESD) -related problems often occur. Once the surface _ board Some of the components suffered ESD damage, the panel is unusable, and its yield loss will be quite serious. During the mass production of TFTs (matrix array process, single-panel test and modular process), the generation of ESD is a very obvious phenomenon. Static electricity causes the TFT element gate insulation layer of the matrix array to be punctured and very large. Leakage current and static electricity have a great impact on product yield. ESD protection design can prevent external factors from generating static electricity, such as: man-made, machine equipment, enhance the effect of electrostatic protection, and achieve better electrostatic protection. Spring For the TFT process, the single panel function test (ceu test functi0n) process is an important detection step. Currently, the single panel function test is mainly divided into two methods. Method one, short wiring (shorting bar) method: first connect all scanning lines (data lines) and data lines (data lines) by shorting (shorting bar), and then apply voltage to test the display of day and day. However, once this test is completed, the laser cutting machine (Laser cut) machine must be used to short the connecting wire (Shorting bar), scanning line (Scan Lines) and data line (Data [丨 脑) the connection line to burn out, so that each A scanning line (gcail Line) and a scanning line (Scan Line) will be independent of each other; and each data line (Data Lines) and data line 5 M265639 (Data Line) will be independent of each other. Method 2: TFT Switch method: Outside the matrix area 10 for displaying daylight, a TFT switching element 12 is formed between the ESD element 11 and the 'matrix area 10' of each scanning line and data line (see (Shown in "Figure 1"), the gates of all the TFT switching elements 12 of the scan line and the data line are connected to a test pad PDS, PSS, and all the scan lines and data lines are also connected to the corresponding test pad PSE , PSO, PDR, PDG, PDB (divided into parity and R, G, B) 〇 As long as the test pad PSE, PSO, PDR, PDG, PDB plus display day voltage, and plus voltage on the test pad pDS, PSS The test function can be achieved by setting the TFT switch element 12 to "On". This method does not require a laser cutting machine to perform a cutting operation, which effectively saves the cost of the laser cutting machine. However, when I was making a matrix area 10 displaying daylight, I had trouble with the yield rate. "If it is a cell test, additional design is needed." As mentioned above, the use of short wiring and TFT Switches, etc. In terms of short wiring, the laser cutting process still needs to be added after the single-panel test. Therefore, it is not only necessary to increase the laser cutting cost and reduce the production volume. As for the TFT switch, in addition to considering the process yield of the matrix region 10 that originally displays daylight, the yield of the TFT switch element 12 is still required to pass, so the overall yield of the display panel often decreases. [New content] Properly, in order to solve the above-mentioned shortcomings, this creative agency provides a layout structure of separated static electricity discharge (ESD) circuits, which connects the ESD components in the display panel to a common electrode line that is separated into several groups. After the common electrode wires are leaded to the outer bows and legs, the external pins are used to short 6 M265639 (Shorting) to achieve the ESD function. As a result, the design of this original creation, after the common electrode is independently and separately arranged to the outer pins, will not only have the characteristics of short wiring, but also the function of adding TFT switching elements, and increase non-destructive single-panel testing. However, unlike short wiring, a laser cutting process needs to be added after the single panel test is completed, which can save laser cutting costs and increase production. There is also no need to add a TFT switch, so in this creation, we only need to pay attention to the process yield of the matrix area that originally displays the day element, and do not need to pay special attention to the yield of the TFT switch element. [Implementation] The detailed content and technical description of this creation are described below with the help of diagrams: Please refer to "Figure 2" for a schematic diagram of the display panel of this creation. This creation is a layout structure that separates electrostatic discharge (ESD) circuits. It is an electrostatic discharge circuit for thin-film transistor liquid crystal display panels 100. When the display panel 100 is not in the middle, the matrix of daylight is displayed Outside the area 10, and each scanning line and data line is provided with an ESD element 11, which is characterized in that the ESD elements of each scanning line and data line are connected to a common electrode line which is separated into several groups, and the common electrode line is independent Separate layout, and then lead to each external pin PI, P2, P3, P4, P5. Please refer to the "Figure 3" again, which is a schematic diagram of the layout of the common circuit of the circuit during the production of this film. For the pins other than the aforementioned pins PI, P2, P3, P4, and P5 at the middle film manufacturing stage, the outer pins PI, P2, P3, P4, and P5 of the display panel 100 in the same row on the middle chip can be separately separated into leads. Several groups of test pads PSE, PS0, PDR, PDG, PDB to the periphery of the middle film, as long as the test pads PSE, PS0, PDR, PDG, PDB are added with the display daytime electricity M265639, which can reach the general film production process. Test function. And the manufacturer only needs. Shoulder K-type pads PSE, PSO, PDR, PDG, and PDB are connected to the test pads PSE, PSO, PDR, PDG, and PDB at the middle of the film production process to form a large common electrode. It can reach the goal of 100 common electrodes of each display panel in the middle film, so that the middle film has the function of ESD protection in the subsequent process. Aiming at the target of common electrode of each display panel 100, in the middle film process stage of the external pins P1, P2, P3, P4, and P5, a shorting bar 21 = external pins P2, P3, P4, Shorting P5 externally (as shown in "Figure 4"), you can reach a total of 100 display panels in the middle film, the goal is to make the middle film ESD protection in the subsequent process The function can protect _iTFT elements in the matrix area of each display panel 100 that display day pixels from being affected by static electricity. Please refer to "Figure 5" again, which is a schematic diagram of a single display panel 100 of this creation. After the above-mentioned medium film process stage, after the small-line film process, the external pins P1, P2, P3, P4, and M of the single display panel 100 are independent because each scanning line and the ESD component on the data line are independent. The common electrode lines are divided into several groups, and the common electrode lines are separated separately, and each lead is connected to each of the external pins PI, P2, P3, P4, and P5, so the external pins ^, P2, P3, P4, and P5 are now It is also like a test pad (functions like the aforementioned test 塾 PSE, PSO, PDG, PDB), users only need to select each pin? 1,? 2, 1 > 3,? 4, 1 > 5 In addition to displaying the day-to-day voltage, the display panel 100 can achieve the function of a single panel test. , Y 'As in "Figure 6", the display panel created in this illustration implements the intention at the common pole of the product. When the display panel 100 of this creation is applied in a modularized product-a single display panel 100 can benefit from an additional circuit, such as a short circuit bar 22a on a flexible printed circuit board (FPC) 22 for connection with electrical conduction. Use this short 8 M265639 common pole line com on 22a (the design of the common pole line depends on the display module, and the wiring will be different). Commonly connect the external pins to the common electrode of the product, so that the The static electricity can be common with the product module, so that the display module installed with the display panel has the function of ESD protection. General> As mentioned above, the layout structure of this creation is to connect the ESD element 11 in the display panel to the common electrode lines that are separately divided into several groups, and the common electrode lines are respectively lead to the outer pins PI and P2. , P3, p4, and P5, and then use the external pins P2, P2, P3, P4, and P5 to achieve the short circuit (Shorti to achieve the ESD function. With this, the advantage of the layout structure of this creation is that Electrical protection protection and tolerance, and can be used for single-panel function test. The common electrode is separately and separately arranged to the outer pins ρ, p2, p3, p4, Μ will have short-circuit characteristics with _youbu Adding the function of the door gate 12 to increase the non-destructive single-panel test. But:: Short A method 'After the single-panel test is completed, laser cutting is required to add laser cutting cost and increase production. In addition, there is no need to add a TFT switch in this creation, so the original display of the book Xin Zhituo pi F evening system and ☆ tj down /, and > main thinking TFT Ημ Ι process yield 'do not need to specifically consider the note lift switch The yield of 70 pieces, so the yield of the display panel _ will be large ^ But the above is only the present The preferred embodiment of the creation is nothing but the scope of Ϊ: I Ϊ, that is, all the 饰 $ decorations made in accordance with the scope of the patent application for this creation are covered by the scope of the creation patent. [Simplified description of the diagram] Figure of the display panel with TFT switch. Figure 3 is the schematic diagram of the display panel of this creation. M265639 Figure 3 is the layout diagram of the common pole layout of the film during the middle film production process. Figure 4 is the display panel of the creation. Another common pole diagram. Figure 5 is a diagram of a single display panel of this creation. Figure 6 is a diagram of the common pole implementation of the display panel of this creation. [Description of main component symbols] PI, P2, P3, P4 P5: Outer pins PSE, PSO, PDR, PDG, PDB: Test pad 10: Matrix area 11 ESD element 12: TFT switching element 21, 22a: Shorting bar 22: Flexible printed circuit board 100: Display panel