WO2023159675A1 - 一种显示面板及显示面板的制备方法 - Google Patents

一种显示面板及显示面板的制备方法 Download PDF

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Publication number
WO2023159675A1
WO2023159675A1 PCT/CN2022/079660 CN2022079660W WO2023159675A1 WO 2023159675 A1 WO2023159675 A1 WO 2023159675A1 CN 2022079660 W CN2022079660 W CN 2022079660W WO 2023159675 A1 WO2023159675 A1 WO 2023159675A1
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Prior art keywords
electrode
layer
photoresist pattern
electrode layer
display panel
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PCT/CN2022/079660
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English (en)
French (fr)
Inventor
章仟益
周星宇
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US17/764,188 priority Critical patent/US20230269977A1/en
Publication of WO2023159675A1 publication Critical patent/WO2023159675A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a method for preparing the display panel.
  • OLED is a current-type light-emitting device.
  • OLED mainly includes anode, cathode and functional layers of organic materials.
  • the main working principle of OLED is: the organic material functional layer is driven by the electric field formed by the anode and cathode, and emits light through carrier injection and recombination.
  • the existing OLED display panel includes: a TFT display panel including a thin film transistor (Thin Film Transistor, TFT for short) driving circuit, and a plurality of OLED display devices arranged on the TFT display panel, each OLED display device is controlled by a corresponding TFT control.
  • TFT Thin Film Transistor
  • a top-emitting backplane is generally used, and the organic layer is formed by inkjet printing.
  • 10 layers of photomasks and multi-layer inorganic films need to be produced, and the production cycle is long and the cost is high.
  • the present application provides a display panel and a method for manufacturing the display panel, so as to reduce the production cycle and cost of the display panel.
  • the application provides a display panel, which includes:
  • the first electrode layer is provided on the substrate, and the first electrode layer includes a drain electrode, a source electrode and a metal wire electrode;
  • the buffer layer is disposed on the first electrode layer
  • the second electrode layer is disposed on the buffer layer, the second electrode layer includes a conductive channel, and the drain electrode and the source electrode are respectively connected to the conductive channel;
  • the gate electrode is disposed on the first insulating layer.
  • the first electrode layer further includes a light-shielding electrode, and an orthographic projection of the light-shielding electrode on the substrate covers an orthographic projection of the conductive channel on the substrate.
  • the drain electrode, the light-shielding electrode, the source electrode and the metal wire electrode are sequentially arranged at intervals.
  • the display panel further includes:
  • the passivation layer is disposed on the buffer layer and covers the gate electrode;
  • planar layer is disposed on the passivation layer.
  • a third electrode layer is arranged on the planar layer, the third electrode layer includes the first connection electrode and the anode electrode of the light-emitting OLED device;
  • the first connection electrode is connected to the metal wiring electrode through the buffer layer, the passivation layer and the via hole on the planar layer, and the anode electrode is connected to the drain electrode.
  • the second electrode layer further includes a second connection electrode, and the anode electrode is connected to the second connection electrode through the via hole on the passivation layer and the planar layer.
  • the second connection electrode is connected to the drain electrode through the via hole on the buffer layer.
  • the second connection electrode is connected to the conductive channel.
  • the second electrode layer further includes a third connection electrode, the third connection electrode is connected to the source electrode through a via hole on the buffer layer, and the first connection electrode The three connection electrodes are connected with the conductive channel.
  • the second electrode layer includes a fourth connection electrode
  • the orthographic projection of the fourth connection electrode on the substrate covers the metal wiring electrodes on the substrate
  • the orthographic projection of the first connection electrode is connected to the fourth connection electrode through the via hole on the passivation layer and the planar layer
  • the fourth connection electrode is connected to the fourth connection electrode through the via hole on the buffer layer.
  • the metal wiring electrodes are connected.
  • the display panel further includes:
  • a fourth electrode layer the fourth electrode layer includes a fifth connection electrode, the fifth connection electrode is located between the metal wire electrode and the buffer layer, and the fifth connection electrode covers the metal wire On the line electrodes, the first connection electrode is connected to the fifth connection electrode through the via hole on the buffer layer.
  • the material of the first electrode layer includes an alloy of one or more of copper, molybdenum, molybdenum-titanium, aluminum, titanium and nickel.
  • the material of the fourth electrode layer includes an alloy of one or more of indium tin oxide, indium gallium zinc oxide, molybdenum titanium, molybdenum titanium nickel and titanium.
  • the present application also provides a method for preparing a display panel, which includes the following steps:
  • the step of performing photolithographic patterning on the first electrode layer to obtain drain electrodes, source electrodes and metal wire electrodes includes the following steps:
  • the photoresist pattern is peeled off to obtain drain electrodes, source electrodes and metal wiring electrodes.
  • the preparation method further includes the following steps:
  • the third electrode layer includes a first connection electrode and an anode electrode of a light-emitting OLED device;
  • the first connection electrode is connected to the first electrode layer through the via holes on the buffer layer, the passivation layer and the planar layer, and the anode electrode is connected to the drain electrode.
  • the step of performing photolithographic patterning on the first electrode layer to obtain drain electrodes, source electrodes and metal wiring electrodes includes:
  • the first electrode layer is photolithographically patterned to obtain a drain electrode, a source electrode, a light-shielding electrode and a metal wiring electrode.
  • the following steps are further included before the step of performing photolithographic patterning on the first electrode layer to obtain drain electrodes, source electrodes and metal wire electrodes:
  • the step of performing photolithographic patterning on the first electrode layer to obtain a drain electrode, a source electrode and a metal wire electrode includes the following steps:
  • the photoresist layer performs photolithography processing on the photoresist layer to obtain a photoresist pattern, the photoresist pattern including a first photoresist pattern and a second photoresist pattern;
  • the step of forming a buffer layer on the first electrode layer comprises:
  • a buffer layer is formed on the fourth electrode layer and the first electrode layer.
  • the step of performing photolithography treatment on the photoresist layer to obtain a photoresist pattern, the photoresist pattern comprising a first photoresist pattern and a second photoresist pattern includes :
  • the photoresist layer is subjected to photolithography using a semi-transparent mask to obtain a photoresist pattern, the photoresist pattern includes a first photoresist pattern and a second photoresist pattern, and the thickness of the second photoresist pattern is greater than the thickness of the photoresist pattern. the thickness of the first photoresist pattern.
  • the first photoresist pattern is stripped, and the first electrode layer and the fourth electrode layer located under the first photoresist pattern are etched.
  • Remove, and the steps of obtaining the drain electrode, the source electrode and the metal wiring electrode include:
  • the first electrode layer and the fourth electrode layer located under the first photoresist pattern are etched away to obtain a drain electrode, a source electrode and a metal wire electrode.
  • the step of depositing and forming a second electrode layer on the buffer layer, and performing photolithographic patterning on the second electrode layer to obtain a conductive channel includes:
  • the orthographic projection of the fourth connection electrode on the substrate covers the orthographic projection of the metal wire electrode on the substrate, and the first connection electrode passes through the passivation layer and the passivation layer on the planar layer.
  • the hole is connected to the fourth connection electrode, and the fourth connection electrode is connected to the metal wiring electrode through the via hole on the buffer layer.
  • the material of the first electrode layer includes an alloy of one or more of copper, molybdenum, molybdenum-titanium, aluminum, titanium and nickel.
  • the material of the fourth electrode layer includes an alloy of one or more of indium tin oxide, indium gallium zinc oxide, molybdenum titanium, molybdenum titanium nickel and titanium.
  • the display panel includes a substrate; a first electrode layer, the first electrode layer is arranged on the substrate, and the first electrode layer includes a drain electrode, a source electrode and a metal wire electrode; a buffer layer, the buffer layer provided on the first electrode layer; a second electrode layer, the second electrode layer is provided on the buffer layer, the second electrode layer includes a conductive channel; a first insulating layer, the first insulating layer A layer is provided on the conductive channel; a gate electrode, the gate electrode is provided on the first insulating layer; a first connection electrode, the first connection electrode is provided on the buffer layer, and the first connection The electrodes are connected to the metal wiring electrodes through the via holes on the buffer layer.
  • the drain electrode, the source electrode and the metal wiring electrode are arranged on the first electrode layer.
  • the present application reduces at least one layer of source and drain metal layers, so that the display panel can reduce light in the manufacturing process.
  • the number of layers of the mask can effectively reduce the production cycle and production cost of the display panel.
  • FIG. 1 is a schematic diagram of a first structure of a display panel provided by the present application.
  • FIG. 2 is a flow chart of the first embodiment of the method for manufacturing a display panel provided by the present application
  • FIG. 3 is a flow chart of step S12 of the first embodiment of the method for manufacturing a display panel provided by the present application;
  • FIG. 4 is a schematic diagram of a second structure of the display panel provided by the present application.
  • FIG. 5 is a flow chart of the second embodiment of the manufacturing method of the display panel provided by the present application.
  • FIG. 6 is a schematic diagram of a third structure of a display panel provided by the present application.
  • FIG. 7 is a flow chart of a third embodiment of the method for manufacturing a display panel provided by the present application.
  • FIG. 8 is a schematic diagram of a fourth structure of a display panel provided by the present application.
  • FIG. 9 is a flowchart of a fourth embodiment of the method for manufacturing a display panel provided by the present application.
  • FIG. 10 is a schematic diagram of a fifth structure of the display panel provided by the present application.
  • FIG. 11 is a flow chart of the fifth embodiment of the method for manufacturing a display panel provided by the present application.
  • FIG. 12 is a flow chart of Step 12 of the fifth embodiment of the method for manufacturing a display panel provided by the present application.
  • FIG. 13 is a flow chart of step 128 of the fifth embodiment of the method for manufacturing a display panel provided by the present application.
  • FIG. 14 is a schematic diagram of a sixth structure of a display panel provided by the present application.
  • FIG. 15 is a flow chart of the sixth embodiment of the manufacturing method of the display panel provided by the present application.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain (drain terminal, drain region, or drain) and a source (source terminal, source region, or source), and current can flow through the drain, channel region, and source .
  • a channel region refers to a region through which current mainly flows. In cases where transistors with opposite polarities are used, or when the direction of current changes during circuit operation, the functions of "source” and “drain” may be interchanged. Therefore, in this specification, “source” and “drain” can be interchanged with each other.
  • the present application provides a display panel 100 and a manufacturing method of the display panel 100 , which will be described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments of the present application.
  • FIG. 1 is a schematic diagram of a first structure of a display panel 100 provided in the present application.
  • the present application provides a display panel 100, which includes a substrate 10, a first electrode layer 20, a buffer layer 30, a second electrode layer 40, a first insulating layer 50 and a gate electrode 50a.
  • the first electrode layer 20 is arranged on the substrate 10, and the first electrode layer 20 includes a drain electrode 21, a source electrode 22 and a metal wire electrode 23; the buffer layer 30 is arranged on the first on the electrode layer 20.
  • the substrate 10 is a flexible substrate, and the material of the first electrode layer 20 includes an alloy of one or more of copper, molybdenum, molybdenum-titanium, aluminum, titanium and nickel.
  • the second electrode layer 40 is disposed on the buffer layer 30, the second electrode layer 40 includes a conductive channel 41, and the drain electrode 21 and the source electrode 22 are respectively connected to the conductive channel 41;
  • the first insulating layer 50 is disposed on the conductive channel 41 ;
  • the gate electrode 50 a is disposed on the first insulating layer 50 .
  • the present application reduces at least one source-drain metal layer compared with the prior art, that is to say, The drain electrode 21, the source electrode 22, and the metal wire electrode 23 can be obtained through a photolithography process of a photomask, so that the display panel 100 can reduce the photomask in the manufacturing process.
  • the present application can effectively The production period and production cost of the display panel 100 are reduced.
  • FIG. 2 is a flow chart of a first embodiment of the method for manufacturing the display panel 100 provided by the present application.
  • the embodiment of the present application also provides a method for manufacturing the display panel 100, which includes the following steps:
  • the drain electrode 21, the source electrode 22 and the metal wiring electrode 23 can be obtained by photolithographic patterning of the first electrode layer 20 at one time.
  • the present application reduces at least one layer of source and drain electrodes
  • the metal layer that is, the application reduces the use of at least one layer of photomask in the manufacturing process of the display panel 100 , thereby effectively reducing the manufacturing cycle and manufacturing cost of the display panel 100 .
  • FIG. 3 is a flow chart of step S12 of the first embodiment of the method for manufacturing the display panel 100 provided by the present application.
  • the step S12 includes the following steps:
  • FIG. 4 is a schematic diagram of a second structure of the display panel 100 provided in the present application, which is different from the display panel provided in FIG. 1 in that: the display panel 100 also includes:
  • the passivation layer 60 is disposed on the buffer layer 30 and covers the gate electrode 50a;
  • a flat layer 70 is disposed on the passivation layer 60 .
  • the third electrode layer 80, the third electrode layer 80 is arranged on the planar layer 70, the third electrode layer 80 includes the first connection electrode 81 and the anode electrode 82 of the light-emitting OLED device;
  • the first connection electrode 81 is connected to the metal wiring electrode 23 through the buffer layer 30, the passivation layer 60 and the via holes on the planar layer 70, and the anode electrode 82 is connected to the drain electrode 21 connections.
  • the first connection electrode 81 serves as a connection terminal of the metal trace electrode 23 .
  • the drain electrode 21, the source electrode 22 and the metal wire electrode 23 are arranged on the first electrode layer 20, the conductive channel 41 is arranged on the second electrode layer 40, and the gate electrode 50a is arranged on the conductive channel 41.
  • the dielectric layer is no longer provided, so the number of layers of the inorganic film can be reduced. Since the buffer layer 30 separates the drain electrode 21, the source electrode 22 from the gate electrode 50a, even if there is no dielectric layer, the drain electrode 21 and the source electrode can be ensured. 22 and the insulation between the gate electrode 50a.
  • the second electrode layer 40 further includes a second connection electrode 42, and the anode electrode 82 is connected to the second electrode 82 through the via holes on the passivation layer 60 and the planar layer 70.
  • the connection electrode 42 is connected, and the second connection electrode 42 is connected to the drain electrode 21 through the via hole on the buffer layer 30 .
  • the second connection electrode 42 is connected to the conductive channel 41 .
  • the connection between the conductive channel 41 and the drain electrode 21 is realized through the second connecting electrode 42 , which can reduce the arrangement of connecting electrodes and via holes.
  • the second electrode layer 40 further includes a third connection electrode 43, the third connection electrode 43 is connected to the source electrode 22 through the via hole on the buffer layer 30, the third The connection electrode 43 is connected to the conductive channel 41 .
  • the above-mentioned embodiment of the display panel 100 only describes the above-mentioned structure, and it can be understood that, in addition to the above-mentioned structure, the display panel 100 in the embodiment of the present application may also include any other necessary structures as required, such as Polarizers and cover plates are not specifically limited here.
  • FIG. 5 is a flow chart of the second embodiment of the manufacturing method of the display panel 100 provided by the present application. The difference from the manufacturing method provided in FIG. 2 is that the manufacturing method further includes the following steps:
  • the third electrode layer 80 includes a first connection electrode 81 and an anode electrode 82 of a light-emitting OLED device;
  • the first connection electrode 81 is connected to the first electrode layer 20 through the buffer layer 30, the passivation layer 60 and the via holes on the planar layer 70, and the anode electrode 82 is connected to the drain electrode 21 connections.
  • FIG. 6 is a schematic diagram of a third structure of the display panel 100 provided by the present application. It is different from the display panel 100 provided in FIG. 1 in that: the first electrode layer 20 includes a drain electrode 21, a source electrode 22 .
  • the light-shielding electrode 24 and the metal wire electrode 23 , the orthographic projection of the light-shielding electrode 24 on the substrate 10 covers the orthographic projection of the conductive channel 41 on the substrate 10 .
  • Setting the drain electrode 21, the source electrode 22, the light-shielding electrode 24 and the metal wire electrode 23 on the first electrode layer 20 at the same time not only reduces a layer of source-drain metal layer, but also avoids setting up a light-shielding layer and reduces production costs .
  • the drain electrode 21, the light-shielding electrode 24, the source electrode 22 and the metal wire electrode 23 are sequentially arranged at intervals, and the light-shielding electrode 24 is arranged between the drain electrode 21 and the source electrode 21. Between the electrodes 22, the light-shielding electrode 24 can be arranged correspondingly to the conductive channel 41, and at the same time, the insulation distance between the drain electrode 21 and the source electrode 22 can be increased to enhance the insulation effect of the two.
  • FIG. 7 is a flow chart of the third embodiment of the method for preparing the display panel 100 provided in this application.
  • the difference from the method for preparing the display panel 100 provided in FIG. 2 is that the step S12 includes:
  • the first electrode layer 20 is photolithographically patterned to obtain a drain electrode 21 , a source electrode 22 , a light-shielding electrode 24 and a metal wire electrode 23 .
  • the drain electrode 21, the source electrode 22, the light-shielding electrode 24 and the metal wiring electrode 23 can be obtained by photolithographic patterning of the first electrode layer 20 at one time, which can avoid additionally setting a light-shielding layer and reduce production costs.
  • FIG. 8 is a schematic diagram of a fourth structure of the display panel 100 provided in the present application, which is different from the display panel 100 provided in FIG. 4 in that: the second electrode layer 40 includes a fourth connection electrode 44 , The orthographic projection of the fourth connection electrode 44 on the substrate 10 covers the orthographic projection of the metal wire electrode 23 on the substrate 10, and the first connection electrode 81 passes through the passivation layer 60 and the The via hole on the flat layer 70 is connected to the fourth connection electrode 44 , and the fourth connection electrode 44 is connected to the metal wiring electrode 23 through the via hole on the buffer layer 30 .
  • the fourth connection electrode 44 as the intermediate connection electrode between the first connection electrode 81 and the metal wiring electrode 23
  • the depth of the via hole can be reduced, and the process risk caused by the difference in the depth of the hole during the exposure and etching process is reduced.
  • the stability and process feasibility of the manufacturing process are improved.
  • the etchant will corrode the metal on the metal wire electrode 23.
  • the orthographic projection of the fourth connection electrode 44 on the substrate 10 covers the orthographic projection of the metal wiring electrode 23 on the substrate 10, and can avoid binding of the metal wiring electrode 23 domain at the same time
  • the etchant affects the metal on the metal wiring electrodes 23 , thereby reducing the occurrence of abnormal reliability of the metal wiring electrodes 23 .
  • FIG. 9 is a flow chart of the fourth embodiment of the method for preparing the display panel 100 provided in this application.
  • the difference from the method for preparing the display panel 100 provided in FIG. 5 is that the step S14 includes:
  • the orthographic projection of the fourth connection electrode 44 on the substrate 10 covers the orthographic projection of the metal wire electrode 23 on the substrate 10, and the first connection electrode 81 passes through the passivation layer 60 and the The via hole on the flat layer 70 is connected to the fourth connection electrode 44 , and the fourth connection electrode 44 is connected to the metal wiring electrode 23 through the via hole on the buffer layer 30 .
  • the conductive channel 41 and the fourth connecting electrode 44 can be obtained by photolithography and patterning once on the same electrode layer, which will not have much impact on the manufacturing cost of the product, and can reduce the depth of the via hole , to reduce the process risk caused by the difference in the depth and depth of holes during the exposure and etching process, and at the same time, it can avoid the impact of the etching solution on the metal on the metal wiring electrode 23 .
  • FIG. 10 is a schematic diagram of a fifth structure of a display panel 100 provided in the present application, which is different from the display panel 100 provided in FIG. 1 in that: the display panel 100 further includes: a fourth electrode layer 90 , The fourth electrode layer 90 includes a fifth connection electrode 91, the fifth connection electrode 91 is located between the metal wiring electrode 23 and the buffer layer 30, the fifth connection electrode 91 covers the metal On the wire electrode 23 , the first connection electrode 81 is connected to the fifth connection electrode 91 through the via hole on the buffer layer 30 .
  • the present application provides a fifth connection electrode 91, the metal wiring electrode 23, the fifth connection electrode 91 and the buffer layer 30 are sequentially stacked, and the fifth connection electrode 91 covers the On the metal wire electrode 23, the first connection electrode 81 is connected to the fifth connection electrode 91 through the via hole on the buffer layer 30, and the fifth connection electrode 91 is connected to the metal wire electrode 23, so
  • the etching solution will not affect the metal on the metal wiring electrode 23, and can also improve the coverage of the metal wiring electrode 23, thereby solving the problem of the metal wiring electrode 23.
  • the electrode 23 is prone to a problem of abnormal reliability.
  • the material of the fourth electrode layer 90 includes an alloy of one or more of indium tin oxide, indium gallium zinc oxide, molybdenum titanium, molybdenum titanium nickel and titanium.
  • FIG. 11 is a flow chart of the fifth embodiment of the method for preparing the display panel 100 provided by the present application, which is different from the method for preparing the display panel 100 provided in FIG. Include the following steps:
  • FIG. 12 is a flow chart of step S12 of the fifth embodiment of the manufacturing method of the display panel 100 provided by the present application, wherein the step S12 includes the following steps:
  • the present application by performing photolithographic patterning on the first electrode layer 20 and the fourth electrode layer 90 at one time, not only the drain electrode 21, the source electrode 22 and the metal wiring electrode 23 can be obtained, but also the metal wiring electrode 23 located at the same time can be obtained.
  • the fifth connection electrode 91 on the top improves the processing production efficiency and reduces the production cost.
  • step S13 includes: forming a buffer layer 30 on the fourth electrode layer 90 and the first electrode layer 20 .
  • the step S126 includes:
  • the photoresist layer is subjected to photolithography using a semi-transparent mask to obtain a photoresist pattern, the photoresist pattern includes a first photoresist pattern and a second photoresist pattern, and the thickness of the second photoresist pattern is greater than the thickness of the photoresist pattern. the thickness of the first photoresist pattern.
  • the semi-transparent cover includes a fully transparent area, an opaque area and a second semi-transparent area, the opaque area corresponds to the second photoresist pattern, and the semi-transparent area corresponds to the second photoresist pattern. corresponding to the first photoresist pattern.
  • two photoresist patterns with different thicknesses are formed at one time by using a semi-transparent mask, which can reduce manufacturing steps and greatly improve work efficiency.
  • FIG. 13 is a flowchart of step S128 of the fifth embodiment of the method for manufacturing the display panel 100 provided by the present application. Further, in some embodiments, the step S128 includes the following steps:
  • FIG. 14 is a schematic diagram of a sixth structure of a display panel 100 provided in the present application, which is different from the display panel 100 provided in FIG. 8 in that: the display panel 100 further includes: a fourth electrode layer 90 , The fourth electrode layer 90 includes a fifth connection electrode 91, the fifth connection electrode 91 is located between the metal wiring electrode 23 and the buffer layer 30, the fifth connection electrode 91 covers the metal On the wire electrode 23 , the first connection electrode 81 is connected to the fifth connection electrode 91 through the via hole on the buffer layer 30 .
  • the present application provides a fifth connection electrode 91, the metal wiring electrode 23, the fifth connection electrode 91 and the buffer layer 30 are sequentially stacked, and the fifth connection electrode 91 covers the On the metal wire electrode 23, the first connection electrode 81 is connected to the fifth connection electrode 91 through the via hole on the buffer layer 30, and the fifth connection electrode 91 is connected to the metal wire electrode 23, so
  • the etching solution will not affect the metal on the metal wiring electrode 23, and can also improve the coverage of the metal wiring electrode 23, thereby solving the problem of the metal wiring electrode 23.
  • the electrode 23 is prone to a problem of abnormal reliability.
  • the material of the fourth electrode layer 90 includes an alloy of one or more of indium tin oxide, indium gallium zinc oxide, molybdenum titanium, molybdenum titanium nickel and titanium.
  • FIG. 15 is a flow chart of the sixth embodiment of the method for preparing the display panel 100 provided by the present application. The difference from the method for manufacturing the display panel 100 provided in FIG. include the following steps:
  • step S12 includes the following steps:
  • the photoresist layer performs photolithography processing on the photoresist layer to obtain a photoresist pattern, the photoresist pattern including a first photoresist pattern and a second photoresist pattern;
  • the second photoresist pattern is peeled off to obtain the fifth connection electrode 91 on the metal wire electrode 23 .
  • the present application by performing photolithographic patterning on the first electrode layer 20 and the fourth electrode layer 90 at one time, not only the drain electrode 21, the source electrode 22 and the metal wiring electrode 23 can be obtained, but also the metal wiring electrode 23 located at the same time can be obtained.
  • the fifth connection electrode 91 on the top improves the processing production efficiency and reduces the production cost.
  • step S13 includes: forming a buffer layer 30 on the fourth electrode layer 90 and the first electrode layer 20 .

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Abstract

一种显示面板（100）及显示面板（100）的制备方法。通过将漏电极（21）、源电极（22）和金属走线电极（23）设在第一电极层（20）上，与现有技术相对比至少减少了一层源漏极金属层，使得显示面板（100）的制作过程能减少光掩模的层数，有效地降低了显示面板（100）的制作周期和制作成本。

Description

一种显示面板及显示面板的制备方法 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及显示面板的制备方法。
 背景技术
OLED是一种电流型发光器件，OLED主要包括阳极、阴极以及有机材料功能层。OLED主要的工作原理是：有机材料功能层在阳极和阴极形成的电场的驱动下，通过载流子注入和复合而发光。
现有的OLED显示面板包括：一包含薄膜晶体管(Thin Film Transistor，简称TFT)驱动电路的TFT显示面板，以及设置于TFT显示面板上的多个OLED显示器件，各个OLED显示器件均由对应的TFT控制。印刷OLED产品中，一般采用顶发射型背板，且有机层通过喷墨打印形成。但是现有的OLED产品在印刷过程中，需要制作10层光掩膜和多层无机膜，制作周期长且成本高。
 技术问题
本申请提供一种显示面板及显示面板的制备方法，以降低显示面板制作周期及成本。
 技术解决方案
本申请提供一种显示面板，其包括：
基板；
第一电极层，所述第一电极层设在所述基板上，所述第一电极层包括漏电极、源电极和金属走线电极；
缓冲层，所述缓冲层设在所述第一电极层上；
第二电极层，所述第二电极层设在所述缓冲层上，所述第二电极层包括导电沟道，所述漏电极和所述源电极分别与所述导电沟道连接；
第一绝缘层，所述第一绝缘层设在所述导电沟道上；
栅电极，所述栅电极设在所述第一绝缘层上。
可选的，在本申请一些实施例中，所述第一电极层还包括遮光电极，所述遮光电极在所述基板上的正投影覆盖所述导电沟道在所述基板上的正投影。
可选的，在本申请一些实施例中，所述漏电极、所述遮光电极、所述源电极和所述金属走线电极依次地间隔设置。
可选的，在本申请一些实施例中，所述显示面板还包括：
钝化层，所述钝化层设在所述缓冲层上，并覆盖所述栅电极；
平坦层，所述平坦层设在所述钝化层上。
第三电极层，所述第三电极层设在所述平坦层上，所述第三电极层包括所述第一连接电极和发光OLED器件的阳电极；其中
所述第一连接电极通过所述缓冲层、所述钝化层和所述平坦层上的过孔与所述金属走线电极连接，所述阳电极与所述漏电极连接。
可选的，在本申请一些实施例中，所述第二电极层还包括第二连接电极，所述阳电极通过所述钝化层和所述平坦层上的过孔与所述第二连接电极连接，所述第二连接电极通过所述缓冲层上的过孔与所述漏电极连接。
可选的，在本申请一些实施例中，所述第二连接电极与所述导电沟道连接。
可选的，在本申请一些实施例中，所述第二电极层还包括第三连接电极，所述第三连接电极通过所述缓冲层上的过孔与所述源电极连接，所述第三连接电极与所述导电沟道连接。
可选的，在本申请一些实施例中，所述第二电极层包括第四连接电极，所述第四连接电极在所述基板上的正投影覆盖所述金属走线电极在所述基板上的正投影，所述第一连接电极通过所述钝化层和所述平坦层上的过孔与所述第四连接电极连接，所述第四连接电极通过所述缓冲层上的过孔与所述金属走线电极连接。
可选的，在本申请一些实施例中，所述显示面板还包括：
第四电极层，所述第四电极层包括第五连接电极，所述第五连接电极位于所述金属走线电极与所述缓冲层之间，所述第五连接电极覆盖在所述金属走线电极上，所述第一连接电极通过所述缓冲层上的过孔与所述第五连接电极连接。
可选的，在本申请一些实施例中，所述第一电极层的材料含有铜、钼、钼钛、铝、钛和镍中一种或多种的合金。
可选的，在本申请一些实施例中，所述第四电极层的材料含有铟锡氧化物、铟镓锌氧化物、钼钛、钼钛镍和钛中的一种或多种的合金。
本申请还提供一种显示面板的制备方法，其包括以下步骤：
提供一基板，并在所述基板上制作形成第一电极层；
对所述第一电极层进行光刻图形化，得到漏电极、源电极和金属走线电极；
在所述第一电极层上制作形成缓冲层；
在所述缓冲层上沉积形成第二电极层，并对所述第二电极层上进行光刻图形化得到导电沟道；
在所述导电沟道上制作形成第一绝缘层；
在所述第一绝缘层上制作形成栅电极；
在所述缓冲层上制作形成第一连接电极，其中，所述第一连接电极通过所述缓冲层上的过孔与所述金属走线电极连接。
可选的，在本申请一些实施例中，所述对所述第一电极层进行光刻图形化，得到漏电极、源电极和金属走线电极的步骤包括以下步骤：
在所述第一电极层上涂布光阻层；
对所述光阻层进行光刻处理，得到光阻图案；
将裸露在所述光阻图案外的所述第一电极层刻蚀去除；
剥离所述光阻图案，得到漏电极、源电极和金属走线电极。
可选的，在本申请一些实施例中，所述制备方法还包括以下步骤：
在所述缓冲层上制作形成钝化层，所述钝化层覆盖所述栅电极；
在所述钝化层上制作形成平坦层；
在所述平坦层上制作形成第三电极层，所述第三电极层包括第一连接电极和发光OLED器件的阳电极；其中
所述第一连接电极通过所述缓冲层、所述钝化层和所述平坦层上的过孔与所述第一电极层连接，所述阳电极与所述漏电极连接。
可选的，在本申请一些实施例中，所述对所述第一电极层进行光刻图形化，得到漏电极、源电极和金属走线电极的步骤包括：
对所述第一电极层进行光刻图形化，得到漏电极、源电极、遮光电极和金属走线电极。
可选的，在本申请一些实施例中，在所述对所述第一电极层进行光刻图形化，得到漏电极、源电极和金属走线电极步骤前还包括以下步骤：
在所述第一电极层上制作形成第四电极层；其中，
所述对所述第一电极层进行光刻图形化，得到漏电极、源电极和金属走线电极的步骤包括以下步骤：
在所述第四电极层上涂布光阻层；
对所述光阻层进行光刻处理，得到光阻图案，所述光阻图案包括第一光阻图案以及第二光阻图案；
将裸露在所述光阻图案外的所述第一电极层和所述第四电极层刻蚀去除；
剥离所述第一光阻图案，并将位于所述第一光阻图案下方的所述第一电极层和所述第四电极层刻蚀去除，得到漏电极、源电极和金属走线电极；
剥离所述第二光阻图案，得到位于所述金属走线电极上的第四电极层；
其中，所述在所述第一电极层上制作形成缓冲层的步骤包括：
在所述第四电极层和所述第一电极层上形成缓冲层。
可选的，在本申请一些实施例中，所述对所述光阻层进行光刻处理，得到光阻图案，所述光阻图案包括第一光阻图案以及第二光阻图案的步骤包括：
采用半透光罩对所述光阻层进行光刻处理，得到光阻图案，所述光阻图案包括第一光阻图案以及第二光阻图案，所述第二光阻图案的厚度大于所述第一光阻图案的厚度。
可选的，在本申请一些实施例中，所述剥离所述第一光阻图案，并将位于所述第一光阻图案下方的所述第一电极层和所述第四电极层刻蚀去除，得到漏电极、源电极和金属走线电极的步骤包括：
对所述光阻图案进行灰化减薄处理，剥离所述第一光阻图案；
将位于所述第一光阻图案下方的所述第一电极层和所述第四电极层刻蚀去除，得到漏电极、源电极和金属走线电极。
可选的，在本申请一些实施例中，所述在所述缓冲层上沉积形成第二电极层，并对所述第二电极层上进行光刻图形化得到导电沟道的步骤包括：
在所述缓冲层上沉积形成第二电极层，并对所述第二电极层上进行光刻图形化得到导电沟道和第四连接电极；其中，
所述第四连接电极在所述基板上的正投影覆盖所述金属走线电极在所述基板上的正投影，所述第一连接电极通过所述钝化层和所述平坦层上的过孔与所述第四连接电极连接，所述第四连接电极通过所述缓冲层上的过孔与所述金属走线电极连接。
可选的，在本申请一些实施例中，所述第一电极层的材料含有铜、钼、钼钛、铝、钛和镍中一种或多种的合金。
可选的，在本申请一些实施例中，所述第四电极层的材料含有铟锡氧化物、铟镓锌氧化物、钼钛、钼钛镍和钛中的一种或多种的合金。
 有益效果
本申请提供一种显示面板及显示面板的制备方法。其中，显示面板包括基板；第一电极层，所述第一电极层设在所述基板上，所述第一电极层包括漏电极、源电极和金属走线电极；缓冲层，所述缓冲层设在所述第一电极层上；第二电极层，所述第二电极层设在所述缓冲层上，所述第二电极层包括导电沟道；第一绝缘层，所述第一绝缘层设在所述导电沟道上；栅电极，所述栅电极设在所述第一绝缘层上；第一连接电极，所述第一连接电极设在所述缓冲层上，所述第一连接电极通过所述缓冲层上的过孔与所述金属走线电极连接。本申请通过将漏电极、源电极和金属走线电极设在第一电极层上，本申请与现有技术相对比至少减少了一层源漏极金属层，使得显示面板在制作过程能减少光掩膜的层数，能有效地降低了显示面板的制作周期和制作成本。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图得到其他的附图。
图1为本申请提供的显示面板的第一结构的示意图；
图2为本申请提供的显示面板的制备方法的第一实施例的流程图；
图3为本申请提供的显示面板的制备方法的第一实施例步骤S12的流程图；
图4为本申请提供的显示面板的第二结构的示意图；
图5为本申请提供的显示面板的制备方法的第二实施例的流程图；
图6为本申请提供的显示面板的第三结构的示意图；
图7为本申请提供的显示面板的制备方法的第三实施例的流程图；
图8为本申请提供的显示面板的第四结构的示意图；
图9为本申请提供的显示面板的制备方法的第四实施例的流程图；
图10为本申请提供的显示面板的第五结构的示意图；
图11为本申请提供的显示面板的制备方法的第五实施例的流程图；
图12为本申请提供的显示面板的制备方法的第五实施例步骤12的流程图；
图13为本申请提供的显示面板的制备方法的第五实施例步骤128的流程图；
图14为本申请提供的显示面板的第六结构的示意图；
图15为本申请提供的显示面板的制备方法的第六实施例的流程图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所得到的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“长度”、“宽度”、“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本说明书中，晶体管是指至少包括栅电极、漏极以及源极这三个端子的元件。晶体管在漏极(漏极端子、漏区域或漏极)与源极(源极端子、源区域或源极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。注意，在本说明书中，沟道区域是指电流主要流过的区域。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。
本申请提供一种显示面板100及显示面板100的制造方法，以下进行详细说明。需要说明的是，以下实施例的描述顺序不作为对本申请实施例优选顺序的限定。
请参阅图1，图1为本申请提供的显示面板100的第一结构的示意图。本申请提供一种显示面板100，其包括基板10、第一电极层20、缓冲层30、第二电极层40、第一绝缘层50和栅电极50a。
其中，所述第一电极层20设在所述基板10上，所述第一电极层20包括漏电极21、源电极22和金属走线电极23；所述缓冲层30设在所述第一电极层20上。另外，在一些实施例中，所述基板10为柔性基板，所述第一电极层20的材料含有铜、钼、钼钛、铝、钛和镍中一种或多种的合金。
所述第二电极层40设在所述缓冲层30上，所述第二电极层40包括导电沟道41，所述漏电极21和所述源电极22分别与所述导电沟道41连接；所述第一绝缘层50设在所述导电沟道41上；所述栅电极50a设在所述第一绝缘层50上。
本申请通过将漏电极21、源电极22和金属走线电极23设在第一电极层20上，本申请与现有技术相对比至少减少了一层源漏极金属层，也即是说，通过一层光掩膜光刻处理即能获得漏电极21、源电极22和金属走线电极23，从而使得显示面板100在制作过程能减少光掩膜，综上所述，本申请能有效地降低了显示面板100的制作周期和制作成本。
请参考图2，图2为本申请提供的显示面板100的制备方法的第一实施例的流程图。本申请实施例中还提供一种显示面板100的制备方法，其包括以下步骤：
S11、提供一基板10，并在所述基板10上制作形成第一电极层20；
S12、对所述第一电极层20进行光刻图形化，得到漏电极21、源电极22和金属走线电极23；
S13、在所述第一电极层20上制作形成缓冲层30；
S14、在所述缓冲层30上沉积形成第二电极层40，并对所述第二电极层40上进行光刻图形化得到导电沟道41；
S15、在所述导电沟道41上制作形成第一绝缘层50；
S16、在所述第一绝缘层50上制作形成栅电极50a。
本申请通过一次性对第一电极层20进行光刻图形化，即可得到漏电极21、源电极22和金属走线电极23，本申请与现有技术相对比至少减少了一层源漏极金属层，也即是本申请使得显示面板100在制作过程能至少减少一层光掩膜的使用，从而有效地降低了显示面板100的制作周期和制作成本。
请参考图3，图3为本申请提供的显示面板100的制备方法的第一实施例步骤S12的流程图，在一些实施例中，所述步骤S12包括以下步骤：
S121、在所述第一电极层20上涂布光阻层；
S122、对所述光阻层进行光刻处理，得到光阻图案；
S123、将裸露在所述光阻图案外的所述第一电极层20刻蚀去除；
S124、剥离所述光阻图案，得到漏电极21、源电极22和金属走线电极23。
请参考图4，图4为本申请提供的显示面板100的第二结构的示意图，其与图1所提供的显示面板不同的是：所述显示面板100还包括：
钝化层60，所述钝化层60设在所述缓冲层30上，并覆盖所述栅电极50a；
平坦层70，所述平坦层70设在所述钝化层60上。
第三电极层80，所述第三电极层80设在所述平坦层70上，所述第三电极层80包括所述第一连接电极81和发光OLED器件的阳电极82；其中
所述第一连接电极81通过所述缓冲层30、所述钝化层60和所述平坦层70上的过孔与所述金属走线电极23连接，所述阳电极82与所述漏电极21连接。所述第一连接电极81作为所述金属走线电极23的接线端子。
本申请通过将漏电极21、源电极22和金属走线电极23设在第一电极层20上，而导电沟道41设在第二电极层40上，栅电极50a设在导电沟道41上，不再设介电层，因此可以减少无机膜的层数，由于缓冲层30将漏电极21、源电极22与栅电极50a隔开，即使没有介电层也能保证漏电极21、源电极22与栅电极50a之间的绝缘性。
另外，在一些实施例中，所述第二电极层40还包括第二连接电极42，所述阳电极82通过所述钝化层60和所述平坦层70上的过孔与所述第二连接电极42连接，所述第二连接电极42通过所述缓冲层30上的过孔与所述漏电极21连接。通过设有第二连接电极42作为阳电极82与漏电极21之间的中间连接电极，可以减少过孔的深度，降低了曝光和蚀刻过程中由于深浅孔差异导致的工艺风险，提高了制程的稳定性和工艺可行性。
进一步地，在一些实施例中，所述第二连接电极42与所述导电沟道41连接。在上述基础上，通过第二连接电极42实现导电沟道41与漏电极21之间的连接，可以减少连接电极和过孔设置。
在一些实施例中，所述第二电极层40还包括第三连接电极43，所述第三连接电极43通过所述缓冲层30上的过孔与所述源电极22连接，所述第三连接电极43与所述导电沟道41连接。
需要说明的是，上述显示面板100实施例中仅描述了上述结构，可以理解的是，除了上述结构之外，本申请实施例显示面板100中，还可以根据需要包括任何其他的必要结构，例如偏光片以及盖板等，具体此处不作限定。
请参考图5，图5为本申请提供的显示面板100的制备方法的第二实施例的流程图，其与图2所提供的制备方法不同的是：所述制备方法还包括以下步骤：
S17、在所述缓冲层30上制作形成钝化层60，所述钝化层60覆盖所述栅电极50a；
S18、在所述钝化层60上制作形成平坦层70；
S19、在所述平坦层70上制作形成第三电极层80，所述第三电极层80包括第一连接电极81和发光OLED器件的阳电极82；其中
所述第一连接电极81通过所述缓冲层30、所述钝化层60和所述平坦层70上的过孔与所述第一电极层20连接，所述阳电极82与所述漏电极21连接。
请参阅图6，图6为本申请提供的显示面板100的第三结构的示意图，其与图1所提供的显示面板100不同的是：所述第一电极层20包括漏电极21、源电极22、遮光电极24和金属走线电极23，所述遮光电极24在所述基板10上的正投影覆盖所述导电沟道41在所述基板10上的正投影。将漏电极21、源电极22、遮光电极24和金属走线电极23同时设在第一电极层20，不仅减少了一层源漏极金属层，而且还可以避免另外设置遮光层，降低生产成本。
进一步地，在一些实施例中，所述漏电极21、所述遮光电极24、所述源电极22和所述金属走线电极23依次地间隔设置，将遮光电极24设置在漏电极21和源电极22之间，可以便于遮光电极24与导电沟道41相对应设置，同时也可以增加漏电极21和源电极22绝缘距离，增强两者的绝缘效果。
请参考图7，图7为本申请提供的显示面板100的制备方法的第三实施例的流程图，其与图2提供的显示面板100的制备方法不同的是：所述步骤S12包括：
对所述第一电极层20进行光刻图形化，得到漏电极21、源电极22、遮光电极24和金属走线电极23。本申请通过一次性对第一电极层20进行光刻图形化，即可得到漏电极21、源电极22、遮光电极24和金属走线电极23，可以避免另外设置遮光层，并降低生产成本。
请参阅图8，图8为本申请提供的显示面板100的第四结构的示意图，其与图4所提供的显示面板100不同的是：所述第二电极层40包括第四连接电极44，所述第四连接电极44在所述基板10上的正投影覆盖所述金属走线电极23在所述基板10上的正投影，所述第一连接电极81通过所述钝化层60和所述平坦层70上的过孔与所述第四连接电极44连接，所述第四连接电极44通过所述缓冲层30上的过孔与所述金属走线电极23连接。
通过设有第四连接电极44作为第一连接电极81与金属走线电极23之间的中间连接电极，可以减少过孔的深度，降低了曝光和蚀刻过程中由于深浅孔差异导致的工艺风险，提高了制程的稳定性和工艺可行性。
而且现有的显示面板100在制作金属走线电极23域的绑定接线端子过程中，刻蚀液会腐蚀到金属走线电极23上的金属，本申请通过在第二电极层40设有第四连接电极44，第四连接电极44在所述基板10上的正投影覆盖所述金属走线电极23在所述基板10上的正投影，同时可以避免在制作金属走线电极23域的绑定接线端子过程中刻蚀液对金属走线电极23上的金属产生影响，而降低金属走线电极23出现可靠性异常的情况。
请参考图9，图9为本申请提供的显示面板100的制备方法的第四实施例的流程图，其与图5提供的显示面板100的制备方法不同的是：所述步骤S14包括：
在所述缓冲层30上沉积形成第二电极层40，并对所述第二电极层40上进行光刻图形化得到导电沟道41和第四连接电极44；其中，
所述第四连接电极44在所述基板10上的正投影覆盖所述金属走线电极23在所述基板10上的正投影，所述第一连接电极81通过所述钝化层60和所述平坦层70上的过孔与所述第四连接电极44连接，所述第四连接电极44通过所述缓冲层30上的过孔与所述金属走线电极23连接。
在本申请中，导电沟道41和第四连接电极44可以在同一电极层上经过一次光刻图形化即可得到，不会对产品的制造成本产生多大的影响，既可以减少过孔的深度，降低曝光和蚀刻过程中由于深浅孔差异导致的工艺风险，同时可以避免刻蚀液对金属走线电极23上的金属产生影响。
请参阅图10，图10为本申请提供的显示面板100的第五结构的示意图，其与图1所提供的显示面板100不同的是：所述显示面板100还包括：第四电极层90，所述第四电极层90包括第五连接电极91，所述第五连接电极91位于所述金属走线电极23与所述缓冲层30之间，所述第五连接电极91覆盖在所述金属走线电极23上，所述第一连接电极81通过所述缓冲层30上的过孔与所述第五连接电极91连接。
现有的显示面板100在制作金属走线电极23的绑定接线端子过程中，刻蚀液会腐蚀到金属走线电极23上的金属，而且缓冲层30与金属走线电极23的覆盖性本来存在瑕疵，上述两个情况都导致绑定接线端子在与走线进行绑定连接后金属走线电极23容易会出现可靠性异常，而影响显示面板100的质量。
有鉴于此，本申请通过设有第五连接电极91，所述金属走线电极23、所述第五连接电极91与所述缓冲层30依次层叠设置，所述第五连接电极91覆盖在所述金属走线电极23上，第一连接电极81通过所述缓冲层30上的过孔与所述第五连接电极91连接，所述第五连接电极91再与金属走线电极23连接，因此在制作金属走线电极23域的绑定接线端子过程中刻蚀液不会对金属走线电极23上的金属产生影响，同时也可以提高金属走线电极23的覆盖性，从而解决金属走线电极23容易会出现可靠性异常的问题。
进一步地，在一些实施例中，所述第四电极层90的材料含有铟锡氧化物、铟镓锌氧化物、钼钛、钼钛镍和钛中的一种或多种的合金。
请参考图11，图11为本申请提供的显示面板100的制备方法的第五实施例的流程图，其与图2提供的显示面板100的制备方法不同的是：在所述步骤S12前还包括以下步骤：
S20、在所述第一电极层20上制作形成第四电极层90。
请参考图12，图12为本申请提供的显示面板100的制备方法的第五实施例步骤S12的流程图，其中，所述步骤S12包括以下步骤：
S125、在所述第四电极层90上涂布光阻层；
S126、对所述光阻层进行光刻处理，得到光阻图案，所述光阻图案包括第一光阻图案以及第二光阻图案；
S127、将裸露在所述光阻图案外的所述第一电极层20和所述第四电极层90刻蚀去除；
S128、剥离所述第一光阻图案，并将位于所述第一光阻图案下方的所述第一电极层20和所述第四电极层90刻蚀去除，得到漏电极21、源电极22和金属走线电极23；
S129、剥离所述第二光阻图案，得到位于所述金属走线电极23上的第五连接电极91。
本申请通过一次性对第一电极层20和第四电极层90进行光刻图形化，不仅可得到漏电极21、源电极22和金属走线电极23，同时得到位于所述金属走线电极23上的第五连接电极91，提高了加工生产效率并降低生产成本。
请参考图11，其中，所述步骤S13包括：在所述第四电极层90和所述第一电极层20上形成缓冲层30。
在一些实施例中，所述步骤S126包括：
采用半透光罩对所述光阻层进行光刻处理，得到光阻图案，所述光阻图案包括第一光阻图案以及第二光阻图案，所述第二光阻图案的厚度大于所述第一光阻图案的厚度。
所述半透光罩包括全透光区域、不透光区域和第二半透光区域，所述不透光区域与所述第二光阻图案相对应，所述半透光区域与所述第一光阻图案相对应。本申请利用半透光罩一次性形成两个厚度不同的光阻图案，可以减少制作步骤，并大大地提高了工作效率。
请参考图13，图13为本申请提供的显示面板100的制备方法的第五实施例步骤S128的流程图，进一步地，在一些实施例中，所述步骤S128包括以下步骤：
S1281、对所述光阻图案进行灰化减薄处理，剥离所述第一光阻图案；
S1282、将位于所述第一光阻图案下方的所述第一电极层20和所述第四电极层90刻蚀去除，得到漏电极21、源电极22和金属走线电极23。
请参阅图14，图14为本申请提供的显示面板100的第六结构的示意图，其与图8所提供的显示面板100不同的是：所述显示面板100还包括：第四电极层90，所述第四电极层90包括第五连接电极91，所述第五连接电极91位于所述金属走线电极23与所述缓冲层30之间，所述第五连接电极91覆盖在所述金属走线电极23上，所述第一连接电极81通过所述缓冲层30上的过孔与所述第五连接电极91连接。
现有的显示面板100在制作金属走线电极23的绑定接线端子过程中，刻蚀液会腐蚀到金属走线电极23上的金属，而且缓冲层30与金属走线电极23的覆盖性本来存在瑕疵，上述两个情况都导致绑定接线端子在与走线进行绑定连接后金属走线电极23容易会出现可靠性异常，而影响显示面板100的质量。
有鉴于此，本申请通过设有第五连接电极91，所述金属走线电极23、所述第五连接电极91与所述缓冲层30依次层叠设置，所述第五连接电极91覆盖在所述金属走线电极23上，第一连接电极81通过所述缓冲层30上的过孔与所述第五连接电极91连接，所述第五连接电极91再与金属走线电极23连接，因此在制作金属走线电极23域的绑定接线端子过程中刻蚀液不会对金属走线电极23上的金属产生影响，同时也可以提高金属走线电极23的覆盖性，从而解决金属走线电极23容易会出现可靠性异常的问题。
进一步地，在一些实施例中，所述第四电极层90的材料含有铟锡氧化物、铟镓锌氧化物、钼钛、钼钛镍和钛中的一种或多种的合金。
请参考图15，图15为本申请提供的显示面板100的制备方法的第六实施例的流程图，其与图9提供的显示面板100的制备方法不同的是：在所述步骤S12前还包括以下步骤：
S20、在所述第一电极层20上制作形成第四电极层90。
其中，所述步骤S12包括以下步骤：
在所述第四电极层90上涂布光阻层；
对所述光阻层进行光刻处理，得到光阻图案，所述光阻图案包括第一光阻图案以及第二光阻图案；
将裸露在所述光阻图案外的所述第一电极层20和所述第四电极层90刻蚀去除；
剥离所述第一光阻图案，并将位于所述第一光阻图案下方的所述第一电极层20和所述第四电极层90刻蚀去除，得到漏电极21、源电极22和金属走线电极23；
剥离所述第二光阻图案，得到位于所述金属走线电极23上的第五连接电极91。
本申请通过一次性对第一电极层20和第四电极层90进行光刻图形化，不仅可得到漏电极21、源电极22和金属走线电极23，同时得到位于所述金属走线电极23上的第五连接电极91，提高了加工生产效率并降低生产成本。
请参考图15，其中，所述步骤S13包括：在所述第四电极层90和所述第一电极层20上形成缓冲层30。
以上对本申请实施例所提供的一种显示面板及显示面板的制造方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其中，包括：
    基板；
    第一电极层，所述第一电极层设在所述基板上，其中，所述第一电极层包括漏电极、源电极和金属走线电极；
    缓冲层，所述缓冲层设在所述第一电极层上；
    第二电极层，所述第二电极层设在所述缓冲层上，所述第二电极层包括导电沟道，所述漏电极和所述源电极分别与所述导电沟道连接；
    第一绝缘层，所述第一绝缘层设在所述导电沟道上；
    栅电极，所述栅电极设在所述第一绝缘层上。
  2. 根据权利要求1所述的显示面板，其中，所述第一电极层还包括遮光电极，所述遮光电极在所述基板上的正投影覆盖所述导电沟道在所述基板上的正投影。
  3. 根据权利要求2所述的显示面板，其中，所述漏电极、所述遮光电极、所述源电极和所述金属走线电极依次地间隔设置。
  4. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    钝化层，所述钝化层设在所述缓冲层上，并覆盖所述栅电极；
    平坦层，所述平坦层设在所述钝化层上。
    第三电极层，所述第三电极层设在所述平坦层上，所述第三电极层包括第一连接电极和发光OLED器件的阳电极；其中
    所述第一连接电极通过所述缓冲层、所述钝化层和所述平坦层上的过孔与所述金属走线电极连接，所述阳电极与所述漏电极连接。
  5. 根据权利要求4所述的显示面板，其中，所述第二电极层还包括第二连接电极，所述阳电极通过所述钝化层和所述平坦层上的过孔与所述第二连接电极连接，所述第二连接电极通过所述缓冲层上的过孔与所述漏电极连接。
  6. 根据权利要求1所述的显示面板，其中，所述第二电极层还包括第三连接电极，所述第三连接电极通过所述缓冲层上的过孔与所述源电极连接，所述第三连接电极与所述导电沟道连接。
  7. 根据权利要求4所述的显示面板，其中，所述第二电极层包括第四连接电极，所述第四连接电极在所述基板上的正投影覆盖所述金属走线电极在所述基板上的正投影，所述第一连接电极通过所述钝化层和所述平坦层上的过孔与所述第四连接电极连接，所述第四连接电极通过所述缓冲层上的过孔与所述金属走线电极连接。
  8. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    第四电极层，所述第四电极层包括第五连接电极，所述第五连接电极位于所述金属走线电极与所述缓冲层之间，所述第五连接电极覆盖在所述金属走线电极上，所述第一连接电极通过所述缓冲层上的过孔与所述第五连接电极连接。
  9. 根据权利要求1所述的显示面板，其中，所述第一电极层的材料含有铜、钼、钼钛、铝、钛和镍中一种或多种的合金。
  10. 根据权利要求8所述的显示面板，其中，所述第四电极层的材料含有铟锡氧化物、铟镓锌氧化物、钼钛、钼钛镍和钛中的一种或多种的合金。
  11. 一种显示面板的制备方法，其中，包括以下步骤：
    提供一基板，并在所述基板上制作形成第一电极层；
    对所述第一电极层进行光刻图形化，得到漏电极、源电极和金属走线电极；
    在所述第一电极层上制作形成缓冲层；
    在所述缓冲层上沉积形成第二电极层，并对所述第二电极层上进行光刻图形化得到导电沟道；
    在所述导电沟道上制作形成第一绝缘层；
    在所述第一绝缘层上制作形成栅电极。
  12. 根据权利要求11所述的制备方法，其中，所述对所述第一电极层进行光刻图形化，得到漏电极、源电极和金属走线电极的步骤包括以下步骤：
    在所述第一电极层上涂布光阻层；
    对所述光阻层进行光刻处理，得到光阻图案；
    将裸露在所述光阻图案外的所述第一电极层刻蚀去除；
    剥离所述光阻图案，得到漏电极、源电极和金属走线电极。
  13. 根据权利要求11所述的制备方法，其中，所述制备方法还包括以下步骤：
    在所述缓冲层上制作形成钝化层，所述钝化层覆盖所述栅电极；
    在所述钝化层上制作形成平坦层；
    在所述平坦层上制作形成第三电极层，所述第三电极层包括第一连接电极和发光OLED器件的阳电极；其中
    所述第一连接电极通过所述缓冲层、所述钝化层和所述平坦层上的过孔与所述第一电极层连接，所述阳电极与所述漏电极连接。
  14. 根据权利要求11所述的制备方法，其中，所述对所述第一电极层进行光刻图形化，得到漏电极、源电极和金属走线电极的步骤包括：
    对所述第一电极层进行光刻图形化，得到漏电极、源电极、遮光电极和金属走线电极。
  15. 根据权利要求11所述的制备方法，其中，在所述对所述第一电极层进行光刻图形化，得到漏电极、源电极和金属走线电极步骤前还包括以下步骤：
    在所述第一电极层上制作形成第四电极层；
    其中，所述对所述第一电极层进行光刻图形化，得到漏电极、源电极和金属走线电极的步骤包括以下步骤：
    在所述第四电极层上涂布光阻层；
    对所述光阻层进行光刻处理，得到光阻图案，所述光阻图案包括第一光阻图案以及第二光阻图案；
    将裸露在所述光阻图案外的所述第一电极层和所述第四电极层刻蚀去除；
    剥离所述第一光阻图案，并将位于所述第一光阻图案下方的所述第一电极层和所述第四电极层刻蚀去除，得到漏电极、源电极和金属走线电极；
    剥离所述第二光阻图案，得到位于所述金属走线电极上的第四电极层；
    其中，所述在所述第一电极层上制作形成缓冲层的步骤包括：
    在所述第四电极层和所述第一电极层上形成缓冲层。
  16. 根据权利要求15所述的制备方法，其中，所述对所述光阻层进行光刻处理，得到光阻图案，所述光阻图案包括第一光阻图案以及第二光阻图案的步骤包括：
    采用半透光罩对所述光阻层进行光刻处理，得到光阻图案，所述光阻图案包括第一光阻图案以及第二光阻图案，所述第二光阻图案的厚度大于所述第一光阻图案的厚度。
  17. 根据权利要求16所述的制备方法，其中，所述剥离所述第一光阻图案，并将位于所述第一光阻图案下方的所述第一电极层和所述第四电极层刻蚀去除，得到漏电极、源电极和金属走线电极的步骤包括：
    对所述光阻图案进行灰化减薄处理，剥离所述第一光阻图案；
    将位于所述第一光阻图案下方的所述第一电极层和所述第四电极层刻蚀去除，得到漏电极、源电极和金属走线电极。
  18. 根据权利要求13所述的制备方法，其中，所述在所述缓冲层上沉积形成第二电极层，并对所述第二电极层上进行光刻图形化得到导电沟道的步骤包括：
    在所述缓冲层上沉积形成第二电极层，并对所述第二电极层上进行光刻图形化得到导电沟道和第四连接电极；其中，
    所述第四连接电极在所述基板上的正投影覆盖所述金属走线电极在所述基板上的正投影，所述第一连接电极通过所述钝化层和所述平坦层上的过孔与所述第四连接电极连接，所述第四连接电极通过所述缓冲层上的过孔与所述金属走线电极连接。
  19. 根据权利要求11所述的制备方法，其中，所述第一电极层的材料含有铜、钼、钼钛、铝、钛和镍中一种或多种的合金。
  20. 根据权利要求15所述的制备方法，其中，所述第四电极层的材料含有铟锡氧化物、铟镓锌氧化物、钼钛、钼钛镍和钛中的一种或多种的合金。
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