CN113871346A - 阵列基板及其制备方法和显示面板 - Google Patents
阵列基板及其制备方法和显示面板 Download PDFInfo
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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Abstract
本申请公开了一种阵列基板及其制备方法和显示面板，阵列基板的制备方法，包括：提供一基板；在基板上依次层叠设置有源层、栅极绝缘层和栅极，采用一道光罩对有源层、栅极绝缘层和栅极进行图形化处理，形成有源部、栅极绝缘部和栅极部，有源部、栅极绝缘部和栅极部依次层叠设置；在基板、有源部、栅极绝缘部和栅极部设置层间介质层，在本申请中，通过一道光罩形成有源部、栅极绝缘部和栅极部，从而简化了阵列基板的制备工艺，并降低成本。
Description
技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板及其制备方法和显示面板。
背景技术
薄膜晶体管(thin film transistor,TFT)是显示器的关键驱动元件。TFT的制备工艺决定了显示质量，更决定了显示器成本的高低。
当下主流的TFT结构主要有背沟道(Back chanel etch，BCE)型和顶栅(Top Gate，TG)型，其中BCE型TFT由于半导体层的背沟道容易在源漏极(Source/Drain Electrode，S/D)刻蚀时受到损伤，所以器件性能通常难以达到最佳。而TG型TFT，半导体层图形化后被绝缘层覆盖保护，再沉积S/D并图形化，避免了S/D图形化过程中对半导体层的损伤，因此TG型TFT器件性能可以做到非常优异的程度。但是，目前用于制备TG型TFT器件需要多道光罩，使得制备工艺复杂，制造成本较高。
发明内容
本申请实施例提供一种阵列基板及其制备方法和显示面板，以节省光罩的次数。
本申请提供一种阵列基板的制备方法，包括：
提供一基板；
在所述基板上依次层叠设置有源层、栅极绝缘层和栅极，采用一道光罩对所述有源层、所述栅极绝缘层和所述栅极进行图形化处理，所述有源层形成有源部，所述栅极绝缘层形成栅极绝缘部，所述栅极形成栅极部，所述有源部、所述栅极绝缘部和所述栅极部依次层叠设置；以及
在所述基板、所述有源部、所述栅极绝缘部和所述栅极部设置层间介质层。
可选的，在本申请的一些实施例中，所述形成有源部、栅极绝缘部和栅极部的步骤包括：
在所述基板上依次层叠设置有源层、栅极绝缘层和栅极，采用一道光罩对所述有源层、所述栅极绝缘层和所述栅极进行图形化处理，所述有源层形成有源部和第一极板，所述栅极绝缘层形成栅极绝缘部和附加部，所述栅极形成金属部和栅极部，所述有源部、所述栅极绝缘部和所述栅极部依次层叠设置，所述第一极板、所述附加部和所述金属部依次层叠设置，所述有源部、所述栅极绝缘部以及所述栅极部与所述第一极板、所述附加部和所述金属部之间具有间隙；以及
去除所述附加部和所述金属部。
可选的，在本申请的一些实施例中，所述去除所述附加部和所述金属部的步骤包括：
对所述栅极部和所述金属部进行第一次蚀刻，去除所述金属部和部分所述栅极部，以暴露所述附加部和部分所述栅极绝缘部；以及
对所述附加部和所述栅极绝缘部进行第二次蚀刻，去除所述附加部和部分所述栅极绝缘部，以暴露所述第一极板和部分所述有源部。
可选的，在本申请的一些实施例中，在暴露所述第一极板和部分所述有源部之后，还包括：
对所述第一极板和部分所述有源部进行导体化处理，以在所述有源部上形成与所述栅极绝缘部层叠的半导体区和围绕所述半导体区设置的导通区。
可选的，在本申请的一些实施例中，所述在所述基板、所述有源部、所述栅极绝缘部和所述栅极部上设置层间介质层之后，还包括：
对所述层间介质层进行第三次蚀刻处理，以在所述层间介质层上形成第一通孔和第二通孔，所述第一通孔和所述第二通孔位于所述栅极部的相对两侧，并且，所述第一通孔和所述第二通孔贯穿所述层间介质层以暴露所述有源部的导通区。
可选的，在本申请的一些实施例中，所述在对所述层间介质层进行第三次蚀刻处理的步骤之后，还包括：
在所述层间介质层上形成金属层，并图案化所述金属层，以形成源极和漏极，所述源极延伸入所述第一通孔中与所述有源部连接，所述漏极延伸入所述第二通孔中与所述有源部连接；以及
在所述层间介质层、所述源极和所述漏极上设置钝化层，并对所述钝化层进行第四次蚀刻处理，以在所述钝化层上形成第三通孔，所述第三通孔贯穿所述钝化层并暴露所述漏极。
可选的，在本申请的一些实施例中，所述在对所述钝化层进行第四次蚀刻处理的步骤之后，还包括：
在所述钝化层上形成导电层，并图案化所述导电层以形成像素电极所述像素电极延伸入所述第三通孔中与所述漏极连接，所述第一极板在所述基板上的正投影位于所述像素电极在所述基板上的正投影中。
可选的，在本申请的一些实施例中，所述提供一基板的步骤包括：
提供一衬底，在所述衬底上形成缓冲层。
相应的，本申请还提供一种阵列基板，包括：
基板；
有源部和第一极板，所述有源部和所述第一极板同层设置于所述基板上，所述第一极板和所述有源部之间具有间隙；
栅极绝缘部，所述栅极绝缘部设置于有源部上；
栅极部，所述栅极部设置于所述栅极绝缘部上；
层间介质层，所述层间介质层覆盖所述基板、所述有源部、所述栅极绝缘部和所述栅极部；以及
像素电极，所述像素电极设置于所述层间介质层上，所述第一极板在所述基板上的正投影位于所述像素电极在所述基板上的正投影中。
相应的，本申请还提供一种显示面板，所述显示面板包括对置基板、液晶层和如上所述的阵列基板，所述对置基板与所述阵列基板相对间隔设置，所述液晶层设置在所述对置基板与所述阵列基板之间。
本申请公开了一种阵列基板及其制备方法和显示面板，阵列基板的制备方法，包括：提供一基板；在基板上依次层叠设置有源层、栅极绝缘层和栅极，采用一道光罩对有源层、栅极绝缘层和栅极进行图形化处理，形成有源部、栅极绝缘部和栅极部，有源部、栅极绝缘部和栅极部依次层叠设置；在基板、有源部、栅极绝缘部和栅极部设置层间介质层，在本申请中，通过一道光罩形成有源部、栅极绝缘部和栅极部，从而简化了阵列基板的制备工艺以及避免阵列基板的损伤，并降低成本以及提高阵列基板的性能。将第一极板在基板上的正投影设置为位于像素电极在基板上的正投影中，使得像素电极可以复用为存储电容的第二极板，且，像素电极由透明材料形成，可以提高阵列基板的透过率，从而提高阵列基板的性能。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的阵列基板的结构示意图。
图2是本申请实施例提供的阵列基板的制备方法的流程图。
图3是本申请实施例提供的阵列基板的制备方法的第一结构流程图。
图4是本申请实施例提供的阵列基板的制备方法的第二结构流程图。
图5是本申请实施例提供的阵列基板的制备方法的第三结构流程图。
图6是本申请实施例提供的阵列基板的制备方法的第四结构流程图。
图7是本申请实施例提供的阵列基板的制备方法的第五结构流程图。
图8是本申请实施例提供的阵列基板的制备方法的第六结构流程图。
图9是本申请实施例提供的阵列基板的制备方法的第七结构流程图。
图10是本申请实施例提供的阵列基板的制备方法的第八结构流程图。
图11是本申请实施例提供的阵列基板的制备方法的第九结构流程图。
图12是本申请实施例提供的阵列基板的制备方法的第十结构流程图。
图13是本申请实施例提供的阵列基板的制备方法的第十一结构流程图。
图14是本申请实施例提供的阵列基板的制备方法的第十二结构流程图。
图15是本申请实施例提供的阵列基板的制备方法的第十三结构流程图。
图16是现有技术中的阵列基板的制备方法的第一结构流程图。
图17是现有技术中的阵列基板的制备方法的第二结构流程图。
图18是现有技术中的阵列基板的制备方法的第三结构流程图。
图19是现有技术中的阵列基板的制备方法的第四结构流程图。
图20是现有技术中的阵列基板的制备方法的第五结构流程图。
图21是现有技术中的阵列基板的制备方法的第六结构流程图。
图22是现有技术中的阵列基板的制备方法的第七结构流程图。
图23是现有技术中的阵列基板的制备方法的第八结构流程图。
图24是现有技术中的阵列基板的制备方法的第九结构流程图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。在本申请中，“反应”可以为化学反应或物理反应。
本申请实施例提供一种阵列基板及其制备方法和显示面板。以下分别进行详细说明。
请参阅图1，图1是本申请实施例提供的阵列基板的结构示意图。本申请提供一种阵列基板10。阵列基板10包括基板100、有源部200、第一极板299、栅极绝缘部300、栅极部400、像素电极499和层间介质层500。
基板100包括衬底110和缓冲层120。缓冲层120设置在衬底110上。衬底110包括刚性衬底和柔性衬底中的一种或几种组合。刚性衬底可以为玻璃。柔性衬底的材料包括聚酰亚胺(PI)、聚碳酸酯(PC)、聚醚砜(PES)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、多芳基化合物(PAR)和玻璃纤维增强塑料(FRP)中的一种或几种组合。在本申请中，在基板100中设置缓冲层120，可以提高基板100的水氧阻隔性能，并可以提高基板100的柔性，进而提高阵列基板10的性能。
在一实施例中，缓冲层120的材料包括氮化硅、氧化铝、氮氧化硅、氧化硅、甲基丙烯酸甲酯、环氧树脂、聚碳酸酯、聚苯乙烯和酚醛树脂中的一种或几种组合。
在一实施例中，基板100可以由多层衬底110和缓冲层120交替形成。
有源部200和第一极板299同层设置在缓冲层120上。有源部200和第一极板299之间具有间隙。有源部200设置有半导体区和位于半导体区两侧的导通区。在本申请中，源极600和漏极700与有源部200的导通区电性接触，从而提高阵列基板10的性能。
在一实施例中，有源部200的材料包括含有In、Ga、Zn、Sn、Pr、Nd、Sc和O中的一种或几种组合的氧化物。如，有源部200和第一极板299的材料可以为铟镓锌氧化物、氧化锌和氧化铟锡中的一种或几种组合。在本实施例中，有源部200的材料为铟镓锌氧化物。
在另一实施例中，有源部200和第一极板299的材料包括非晶硅、多晶硅和有机化合物中的一种或几种组合。
栅极绝缘部300和栅极部400依次层叠设置于有源部200上的半导体区内。栅极绝缘部300的材料包括氮化硅、氧化铝、氮氧化硅和氧化硅中的一种或几种组合。栅极部400的材料包括Mo、Cu、Al和Ti中的一种或几种组合。
现有技术中，有源部需要采用一道光罩形成，栅极绝缘部和栅极部也需要采用一道光罩形成，即现有技术中的阵列基板需要采用多道光罩形成，使得阵列基板的制备工艺复杂化，且生产周期长，进而使得成本升高；而在本申请，有源部200、栅极绝缘部300和栅极部400采用同一道光罩形成，节省了光罩次数，即，简化了阵列基板10的制备工序，进而降低了成本。有源部200、栅极绝缘部300和栅极部400采用同一道光罩形成，可以避免阵列基板中的其他膜层受到损伤，从而提高阵列基板10的性能。
层间介质层500覆盖于基板100、有源部200、栅极绝缘部300和栅极部400上。层间介质层500上设置有第一通孔501和第二通孔502。第一通孔501和第二通孔502位于栅极部400的相对两侧，并且第一通孔501和第二通孔502贯穿层间介质层500以暴露有源部200的导通区。
在一实施例中，阵列基板10还包括源极600和漏极700。源极600和漏极700设置在层间介质层500上，并分别延伸入第一通孔501和第二通孔502中与有源部200的上表面连接。
在另一实施例中，源极600和漏极700分别延伸入第一通孔501和第二通孔502中与有源部200的侧面连接。
在一实施例中，阵列基板10还包括钝化层800。钝化层800覆盖于层间介质层500、源极600和漏极700上。钝化层800设置有第三通孔801。第三通孔801贯穿钝化层800以暴露漏极700。
像素电极499设置在钝化层800上，并延伸入第三通孔801中与漏极700连接。第一极板299在基板100上的正投影位于像素电极499在基板100上的正投影中。像素电极499可以作为第二极板与第一极板299构成存储电容。
在本申请中，将第一极板299在基板100上的正投影设置为位于像素电极499在基板100上的正投影中，使得像素电极499可以复用为存储电容的第二极板，从而简化了制备工艺，并降低成本，且像素电极499由透明材料形成，可以提高阵列基板10的透过率。
本申请提供一种阵列基板10，阵列基板10包括基板100、有源部200、第一极板299、栅极绝缘部300、栅极部400、像素电极499和层间介质层500，有源部200、栅极绝缘部300和栅极部400采用同一道光罩形成，节省了光罩次数，即，简化了阵列基板10的制备工序，进而降低了成本。有源部200、栅极绝缘部300和栅极部400采用同一道光罩形成，可以避免阵列基板中的其他膜层受到损伤，从而提高阵列基板10的性能。将第一极板299在基板100上的正投影设置为位于像素电极499在基板100上的正投影中，使得像素电极499可以复用为存储电容的第二极板，从而简化了制备工艺，并降低成本，且像素电极499由透明材料形成，可以提高阵列基板10的透过率。
本申请还提供一种显示面板，显示面板包括本申请提供的阵列基板10，具有本申请所述的所有特征。
请参阅图1至图15，图2是本申请实施例提供的阵列基板的制备方法的流程图。本申请还提供一种阵列基板的制备方法，包括：
B11、提供一基板。
请参阅图3。提供一衬底110，在衬底110上设置氮氧化硅形成缓冲层120。
B12、在基板上依次层叠设置有源层、栅极绝缘层和栅极，采用一道光罩对有源层、栅极绝缘层和栅极进行图形化处理，形成有源部、栅极绝缘部和栅极部，有源部、栅极绝缘部和栅极部依次层叠设置。
请参阅图3-图6。具体的，在缓冲层120上采用物理气相沉积方式沉积铟镓锌氧化物形成有源层201。然后，在有源层201上采用化学气相沉积方式沉积氧化硅形成栅极绝缘层301。然后，在栅极绝缘层301上采用物理气相沉积方式沉积金属形成栅极401。然后，在栅极401上涂布光刻胶材料，并使用半色调光罩进行曝光显影图形化，光刻胶材料形成第一光刻胶900和第二光刻胶1000，第一光刻胶900和第二光刻胶1000之间具有间隙。第二光刻胶1000包括第一部分1010和围绕第一部分1010设置的第二部分1020。第一部分1010的垂直截面的厚度大于第二部分1020的垂直截面的厚度。第二部分1020的厚度与第一光刻胶900的厚度相同。
请参阅图7，然后，对栅极401进行湿法蚀刻，栅极401形成金属部402和栅极部400。金属部402与栅极部400之间具有间隙。金属部402位于第一光刻胶900的正下方，栅极部400位于第二光刻胶1000的正下方。
请参阅图8，然后，对栅极绝缘层301进行干法蚀刻，形成栅极绝缘部300和附加部303。栅极绝缘部300与附加部303之间具有间隙。附加部303位于金属部402的正下方。栅极绝缘部300位于栅极部400的正下方。
请参阅图9，然后，对有源层201进行湿法蚀刻，形成有源部200和第一极板299。有源部200与第一极板299之间具有间隙。第一极板299位于附加部303的正下方。有源部200位于栅极绝缘部300的正下方。
请继续参阅图9，然后，灰化去除第一光刻胶900以及第二部分1020，第一部分1010的厚度相应的被减薄。
请参阅图9和图10，然后，对金属部402和栅极部400进行第一次蚀刻，去除金属部402以及部分栅极部400，以暴露附加部303和部分栅极绝缘部300。
请参阅图11，然后，对附加部303和栅极绝缘部300进行第二次蚀刻，去除附加部303以及部分栅极绝缘部300。第二次蚀刻为干法蚀刻。
请参阅图12，然后，灰化去除第一部分1010，并对有源部200经栅极绝缘部300露出的部分和第一极板299进行导体化处理，以形成被栅极绝缘部300覆盖的半导体区和未被栅极绝缘部300覆盖的导通区。
B13、在基板、有源部、栅极绝缘部和栅极部上设置层间介质层。
请参阅图12，具体的，在基板100、有源部200、第一极板299、栅极绝缘部300和栅极部400上采用化学气相沉积方式形成层间介质层500，并对层间介质层500进行第三次蚀刻处理，以在层间介质层500上形成具有第一通孔501和第二通孔502。第一通孔501和第二通孔502位于栅极部400的相对两侧，并且，第一通孔501和第二通孔502贯穿层间介质层500以暴露有源部200的导通区。
在一实施例中，在步骤B13之后，还包括：
请参阅图13，在层间介质层500上采用物理气相沉积方式形成设置金属层，并图案化金属层，以形成源极600和漏极700。即采用湿法蚀刻形成源极600和漏极700。源极600和漏极700分别延伸入第一通孔501和第二通孔502中与有源部200的导通区上表面连接。
请参阅图13和图14，然后，在源极600、漏极700和层间介质层500上采用化学气相沉积方式形成钝化层800，并对钝化层800进行图案化处理，形成具有第三通孔801的钝化层800。第三通孔801贯穿钝化层800以暴露漏极700。
请参阅图15，然后，在钝化层800上采用物理气相沉积方式沉积导电层，并对导电层进行图案化处理形成像素电极499。即，采用湿法蚀刻形成像素电极499。第一极板299在基板100上的正投影位于像素电极499在基板100上的正投影中。像素电极499可以复用为存储电容的第二极板与第一极板299构成存储电容。导电层的材料为透明导电材料。
请参阅图16-图24，现有技术中，阵列基板的制备方法包括：在缓冲层上采用一道光罩形成图案化的有源部21；然后，在缓冲层上依次层叠形成栅极绝缘层和栅极，采用一道光罩对栅极以及栅极绝缘层进行图案化处理分别形成栅极部31和栅极绝缘部41，然后，在缓冲层上形成层间介质层和钝化层等。即，现有技术中的阵列基板需要采用两道光罩来形成有源部21、栅极绝缘部31和栅极部41，即现有技术中的阵列基板需要采用多道光罩形成，使得阵列基板的制备工艺复杂化，且生产周期长，进而使得成本升高。
而在本申请中，将有源部200、栅极绝缘部300和栅极部400采用同一道半色调光罩形成，节省了光罩，从而降低了成本。将第一极板299在基板100上的正投影设置为位于像素电极499在基板100上的正投影中，使得像素电极499可以复用为存储电容的第二极板，从而简化了制备工艺，并降低成本；将第一极板299在基板100上的正投影设置为位于像素电极499在基板100上的正投影中，使得像素电极499可以复用为存储电容的第二极板，且，像素电极499由透明材料形成，可以提高阵列基板10的透过率。
在另一实施例中，有源部200、栅极绝缘部300和栅极部400采用同一道非半色调光罩形成，即正常的光罩形成，其源极600和漏极700与有源部200的导通区侧面连接，但不影响阵列基板10的正常工作。
本申请公开了一种阵列基板10及其制备方法和显示面板，阵列基板10的制备方法，包括：提供一基板100；在基板100上依次层叠设置有源层201、栅极401绝缘层301和栅极401，采用一道光罩对有源层201、栅极401绝缘层301和栅极401进行图形化处理，形成有源部200、栅极绝缘部300和栅极部400，有源部200、栅极绝缘部300和栅极部400依次层叠设置；在基板100、有源部200、栅极绝缘部300和栅极部400设置层间介质层500，在本申请中，通过一道光罩形成有源部200、栅极绝缘部300和栅极部400，从而简化了阵列基板10的制备工艺，并降低成本。将第一极板299在基板100上的正投影设置为位于像素电极499在基板100上的正投影中，使得像素电极499可以复用为存储电容的第二极板，且，像素电极499由透明材料形成，可以提高阵列基板10的透过率。
以上对本申请实施例所提供的一种阵列基板及其制备方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。
Claims (10)
1.一种阵列基板的制备方法，其特征在于，包括：
提供一基板；
在所述基板上依次层叠设置有源层、栅极绝缘层和栅极，采用一道光罩对所述有源层、所述栅极绝缘层和所述栅极进行图形化处理，形成有源部、栅极绝缘部和栅极部，所述有源部、所述栅极绝缘部和所述栅极部依次层叠设置；以及
在所述基板、所述有源部、所述栅极绝缘部和所述栅极部上设置层间介质层。
2.根据权利要求1所述的阵列基板的制备方法，其特征在于，所述形成有源部、栅极绝缘部和栅极的步骤包括：
在所述基板上依次层叠设置有源层、栅极绝缘层和栅极，采用一道光罩对所述有源层、所述栅极绝缘层和所述栅极进行图形化处理，所述有源层形成有源部和第一极板，所述栅极绝缘层形成栅极绝缘部和附加部，所述栅极形成金属部和栅极部，所述有源部、所述栅极绝缘部和所述栅极部依次层叠设置，所述第一极板、所述附加部和所述金属部依次层叠设置，所述有源部、所述栅极绝缘部以及所述栅极部与所述第一极板、所述附加部和所述金属部之间具有间隙；以及
去除所述附加部和所述金属部。
3.根据权利要求2所述的阵列基板的制备方法，其特征在于，所述去除所述附加部和所述金属部的步骤包括：
对所述栅极部和所述金属部进行第一次蚀刻，去除所述金属部以及部分所述栅极部，以暴露所述附加部和部分所述栅极绝缘部；以及
对所述附加部和所述栅极绝缘部进行第二次蚀刻，去除所述附加部以及部分所述栅极绝缘部，以暴露所述第一极板和部分所述有源部。
4.根据权利要求3所述的阵列基板的制备方法，其特征在于，在暴露所述第一极板和部分所述有源部之后，还包括：
对所述第一极板和部分所述有源部进行导体化处理，以在所述有源部上形成与所述栅极绝缘部层叠的半导体区和围绕所述半导体区设置的导通区。
5.根据权利要求4所述的阵列基板的制备方法，其特征在于，所述在所述基板、所述有源部、所述栅极绝缘部和所述栅极部上设置层间介质层之后，还包括：
对所述层间介质层进行第三次蚀刻处理，以在所述层间介质层上形成第一通孔和第二通孔，所述第一通孔和所述第二通孔位于所述栅极部的相对两侧，并且，所述第一通孔和所述第二通孔贯穿所述层间介质层以暴露所述有源部的所述导通区。
6.根据权利要求5所述的阵列基板的制备方法，其特征在于，所述在对所述层间介质层进行第三次蚀刻处理的步骤之后，还包括：
在所述层间介质层上形成金属层，并图案化所述金属层，以形成源极和漏极，所述源极延伸入所述第一通孔中与所述有源部连接，所述漏极延伸入所述第二通孔中与所述有源部连接；以及
在所述层间介质层、所述源极和所述漏极上设置钝化层，并对所述钝化层进行第四次蚀刻处理，以在所述钝化层上形成第三通孔，所述第三通孔贯穿所述钝化层并暴露所述漏极。
7.根据权利要求6所述的阵列基板的制备方法，其特征在于，所述在对所述钝化层进行第四次蚀刻处理的步骤之后，还包括：
在所述钝化层上形成导电层，并图案化所述导电层以形成像素电极，所述像素电极延伸入所述第三通孔中与所述漏极连接，所述第一极板在所述基板上的正投影位于所述像素电极在所述基板上的正投影中。
8.根据权利要求1所述的阵列基板的制备方法，其特征在于，所述提供一基板的步骤包括：
提供一衬底，在所述衬底上形成缓冲层。
9.一种阵列基板，其特征在于，包括：
基板；
有源部和第一极板，所述有源部和所述第一极板同层设置于所述基板上，所述第一极板和所述有源部之间具有间隙；
栅极绝缘部，所述栅极绝缘部设置于有源部上；
栅极部，所述栅极部设置于所述栅极绝缘部上；
层间介质层，所述层间介质层覆盖所述基板、所述有源部、所述栅极绝缘部和所述栅极部；以及
像素电极，所述像素电极设置于所述层间介质层上，所述第一极板在所述基板上的正投影位于所述像素电极在所述基板上的正投影中。
10.一种显示面板，其特征在于，所述显示面板包括对置基板、液晶层和如权利要求9所述的阵列基板，所述对置基板与所述阵列基板相对间隔设置，所述液晶层设置在所述对置基板与所述阵列基板之间。
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