WO2016176881A1 - 双栅极tft基板的制作方法及其结构 - Google Patents

双栅极tft基板的制作方法及其结构 Download PDF

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WO2016176881A1
WO2016176881A1 PCT/CN2015/079665 CN2015079665W WO2016176881A1 WO 2016176881 A1 WO2016176881 A1 WO 2016176881A1 CN 2015079665 W CN2015079665 W CN 2015079665W WO 2016176881 A1 WO2016176881 A1 WO 2016176881A1
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insulating layer
layer
gate
drain
source
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PCT/CN2015/079665
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English (en)
French (fr)
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李文辉
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深圳市华星光电技术有限公司
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Priority to US14/770,091 priority Critical patent/US9716119B2/en
Publication of WO2016176881A1 publication Critical patent/WO2016176881A1/zh

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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method and a structure for fabricating a dual-gate TFT substrate.
  • CTR cathode ray tube
  • a common flat panel display device mainly includes a liquid crystal display (LCD) and an active matrix organic light-emitting diode (AMOLED).
  • LCD liquid crystal display
  • AMOLED active matrix organic light-emitting diode
  • a Thin Film Transistor (TFT) can be formed on a glass substrate or a plastic substrate, and is generally used as a switching member and a driving member on a flat panel display device such as an LCD or an AMOLED.
  • Oxide semiconductor TFT technology is currently a popular technology. Oxide semiconductors have high electron mobility and are relatively simple to process and have high compatibility with amorphous silicon processes, and can be applied to various display devices such as LCD and AMOLED. Good development prospects.
  • conventional oxide semiconductor TFTs are generally single-gate structures, which have stability problems including environmental stability, stress bias stability, and mask stability problems.
  • a TFT substrate with double-gate structure is proposed to improve TFT stability and reduce threshold voltage (Vth) drift, as shown in Figure 1.
  • a double-gate TFT substrate includes a substrate 10, a bottom gate 20 stacked on the substrate 10 in this order from the bottom, a first insulating layer 30, an island-shaped oxide semiconductor layer 40, and a second insulating layer 50, The source/drain electrode 60, the third insulating layer 70, the top gate 80, the fourth insulating layer 90, and the pixel electrode 100.
  • the source/drain electrode 60 is in contact with the island-shaped oxide semiconductor layer 40 via a via penetrating through the second insulating layer 50 to form an electrical connection; the pixel electrode 100 is penetrated through the fourth insulating layer 90 and the third insulating layer.
  • the vias of layer 70 are in contact with source/drain electrodes 60 to form an electrical connection.
  • the above-mentioned conventional dual-gate TFT substrate has the bottom gate 20 disposed on the substrate 10, the source/drain electrodes 60 disposed on the second insulating layer 50, and the top gate 80 disposed on the third surface.
  • the source/drain electrodes 60 and the top gate 80 are respectively located in different layers, so that the bottom gate 20, the source/drain electrodes 60, and the top gate 80 are separately formed by a separate mask.
  • Figure In the case of the process the number of masks required is large, the process flow is long, the process is complicated, and the production cost is high.
  • An object of the present invention is to provide a method for fabricating a dual-gate TFT substrate, which can improve the stability of the TFT, reduce the number of masks, shorten the process flow, simplify the process, and reduce the production cost.
  • Another object of the present invention is to provide a dual-gate TFT substrate structure, which has a simple structure, good TFT stability, and is easy to manufacture.
  • the present invention firstly provides a method for fabricating a dual-gate TFT substrate, which firstly fabricates a bottom gate, a first insulating layer, an island-shaped semiconductor layer, and a second insulating layer on a substrate; and then deposits a second metal a layer, the second metal layer is patterned by a mask, and the source, the drain, and the top gate are simultaneously formed; and the third insulating layer and the pixel electrode are sequentially formed, and the method includes the following steps:
  • Step 1 providing a substrate, depositing a first metal layer on the substrate, patterning the first metal layer through a first photomask to form a bottom gate;
  • Step 2 depositing a first insulating layer on the bottom gate and the substrate;
  • Step 3 depositing a semiconductor layer on the first insulating layer, patterning the semiconductor layer through a second mask to form an island-shaped semiconductor layer corresponding to the bottom gate;
  • Step 4 depositing a second insulating layer on the island-shaped semiconductor layer and the first insulating layer, and patterning the second insulating layer through a third mask to form a first through the second insulating layer a via hole and a second via hole to respectively expose both ends of the island-shaped semiconductor layer;
  • Step 5 depositing a second metal layer on the second insulating layer, patterning the second metal layer through a fourth photomask, and simultaneously forming a source, a drain, and a top gate;
  • the source and the drain respectively contact both ends of the island-shaped semiconductor layer via the first and second via holes, and the top gate is located between the source and the drain;
  • the bottom gate, the island-shaped semiconductor layer, the source, the drain, and the top gate constitute a double gate TFT
  • Step 6 depositing a third insulating layer on the source, the drain, the top gate, and the second insulating layer, and patterning the third insulating layer through a fifth mask to form a third through a third via of the insulating layer to expose a portion of the surface of the drain;
  • Step 7 depositing a pixel electrode layer on the third insulating layer, patterning the pixel electrode layer through a sixth mask to form a pixel electrode, and the pixel electrode contacts the drain via a third via hole .
  • the second insulating layer is patterned by the third reticle, and the first insulating layer is also patterned to form the through-second insulating layer and the first insulating layer.
  • the material of the first metal layer and the second metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the first insulating layer and the second insulating layer is silicon nitride, silicon oxide, or a combination of the two, and the material of the third insulating layer is an organic photoresist.
  • the material of the semiconductor layer is an oxide semiconductor, an amorphous silicon semiconductor, or a low temperature polysilicon semiconductor.
  • the pixel electrode is a transparent electrode.
  • the present invention also provides a dual-gate TFT substrate structure, including a substrate, a bottom gate disposed on the substrate, a first insulating layer disposed on the bottom gate, and the substrate, and the bottom gate An island-shaped semiconductor layer disposed on the first insulating layer, a second insulating layer disposed on the island-shaped semiconductor layer and the first insulating layer, a source disposed on the second insulating layer, a drain, a top gate, a third insulating layer disposed on the source, the drain, the top gate, and the second insulating layer, and a pixel electrode disposed on the third insulating layer;
  • the second insulating layer has a first via hole penetrating the second insulating layer and a second via hole
  • the third insulating layer has a third via hole penetrating the third insulating layer
  • the bottom gate, the island-shaped semiconductor layer, the source, the drain, and the top gate constitute a double gate TFT.
  • the second insulating layer and the first insulating layer further have a via hole penetrating the second insulating layer and the first insulating layer, and the top gate contacts the bottom gate via the via hole.
  • the bottom gate, the source, the drain, and the top gate are made of a stack combination of one or more of molybdenum, titanium, aluminum, and copper;
  • the material of the first insulating layer and the second insulating layer is silicon nitride, silicon oxide, or a combination of the two, and the material of the third insulating layer is an organic photoresist;
  • the material of the island-shaped semiconductor layer is an oxide semiconductor, an amorphous silicon semiconductor, or a low-temperature polysilicon semiconductor;
  • the pixel electrode is a transparent electrode.
  • the invention also provides a method for fabricating a double-gate TFT substrate, which firstly forms a bottom gate, a first insulating layer, an island-shaped semiconductor layer and a second insulating layer on a substrate; then deposits a second metal layer through a light The mask is patterned on the second metal layer to form a source, a drain, and a top gate; and a third insulating layer and a pixel electrode are sequentially formed;
  • the specific steps include the following steps:
  • Step 1 providing a substrate, depositing a first metal layer on the substrate, patterning the first metal layer through a first photomask to form a bottom gate;
  • Step 2 depositing a first insulating layer on the bottom gate and the substrate;
  • Step 3 depositing a semiconductor layer on the first insulating layer, patterning the semiconductor layer through a second mask to form an island-shaped semiconductor layer corresponding to the bottom gate;
  • Step 4 depositing a second insulating layer on the island-shaped semiconductor layer and the first insulating layer, and patterning the second insulating layer through a third mask to form a first through the second insulating layer a via hole and a second via hole to respectively expose both ends of the island-shaped semiconductor layer;
  • Step 5 depositing a second metal layer on the second insulating layer, patterning the second metal layer through a fourth photomask, and simultaneously forming a source, a drain, and a top gate;
  • the source and the drain respectively contact both ends of the island-shaped semiconductor layer via the first and second via holes, and the top gate is located between the source and the drain;
  • the bottom gate, the island-shaped semiconductor layer, the source, the drain, and the top gate constitute a double gate TFT
  • Step 6 depositing a third insulating layer on the source, the drain, the top gate, and the second insulating layer, and patterning the third insulating layer through a fifth mask to form a third through a third via of the insulating layer to expose a portion of the surface of the drain;
  • Step 7 depositing a pixel electrode layer on the third insulating layer, patterning the pixel electrode layer through a sixth mask to form a pixel electrode, and the pixel electrode contacts the drain via a third via hole ;
  • the second insulating layer is patterned by the third reticle, and the first insulating layer is also patterned to form a via hole penetrating the second insulating layer and the first insulating layer. a portion of the surface of the bottom gate is exposed; the top gate formed in the step 6 contacts the bottom gate via the via;
  • the material of the first metal layer and the second metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, and copper;
  • the material of the first insulating layer and the second insulating layer is silicon nitride, silicon oxide, or a combination of the two, and the material of the third insulating layer is an organic photoresist;
  • the material of the semiconductor layer is an oxide semiconductor, an amorphous silicon semiconductor, or a low temperature polysilicon semiconductor;
  • the pixel electrode is a transparent electrode.
  • the present invention provides a method for fabricating a dual-gate TFT substrate, which improves the stability of the TFT by fabricating a bottom gate and a top gate; performing a patterning process through a mask to simultaneously form a source
  • the pole, the drain, and the top gate reduce the number of masks, shorten the process flow, simplify the process, and reduce production costs.
  • Double gate TFT substrate junction provided by the invention By setting the bottom gate and the top gate to make the stability of the TFT better, the dual gate TFT substrate is simple in structure by disposing the source, the drain, and the top gate together on the second insulating layer. Easy to make.
  • FIG. 1 is a schematic structural view of a conventional dual-gate TFT substrate
  • FIG. 2 is a flow chart of a method for fabricating a dual gate TFT substrate of the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating a dual-gate TFT substrate according to the present invention
  • step 3 is a schematic diagram of step 3 of a method for fabricating a dual-gate TFT substrate according to the present invention
  • step 4 is a schematic diagram of step 4 of a method for fabricating a dual-gate TFT substrate according to the present invention
  • step 5 is a schematic diagram of step 5 of a method for fabricating a dual-gate TFT substrate according to the present invention.
  • step 6 is a schematic diagram of step 6 of a method for fabricating a dual-gate TFT substrate according to the present invention.
  • FIG. 9 is a schematic view showing the step 7 of the method for fabricating the dual-gate TFT substrate of the present invention and a schematic diagram of the structure of the double-gate TFT substrate of the present invention.
  • the present invention first provides a method for fabricating a dual-gate TFT substrate, including the following steps:
  • Step 1 as shown in FIG. 3, a substrate 1 is provided, a first metal layer is deposited on the substrate 1, and the first metal layer is patterned by a first mask to form a bottom gate 2.
  • the step 1 deposits the first metal layer by Physical Vapor Deposition (PVD).
  • the material of the first metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the first metal layer is patterned by a photolithography process, including a photo-resistance, exposure, development, wet etching, and photoresist removal process.
  • Step 2 As shown in FIG. 4, a first insulating layer 3 is deposited on the bottom gate 2 and the substrate 1.
  • the first insulating layer 3 is deposited by chemical vapor deposition (CVD).
  • the material of the first insulating layer 3 is silicon nitride, silicon oxide, or a combination of the two.
  • Step 3 depositing a semiconductor layer on the first insulating layer 3, and patterning the semiconductor layer through a second mask to form an island shape corresponding to the bottom gate 2 Semiconductor layer 4.
  • the step 3 deposits the semiconductor layer by physical vapor deposition.
  • the material of the semiconductor layer is an oxide semiconductor (such as an Indium Gallium Zinc Oxide (IGZO) semiconductor), an amorphous silicon semiconductor, or a low temperature polysilicon semiconductor.
  • IGZO Indium Gallium Zinc Oxide
  • step 3 the semiconductor layer is patterned by a photolithography process, including a photoresist process such as photoresist, exposure, development, wet etching, and photoresist removal.
  • a photoresist process such as photoresist, exposure, development, wet etching, and photoresist removal.
  • Step 4 depositing a second insulating layer 5 on the island-shaped semiconductor layer 4 and the first insulating layer 3, and patterning the second insulating layer 5 through a third mask.
  • the first via 51 and the second via 52 penetrating the second insulating layer 5 are formed to expose both ends of the island-shaped semiconductor layer 4, respectively.
  • the step 4 deposits the second insulating layer 5 by chemical vapor deposition.
  • the material of the second insulating layer 5 is silicon nitride, silicon oxide, or a combination of the two.
  • the second insulating layer 5 is patterned by a photolithography process, including a photoresist process such as photoresist, exposure, development, dry etching, and photoresist removal.
  • a photoresist process such as photoresist, exposure, development, dry etching, and photoresist removal.
  • Step 5 depositing a second metal layer on the second insulating layer 5, patterning the second metal layer through a fourth mask, and simultaneously forming a source 61 and a drain 62. And the top gate 63.
  • the source 61 and the drain 62 contact the two ends of the island-shaped semiconductor layer 4 via the first and second vias 51 and 52, respectively, so that the source 61 and the drain 62 respectively form an electric charge with the island-shaped semiconductor layer 4.
  • the top gate 63 is located between the source 61 and the drain 62.
  • the bottom gate 2, the island-shaped semiconductor layer 4, the source 61, the drain 62, and the top gate 63 constitute a double gate TFT T.
  • the step 5 deposits the second metal layer by physical vapor deposition.
  • the material of the second metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the second metal layer is patterned by a photolithography process, including a photoresist process such as photoresist, exposure, development, wet etching, and photoresist removal.
  • a photoresist process such as photoresist, exposure, development, wet etching, and photoresist removal.
  • Step 6 as shown in FIG. 8, a third insulating layer 7 is deposited on the source 61, the drain 62, the top gate 63, and the second insulating layer 5, and the third insulating layer is passed through the fifth mask.
  • Layer 7 pattern The third via 71 is formed through the third insulating layer 7 to expose a portion of the surface of the drain 62.
  • the material of the third insulating layer 7 is an organic photoresist, which functions as insulation and planarization.
  • Step 7 depositing a pixel electrode layer on the third insulating layer 7, and patterning the pixel electrode layer through a sixth mask to form a pixel electrode 8, and the pixel electrode 8 is via the pixel electrode 8
  • the third via 71 contacts the drain 62 such that the pixel electrode 8 and the drain 62 are electrically connected.
  • the pixel electrode 8 is a transparent electrode, such as an Indium Tin Oxide (ITO) electrode, an Indium Zinc Oxide (IZO) electrode, or the like.
  • ITO Indium Tin Oxide
  • IZO Indium Zinc Oxide
  • the TFT substrate fabricated through the above steps 1 to 7 does not form an electrical connection between the top gate 63 and the bottom gate 2, but the step 4 may also pass through the third light.
  • the masking process is performed on the second insulating layer 5, and the first insulating layer 3 is also patterned to form a via hole penetrating the second insulating layer 5 and the first insulating layer 3 to expose the bottom gate. a portion of the surface of the pole 2; the top gate 63 formed in the step 6 contacts the bottom gate 2 via the via, such that an electrical connection is formed between the top gate 63 and the bottom gate 2.
  • the bottom gate 2, the first insulating layer 3, the island-shaped semiconductor layer 4, and the second insulating layer 5 are sequentially formed on the substrate 1, and then the second metal layer is deposited.
  • the second metal layer is patterned by a photomask to simultaneously form the source electrode 61, the drain electrode 62, and the top gate electrode 63; and the third insulating layer 7 and the pixel electrode 8 are sequentially formed.
  • the bottom gate 2 and the top gate 63 can improve the stability of the TFT; the top gate 63 and the source 61 and the drain 62 are simultaneously formed by patterning through a photomask, which can reduce the number of masks. Shorten process flow, simplify process and reduce production costs.
  • the present invention further provides a dual-gate TFT substrate structure prepared by the above manufacturing method, comprising a substrate 1 , a bottom gate 2 disposed on the substrate 1 , and a bottom gate 2 . And a first insulating layer 3 on the substrate 1 , an island-shaped semiconductor layer 4 disposed on the first insulating layer 3 above the bottom gate 2 , and the island-shaped semiconductor layer 4 and the first insulating layer a second insulating layer 5 on the layer 3, a source 61, a drain 62, and a top gate 63 disposed on the second insulating layer 5, and the source 61, the drain 62, and the top gate. 63.
  • the third insulating layer 7 on the second insulating layer 5 and the pixel electrode 8 disposed on the third insulating layer 7.
  • the second insulating layer 5 has a first via 51 and a second via 52 extending through the second insulating layer 5, and the third insulating layer 7 has a third via 71 extending through the third insulating layer 7.
  • the source 61 and the drain 62 are in contact with both ends of the island-shaped semiconductor layer 4 via the first and second vias 51 and 52, respectively, and the top gate 63 is located between the source 61 and the drain 62;
  • the pixel electrode 8 is via the third The via 71 contacts the drain 62.
  • the bottom gate 2, the island-shaped semiconductor layer 4, the source 61, the drain 62, and the top gate 63 constitute a double gate TFT T.
  • the top gate 63 and the bottom gate 2 may not be electrically connected or may be electrically connected.
  • the second insulating layer 5 and the first insulating layer 3 further have a second insulating layer 5 and a first insulating layer 3 extending therethrough. a via hole, the top gate 63 contacting the bottom gate 2 via the via.
  • the dual-gate TFT substrate structure of the present invention has better stability of the TFT by providing the bottom gate 2 and the top gate 63, and the source 61, the drain 62, and the top gate 63 are collectively disposed in the second
  • the structure of the double-gate TFT substrate is simple on the insulating layer 5, and the source electrode 61, the drain electrode 62, and the top gate electrode 63 are simultaneously patterned by one mask, and the process flow is shortened and easy to manufacture.
  • the material of the bottom gate 2, the source 61, the drain 62, and the top gate 63 is a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the first insulating layer 3 and the second insulating layer 5 is silicon nitride, silicon oxide, or a combination of the two; the material of the third insulating layer 7 is an organic photoresist, which is insulated and planarized. effect.
  • the material of the island-shaped semiconductor layer 4 is an oxide semiconductor (such as IGZO), an amorphous silicon semiconductor, or a low-temperature polysilicon semiconductor.
  • the pixel electrode 8 is a transparent electrode such as ITO, IZO, or the like.
  • the method for fabricating the dual-gate TFT substrate of the present invention improves the stability of the TFT by fabricating the bottom gate and the top gate; performing a patterning process through a mask to simultaneously form the source and the drain. And the top gate can reduce the number of masks, shorten the process flow, simplify the process, and reduce the production cost.
  • the dual-gate TFT substrate structure of the present invention has better stability of the TFT by providing a bottom gate and a top gate, and the source, the drain, and the top gate are collectively disposed on the second insulating layer.
  • the double-gate TFT substrate has a simple structure and is easy to manufacture.

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Abstract

提供一种双栅极TFT基板的制作方法及其结构。该双栅极TFT基板的制作方法，先在基板（1）上依次制作底栅极（2）、第一绝缘层（3）、岛状半导体层（4）、第二绝缘层（5）；然后沉积第二金属层，通过一道光罩对第二金属层进行图案化处理，同时形成源极（61）、漏极（62）、及顶栅极（63）；再依次制作第三绝缘层（7）、及像素电极（8），能够提高TFT的稳定性，减少光罩数量，缩短工序流程，简化制程，降低生产成本。该双栅极TFT基板结构，其结构简单，TFT稳定性较好，易于制作。

Description

双栅极TFT基板的制作方法及其结构 技术领域
本发明涉及显示技术领域，尤其涉及一种双栅极TFT基板的制作方法及其结构。
背景技术
在显示技术领域，平板显示装置已经逐步取代阴极射线管(Cathode Ray Tube，CRT)显示器。平板显示装置因具有高画质、省电、机身薄、无辐射等众多优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
目前常见的平板显示装置主要包括：液晶显示装置(Liquid Crystal Display，LCD)和有源矩阵驱动式有机电致发光显示装置(Active Matrix Organic Light-Emitting Diode，AMOLED)。薄膜晶体管(Thin Film Transistor，TFT)可形成在玻璃基板或塑料基板上，通常作为开关部件和驱动部件用在诸如LCD、AMOLED等平板显示装置上。
氧化物半导体TFT技术是当前的热门技术。氧化物半导体由于具有较高的电子迁移率，而且相对于低温多晶半导体，氧化物半导体制程简单，与非晶硅制程相容性较高，可应用于LCD、AMOLED等多种显示装置，具有良好的发展前景。然而，传统的氧化物半导体TFT一般为单栅极结构，存在稳定性问题，包括环境稳定性、应力偏压稳定性、及光罩稳定性问题。为解决单栅极氧化物半导体TFT存在的稳定性问题，提出了一种双栅极结构的TFT基板，用于提高TFT稳定性，减少阈值电压(Vth)漂移，如图1所示，现有的一种双栅极TFT基板包括：基板10、自下往上依次层叠设置于基板10上的底栅极20、第一绝缘层30、岛状氧化物半导体层40、第二绝缘层50、源/漏电极60、第三绝缘层70、顶栅极80、第四绝缘层90、及像素电极100。其中，所述源/漏电极60经由贯穿第二绝缘层50的过孔与岛状氧化物半导体层40接触，形成电性连接；所述像素电极100经由贯穿第四绝缘层90和第三绝缘层70的过孔与源/漏电极60接触，形成电性连接。
特别需要指出的是，上述现有的双栅极TFT基板将底栅极20设置于基板10上，将源/漏电极60设置于第二绝缘层50上，将顶栅极80设置于第三绝缘层70上，源/漏电极60与顶栅极80分别位于不同的层别，从而制作底栅极20、源/漏电极60、及顶栅极80时各需要一道单独的光罩来进行图 案化制程，所需的光罩数量较多，工序流程较长，制程较复杂，生产成本较高。
发明内容
本发明的目的在于提供一种双栅极TFT基板的制作方法，能够提高TFT的稳定性，减少光罩数量，缩短工序流程，简化制程，降低生产成本。
本发明的目的还在于提供一种双栅极TFT基板结构，其结构简单，TFT稳定性较好，易于制作。
为实现上述目的，本发明首先提供一种双栅极TFT基板的制作方法，先在基板上依次制作底栅极、第一绝缘层、岛状半导体层、第二绝缘层；然后沉积第二金属层，通过一道光罩对第二金属层进行图案化处理，同时形成源极、漏极、及顶栅极；再依次制作第三绝缘层、及像素电极，具体包括如下步骤：
步骤1、提供一基板，在该基板上沉积第一金属层，通过第一道光罩对所述第一金属层进行图案化处理，形成底栅极；
步骤2、在所述底栅极、及基板上沉积第一绝缘层；
步骤3、在所述第一绝缘层上沉积半导体层，通过第二道光罩对所述半导体层进行图案化处理，形成对应位于所述底栅极上方的岛状半导体层；
步骤4、在所述岛状半导体层、及第一绝缘层上沉积第二绝缘层，通过第三道光罩对所述第二绝缘层进行图案化处理，形成贯穿该第二绝缘层的第一过孔、与第二过孔，以分别暴露出所述岛状半导体层的两端；
步骤5、在所述第二绝缘层上沉积第二金属层，通过第四道光罩对所述第二金属层进行图案化处理，同时形成源极、漏极、及顶栅极；
所述源极、漏极分别经由第一、第二过孔接触岛状半导体层的两端，所述顶栅极位于源极与漏极之间；
所述底栅极、岛状半导体层、源极、漏极、及顶栅极构成双栅极TFT；
步骤6、在所述源极、漏极、顶栅极、及第二绝缘层上沉积第三绝缘层，通过第五道光罩对所述第三绝缘层进行图案化处理，形成贯穿该第三绝缘层的第三过孔，以暴露出所述漏极的部分表面；
步骤7、在所述第三绝缘层上沉积像素电极层，通过第六道光罩对所述像素电极层进行图案化处理，形成像素电极，所述像素电极经由第三过孔接触所述漏极。
所述步骤4通过第三道光罩对所述第二绝缘层进行图案化处理的同时，也对第一绝缘层进行图案化处理，形成贯穿第二绝缘层与第一绝缘层 的过孔，以暴露出底栅极的部分表面；所述步骤6中形成的顶栅极经由所述过孔接触所述底栅极。
所述第一金属层与第二金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
所述第一绝缘层与第二绝缘层的材料为氮化硅、氧化硅、或二者的组合，所述第三绝缘层的材料为有机光阻。
所述半导体层的材料为氧化物半导体、非晶硅半导体、或低温多晶硅半导体。
所述像素电极为透明电极。
本发明还提供一种双栅极TFT基板结构，包括基板、设于所述基板上的底栅极、设于所述底栅极、及基板上的第一绝缘层、于所述底栅极上方设于所述第一绝缘层上的岛状半导体层、设于所述岛状半导体层、及第一绝缘层上的第二绝缘层、设于所述第二绝缘层上的源极、漏极、及顶栅极、设于所述源极、漏极、顶栅极、及第二绝缘层上的第三绝缘层、及设于所述第三绝缘层上的像素电极；
所述第二绝缘层具有贯穿该第二绝缘层的第一过孔、与第二过孔，所述第三绝缘层具有贯穿该第三绝缘层的第三过孔；所述源极、漏极分别经由第一、第二过孔接触岛状半导体层的两端，所述顶栅极位于源极与漏极之间；所述像素电极经由第三过孔接触所述漏极；
所述底栅极、岛状半导体层、源极、漏极、及顶栅极构成双栅极TFT。
所述第二绝缘层与第一绝缘层还具有贯穿该第二绝缘层与第一绝缘层的过孔，所述顶栅极经由所述过孔接触所述底栅极。
所述底栅极、源极、漏极、及顶栅极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；
所述第一绝缘层与第二绝缘层的材料为氮化硅、氧化硅、或二者的组合，所述第三绝缘层的材料为有机光阻；
所述岛状半导体层的材料为氧化物半导体、非晶硅半导体、或低温多晶硅半导体；
所述像素电极为透明电极。
本发明还提供一种双栅极TFT基板的制作方法，先在基板上依次制作底栅极、第一绝缘层、岛状半导体层、第二绝缘层；然后沉积第二金属层，通过一道光罩对第二金属层进行图案化处理，同时形成源极、漏极、及顶栅极；再依次制作第三绝缘层、及像素电极；
其中，具体包括如下步骤：
步骤1、提供一基板，在该基板上沉积第一金属层，通过第一道光罩对所述第一金属层进行图案化处理，形成底栅极；
步骤2、在所述底栅极、及基板上沉积第一绝缘层；
步骤3、在所述第一绝缘层上沉积半导体层，通过第二道光罩对所述半导体层进行图案化处理，形成对应位于所述底栅极上方的岛状半导体层；
步骤4、在所述岛状半导体层、及第一绝缘层上沉积第二绝缘层，通过第三道光罩对所述第二绝缘层进行图案化处理，形成贯穿该第二绝缘层的第一过孔、与第二过孔，以分别暴露出所述岛状半导体层的两端；
步骤5、在所述第二绝缘层上沉积第二金属层，通过第四道光罩对所述第二金属层进行图案化处理，同时形成源极、漏极、及顶栅极；
所述源极、漏极分别经由第一、第二过孔接触岛状半导体层的两端，所述顶栅极位于源极与漏极之间；
所述底栅极、岛状半导体层、源极、漏极、及顶栅极构成双栅极TFT；
步骤6、在所述源极、漏极、顶栅极、及第二绝缘层上沉积第三绝缘层，通过第五道光罩对所述第三绝缘层进行图案化处理，形成贯穿该第三绝缘层的第三过孔，以暴露出所述漏极的部分表面；
步骤7、在所述第三绝缘层上沉积像素电极层，通过第六道光罩对所述像素电极层进行图案化处理，形成像素电极，所述像素电极经由第三过孔接触所述漏极；
其中，所述步骤4通过第三道光罩对所述第二绝缘层进行图案化处理的同时，也对第一绝缘层进行图案化处理，形成贯穿第二绝缘层与第一绝缘层的过孔，以暴露出底栅极的部分表面；所述步骤6中形成的顶栅极经由所述过孔接触所述底栅极；
其中，所述第一金属层与第二金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；
其中，所述第一绝缘层与第二绝缘层的材料为氮化硅、氧化硅、或二者的组合，所述第三绝缘层的材料为有机光阻；
其中，所述半导体层的材料为氧化物半导体、非晶硅半导体、或低温多晶硅半导体；
其中，所述像素电极为透明电极。
本发明的有益效果：本发明提供的一种双栅极TFT基板的制作方法，通过制作底栅极、及顶栅极提高TFT的稳定性；通过一道光罩进行一次图案化处理，同时形成源极、漏极、及顶栅极，能够减少光罩数量，缩短工序流程，简化制程，降低生产成本。本发明提供的一种双栅极TFT基板结 构，通过设置底栅极、及顶栅极使得TFT的稳定性较好，通过将源极、漏极、及顶栅极共同设置于第二绝缘层上使得该双栅极TFT基板结构简单，易于制作。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1现有的一种双栅极TFT基板的结构示意图；
图2为本发明双栅极TFT基板的制作方法的流程图；
图3为本发明双栅极TFT基板的制作方法的步骤1的示意图；
图4为本发明双栅极TFT基板的制作方法的步骤2的示意图；
图5为本发明双栅极TFT基板的制作方法的步骤3的示意图；
图6为本发明双栅极TFT基板的制作方法的步骤4的示意图；
图7为本发明双栅极TFT基板的制作方法的步骤5的示意图；
图8为本发明双栅极TFT基板的制作方法的步骤6的示意图；
图9为本发明双栅极TFT基板的制作方法的步骤7的示意图暨本发明双栅极TFT基板结构的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明首先提供一种双栅极TFT基板的制作方法，包括如下步骤：
步骤1、如图3所示，提供一基板1，在该基板1上沉积第一金属层，通过第一道光罩对所述第一金属层进行图案化处理，形成底栅极2。
具体地，该步骤1采用物理气相沉积法(Physical Vapor Deposition，PVD)沉积所述第一金属层。所述第一金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
该步骤1采用光刻制程对所述第一金属层进行图案化处理，包括了涂光阻、曝光、显影、湿蚀刻、及去光阻等制程工序。
步骤2、如图4所示，在所述底栅极2、及基板1上沉积第一绝缘层3。
具体地，该步骤2采用化学气相沉积法(Chemical Vapor Deposition，CVD)沉积所述第一绝缘层3。所述第一绝缘层3的材料为氮化硅、氧化硅、或二者的组合。
步骤3、如图5所示，在所述第一绝缘层3上沉积半导体层，通过第二道光罩对所述半导体层进行图案化处理，形成对应位于所述底栅极2上方的岛状半导体层4。
具体地，该步骤3采用物理气相沉积法沉积所述半导体层。所述半导体层的材料为氧化物半导体(如铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)半导体)、非晶硅半导体、或低温多晶硅半导体。
该步骤3采用光刻制程对所述半导体层进行图案化处理，包括了涂光阻、曝光、显影、湿蚀刻、及去光阻等制程工序。
步骤4、如图6所示，在所述岛状半导体层4、及第一绝缘层3上沉积第二绝缘层5，通过第三道光罩对所述第二绝缘层5进行图案化处理，形成贯穿该第二绝缘层5的第一过孔51、与第二过孔52，以分别暴露出所述岛状半导体层4的两端。
具体地，该步骤4采用化学气相沉积法沉积所述第二绝缘层5。所述第二绝缘层5的材料为氮化硅、氧化硅、或二者的组合。
该步骤4采用光刻制程对所述第二绝缘层5进行图案化处理，包括了涂光阻、曝光、显影、干蚀刻、及去光阻等制程工序。
步骤5、如图7所示，在所述第二绝缘层5上沉积第二金属层，通过第四道光罩对所述第二金属层进行图案化处理，同时形成源极61、漏极62、及顶栅极63。
所述源极61、漏极62分别经由第一、第二过孔51、52接触岛状半导体层4的两端，使得所述源极61、漏极62分别与岛状半导体层4形成电性连接；所述顶栅极63位于源极61与漏极62之间。
所述底栅极2、岛状半导体层4、源极61、漏极62、及顶栅极63构成双栅极TFT T。
具体的，该步骤5采用物理气相沉积法沉积所述第二金属层。所述第二金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
该步骤5采用光刻制程对所述第二金属层进行图案化处理，包括了涂光阻、曝光、显影、湿蚀刻、及去光阻等制程工序。
步骤6、如图8所示，在所述源极61、漏极62、顶栅极63、及第二绝缘层5上沉积第三绝缘层7，通过第五道光罩对所述第三绝缘层7进行图案 化处理，形成贯穿该第三绝缘层7的第三过孔71，以暴露出所述漏极62的部分表面。
具体地，所述第三绝缘层7的材料为有机光阻，起到绝缘及平坦化的作用。
步骤7、如图9所示，在所述第三绝缘层7上沉积像素电极层，通过第六道光罩对所述像素电极层进行图案化处理，形成像素电极8，所述像素电极8经由第三过孔71接触所述漏极62，使得所述像素电极8与漏极62形成电性连接。
具体地，所述像素电极8为透明电极，如氧化铟锡(Indium Tin Oxide，ITO)电极、氧化铟锌(Indium Zinc Oxide，IZO)电极等。
值得一提的是，经上述步骤1至步骤7制作出的TFT基板，其顶栅极63与底栅极2之间并不形成电性连接，但所述步骤4也可以在通过第三道光罩对所述第二绝缘层5进行图案化处理的同时，也对第一绝缘层3进行图案化处理，形成贯穿第二绝缘层5与第一绝缘层3的过孔，以暴露出底栅极2的部分表面；所述步骤6中形成的顶栅极63经由所述过孔接触所述底栅极2，使得所述顶栅极63与底栅极2之间形成电性连接。
本发明提供的双栅极TFT基板的制作方法，先在基板1上依次制作底栅极2、第一绝缘层3、岛状半导体层4、第二绝缘层5；然后沉积第二金属层，通过一道光罩对第二金属层进行图案化处理，同时形成源极61、漏极62、及顶栅极63；再依次制作第三绝缘层7、及像素电极8。所述底栅极2与顶栅极63能够提高TFT的稳定性；所述顶栅极63与源极61、漏极62通过一道光罩进行一次图案化处理同时形成，能够减少光罩数量，缩短工序流程，简化制程，降低生产成本。
请参阅图9，本发明还提供一种由上述制作方法制备的双栅极TFT基板结构，包括基板1、设于所述基板1上的底栅极2、设于所述底栅极2、及基板1上的第一绝缘层3、于所述底栅极2上方设于所述第一绝缘层3上的岛状半导体层4、设于所述岛状半导体层4、及第一绝缘层3上的第二绝缘层5、设于所述第二绝缘层5上的源极61、漏极62、及顶栅极63、设于所述源极61、漏极62、顶栅极63、及第二绝缘层5上的第三绝缘层7、及设于所述第三绝缘层7上的像素电极8。
所述第二绝缘层5具有贯穿该第二绝缘层5的第一过孔51、与第二过孔52，所述第三绝缘层7具有贯穿该第三绝缘层7的第三过孔71；所述源极61、漏极62分别经由第一、第二过孔51、52接触岛状半导体层4的两端，所述顶栅极63位于源极61与漏极62之间；所述像素电极8经由第三 过孔71接触所述漏极62。
所述底栅极2、岛状半导体层4、源极61、漏极62、及顶栅极63构成双栅极TFT T。
值得一提的是，所述顶栅极63与底栅极2之间可以不形成电性连接，也可以形成电性连接。在所述顶栅极63与底栅极2之间形成电性连接的情况下，所述第二绝缘层5与第一绝缘层3还具有贯穿该第二绝缘层5与第一绝缘层3的过孔，所述顶栅极63经由所述过孔接触所述底栅极2。
本发明的双栅极TFT基板结构，通过设置底栅极2、及顶栅极63使得TFT的稳定性较好，通过将源极61、漏极62、及顶栅极63共同设置于第二绝缘层5上使得该双栅极TFT基板结构简单，且源极61、漏极62、及顶栅极63通过一道光罩进行一次图案化处理同时形成，工序流程缩短，易于制作。
具体地，所述底栅极2、源极61、漏极62、及顶栅极63的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
所述第一绝缘层3与第二绝缘层5的材料为氮化硅、氧化硅、或二者的组合；所述第三绝缘层7的材料为有机光阻，起到绝缘及平坦化的作用。
所述岛状半导体层4的材料为氧化物半导体(如IGZO)、非晶硅半导体、或低温多晶硅半导体。
所述像素电极8为透明电极，如ITO、IZO等。
综上所述，本发明的双栅极TFT基板的制作方法，通过制作底栅极、及顶栅极提高TFT的稳定性；通过一道光罩进行一次图案化处理，同时形成源极、漏极、及顶栅极，能够减少光罩数量，缩短工序流程，简化制程，降低生产成本。本发明的双栅极TFT基板结构，通过设置底栅极、及顶栅极使得TFT的稳定性较好，通过将源极、漏极、及顶栅极共同设置于第二绝缘层上使得该双栅极TFT基板结构简单，易于制作。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (11)

  1. 一种双栅极TFT基板的制作方法，先在基板上依次制作底栅极、第一绝缘层、岛状半导体层、第二绝缘层；然后沉积第二金属层，通过一道光罩对第二金属层进行图案化处理，同时形成源极、漏极、及顶栅极；再依次制作第三绝缘层、及像素电极。
  2. 如权利要求1所述的双栅极TFT基板的制作方法，其中，具体包括如下步骤：
    步骤1、提供一基板，在该基板上沉积第一金属层，通过第一道光罩对所述第一金属层进行图案化处理，形成底栅极；
    步骤2、在所述底栅极、及基板上沉积第一绝缘层；
    步骤3、在所述第一绝缘层上沉积半导体层，通过第二道光罩对所述半导体层进行图案化处理，形成对应位于所述底栅极上方的岛状半导体层；
    步骤4、在所述岛状半导体层、及第一绝缘层上沉积第二绝缘层，通过第三道光罩对所述第二绝缘层进行图案化处理，形成贯穿该第二绝缘层的第一过孔、与第二过孔，以分别暴露出所述岛状半导体层的两端；
    步骤5、在所述第二绝缘层上沉积第二金属层，通过第四道光罩对所述第二金属层进行图案化处理，同时形成源极、漏极、及顶栅极；
    所述源极、漏极分别经由第一、第二过孔接触岛状半导体层的两端，所述顶栅极位于源极与漏极之间；
    所述底栅极、岛状半导体层、源极、漏极、及顶栅极构成双栅极TFT；
    步骤6、在所述源极、漏极、顶栅极、及第二绝缘层上沉积第三绝缘层，通过第五道光罩对所述第三绝缘层进行图案化处理，形成贯穿该第三绝缘层的第三过孔，以暴露出所述漏极的部分表面；
    步骤7、在所述第三绝缘层上沉积像素电极层，通过第六道光罩对所述像素电极层进行图案化处理，形成像素电极，所述像素电极经由第三过孔接触所述漏极。
  3. 如权利要求2所述的双栅极TFT基板的制作方法，其中，所述步骤4通过第三道光罩对所述第二绝缘层进行图案化处理的同时，也对第一绝缘层进行图案化处理，形成贯穿第二绝缘层与第一绝缘层的过孔，以暴露出底栅极的部分表面；所述步骤6中形成的顶栅极经由所述过孔接触所述底栅极。
  4. 如权利要求2所述的双栅极TFT基板的制作方法，其中，所述第一 金属层与第二金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
  5. 如权利要求2所述的双栅极TFT基板的制作方法，其中，所述第一绝缘层与第二绝缘层的材料为氮化硅、氧化硅、或二者的组合，所述第三绝缘层的材料为有机光阻。
  6. 如权利要求2所述的双栅极TFT基板的制作方法，其中，所述半导体层的材料为氧化物半导体、非晶硅半导体、或低温多晶硅半导体。
  7. 如权利要求2所述的双栅极TFT基板的制作方法，其中，所述像素电极为透明电极。
  8. 一种双栅极TFT基板结构，包括基板、设于所述基板上的底栅极、设于所述底栅极、及基板上的第一绝缘层、于所述底栅极上方设于所述第一绝缘层上的岛状半导体层、设于所述岛状半导体层、及第一绝缘层上的第二绝缘层、设于所述第二绝缘层上的源极、漏极、及顶栅极、设于所述源极、漏极、顶栅极、及第二绝缘层上的第三绝缘层、及设于所述第三绝缘层上的像素电极；
    所述第二绝缘层具有贯穿该第二绝缘层的第一过孔、与第二过孔，所述第三绝缘层具有贯穿该第三绝缘层的第三过孔；所述源极、漏极分别经由第一、第二过孔接触岛状半导体层的两端，所述顶栅极位于源极与漏极之间；所述像素电极经由第三过孔接触所述漏极；
    所述底栅极、岛状半导体层、源极、漏极、及顶栅极构成双栅极TFT。
  9. 如权利要求8所述的双栅极TFT基板结构，其中，所述第二绝缘层与第一绝缘层还具有贯穿该第二绝缘层与第一绝缘层的过孔，所述顶栅极经由所述过孔接触所述底栅极。
  10. 如权利要求8所述的双栅极TFT基板结构，其中，所述底栅极、源极、漏极、及顶栅极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；
    所述第一绝缘层与第二绝缘层的材料为氮化硅、氧化硅、或二者的组合，所述第三绝缘层的材料为有机光阻；
    所述岛状半导体层的材料为氧化物半导体、非晶硅半导体、或低温多晶硅半导体；
    所述像素电极为透明电极。
  11. 一种双栅极TFT基板的制作方法，先在基板上依次制作底栅极、第一绝缘层、岛状半导体层、第二绝缘层；然后沉积第二金属层，通过一道光罩对第二金属层进行图案化处理，同时形成源极、漏极、及顶栅极；再依次制作第三绝缘层、及像素电极；
    其中，具体包括如下步骤：
    步骤1、提供一基板，在该基板上沉积第一金属层，通过第一道光罩对所述第一金属层进行图案化处理，形成底栅极；
    步骤2、在所述底栅极、及基板上沉积第一绝缘层；
    步骤3、在所述第一绝缘层上沉积半导体层，通过第二道光罩对所述半导体层进行图案化处理，形成对应位于所述底栅极上方的岛状半导体层；
    步骤4、在所述岛状半导体层、及第一绝缘层上沉积第二绝缘层，通过第三道光罩对所述第二绝缘层进行图案化处理，形成贯穿该第二绝缘层的第一过孔、与第二过孔，以分别暴露出所述岛状半导体层的两端；
    步骤5、在所述第二绝缘层上沉积第二金属层，通过第四道光罩对所述第二金属层进行图案化处理，同时形成源极、漏极、及顶栅极；
    所述源极、漏极分别经由第一、第二过孔接触岛状半导体层的两端，所述顶栅极位于源极与漏极之间；
    所述底栅极、岛状半导体层、源极、漏极、及顶栅极构成双栅极TFT；
    步骤6、在所述源极、漏极、顶栅极、及第二绝缘层上沉积第三绝缘层，通过第五道光罩对所述第三绝缘层进行图案化处理，形成贯穿该第三绝缘层的第三过孔，以暴露出所述漏极的部分表面；
    步骤7、在所述第三绝缘层上沉积像素电极层，通过第六道光罩对所述像素电极层进行图案化处理，形成像素电极，所述像素电极经由第三过孔接触所述漏极；
    其中，所述步骤4通过第三道光罩对所述第二绝缘层进行图案化处理的同时，也对第一绝缘层进行图案化处理，形成贯穿第二绝缘层与第一绝缘层的过孔，以暴露出底栅极的部分表面；所述步骤6中形成的顶栅极经由所述过孔接触所述底栅极；
    其中，所述第一金属层与第二金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；
    其中，所述第一绝缘层与第二绝缘层的材料为氮化硅、氧化硅、或二者的组合，所述第三绝缘层的材料为有机光阻；
    其中，所述半导体层的材料为氧化物半导体、非晶硅半导体、或低温多晶硅半导体；
    其中，所述像素电极为透明电极。
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