CN105225975B - 封装结构及其制法 - Google Patents

封装结构及其制法 Download PDF

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Publication number
CN105225975B
CN105225975B CN201410247337.2A CN201410247337A CN105225975B CN 105225975 B CN105225975 B CN 105225975B CN 201410247337 A CN201410247337 A CN 201410247337A CN 105225975 B CN105225975 B CN 105225975B
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China
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convex block
substrate
encapsulating structure
layer
conductive column
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CN105225975A (zh
Inventor
萧惟中
林俊贤
白裕呈
孙铭成
邱士超
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种封装结构及其制法，该封装结构包括：具有相对的顶面及外露有多个第一连接垫的底面的基板；多个嵌埋于该基板中且与该第一连接垫电性连接的导电柱，该导电柱的端面并外露于该基板的顶面；多个形成于该导电柱的端面上的第一凸块；多个形成于该基板的顶面上的第二凸块，且该第二凸块的高度大于该第一凸块的高度；以及设置于该基板的顶面上的第一电子元件，该第一电子元件与该第一凸块电性连接，藉以在不改变现有机台的情况下，使后续设置的电子元件不受到限制。

Description

封装结构及其制法
技术领域
本发明涉及一种封装结构及其制法，尤指一种能具有凸块的封装结构及其制法。
背景技术
随着电子产品朝多功能、高电性及高速运作的方向发展，半导体封装技术的演进已开发出不同的封装型态，例如多晶片模组(Multi Chip Module，MCM)，多晶片模组能整合多个晶片的半导体装置(Semiconductor device)，藉以符合电子产品的需求。
请参阅图1A至图1B，前述能整合多个晶片的半导体装置的主要类型为于单一的半导体装置中整合多个晶片者，其如图1A所示，该半导体装置在一基板10上承载多个堆迭的半导体晶片11，或于一基板10上布设多个置于同一平面上的半导体晶片11，如图1B所示。然而，该种半导体装置的缺点在于其完成封装后始能对各半导体晶片11进行电性及信赖性等测试，若其中有任一半导体晶片11无法通过测试，将导致整个半导体装置无法使用。
为改善前揭缺失，第6,303,997号美国专利揭露一种整合有多个晶片的半导体装置的类型，其如图1C所示，于一基板10的上表面安置一电性连接至该基板10的半导体晶片11与另一半导体封装件12，制作该半导体装置时，通过先将该半导体晶片11藉由焊线111电性连接至该基板10上表面并进行测试，俟确认功能正常后，再以表面藕接技术(SurfaceMount Technology，SMT)将另一已完成封装并经测试的BGA型式半导体封装件12藉焊球121电性连接至该基板10，最后再进行整体测试，以避免前述传统的多晶片模组所存在的已知良晶片(Known Good Die，KGD)的问题。
然而，于前揭方法中，该半导体装置必须在该基板10上表面同时设置多数的焊线垫与焊球垫，以供该半导体晶片11与半导体封装件12电性连接至该基板10，不仅造成基板布局限制，同时必须使用高密度的制程，如积层基板(Build-Up substrate)，导致生产成本的提升。
因此，请参阅图1D，第5,783,870号美国专利揭露另一整合有多个晶片的半导体装置的类型，其将多个半导体封装件整合为单一的模组化的半导体装置(ModuleSemiconductor Device)。该模组化半导体装置于一第一半导体封装件12a上迭接一第二半导体封装件12b，并藉该第二半导体封装件12b的多个焊球121b焊接至该第一半导体封装件12a；同理，第三半导体封装件12c与第二半导体封装件12b的迭接亦然，且该第一半导体封装件12a藉由多个焊球121a电性连接至基板10，使该第二半导体封装件12b与第三半导体封装件12c得以电性连接至该基板10，且该模组化的半导体装置所使用的半导体封装件12a,12b,12c得先个别予以测试，俟测试通过后再加以迭接。
然而，前述方法虽可利用一般基板解决多晶片模组所存在的已知良晶片(KnownGood Die，KGD)的问题。然而，该种具多个迭接半导体封装件的装置中，位于下层的半导体封装件还具有安置半导体晶片的晶片接置区。因此，仅能在该晶片接置区以外的其余部分的区域才可供上层半导体封装件的焊球进行焊接以电性连接至下层半导体封装件，也就是，使该电性连接区域(electrically-connecting area)大小受到限制，而影响到基板的电路布局性，遂亦局限往上层半导体封装件的输入/输出连接端(I/O Connection)的数量与布设，导致整体封装装置的设计灵活性(design flexibility)受到不利的影响。
因此，如何藉由简单的制程技术与花费较少的成本，克服现有技术中的问题，实为业界迫切待解之题。
发明内容
鉴于上述现有技术的缺失，本发明的目的为提供一种封装结构及其制法，以在不改变现有机台的情况下，使后续设置的电子元件不受到限制。
本发明的封装结构包括：基板，其具有多个第一连接垫及相对的顶面及外露该多个第一连接垫的底面；多个导电柱，其嵌埋于该基板中，且与该第一连接垫电性连接，该导电柱的端面并外露于该基板的顶面；多个第一凸块，其形成于该导电柱的端面上；多个第二凸块，其形成于该基板的顶面上，且该第二凸块的高度大于该第一凸块的高度；以及至少一第一电子元件，其设置于该基板的顶面上方，且与该第一凸块电性连接。
为得到本发明的封装结构，本发明还提供一种封装结构的制法，其包括：提供一具有多个第一连接垫及相对的顶面及外露有该多个第一连接垫的底面的基板，该基板中嵌埋有多个与该第一连接垫电性连接的导电柱，且该导电柱外露于该基板的顶面；于该基板的顶面形成导电层；于该导电层上形成多个第一凸块及第二凸块，该第二凸块的高度大于该第一凸块的高度；移除该导电层未为该第二凸块及第一凸块所覆盖的部分；以及设置并电性连接至少一第一电子元件于该第一凸块上。
由上可知，本发明封装结构及其制法主要藉由在该基板上形成多个高度大于第一凸块的第二凸块，并藉此使设置第一电子元件后，后续堆迭的第二电子元件能使该第一电子元件收纳于该第二电子元件、第二凸块与基板所形成的容置空间，而不仅能避免电性连接区域的大小受到限制，更能有效降低封装结构的高度。
附图说明
图1A至图1D为现有封装堆迭结构的制法的剖视图。
图2A至图2D为本发明的基板的制法的剖视图。
图3A至图3I为本发明的封装结构的制法的剖视图，其中，图3G’为图3G的另一实施例。
符号说明
10 基板
11 半导体晶片
111 焊线
12 半导体封装件
12a 第一半导体封装件
12b 第二半导体封装件
12c 第三半导体封装件
121、121a、121b 焊球
20、20’ 离型件
20a 第一表面
20b 第二表面
200 铁
201 金属材料
21 基板
21a 顶面
21b 底面
210 第一阻层
210a 第一开口
211 第一连接垫
212 第二阻层
212a 第二开口
213 导电柱
213a 端面
214 绝缘体
22 聚合物层
22a 开口
23 导电层
24 第三阻层
24a 第三开口
24b 第四开口
25 第一凸块
26 第四阻层
26a 第五开口
27 第二凸块
270 支撑部
271 连接部
29 表面处理层
3 第二电子元件
3a 容置空间
30 第一电子元件。
具体实施方式
以下藉由特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点与功效。本发明也可藉由其他不同的具体实例加以施行或应用，本说明书中的各项细节也可基于不同观点与应用，在不悖离本发明的精神下进行各种修饰与变更。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本创作所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如「第一」、「第二」、「上」及「一」等用语，也仅为便于叙述的明了，而非用以限定本创作可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
请参阅图2A至图2D为显示本发明的基板的制法剖视图。
如图2A所示，提供一具有相对的第一表面20a与第二表面20b的离型件20。
于本实施例中，以表面形成有金属材料201的铁200组成的金属复合材料做为离型件20。于本发明的制法中，对于该金属材料的材质并未有特殊限制，仅需为可被蚀刻的金属即可。
如图2B至图2C所示，于该离型件20的第一表面20a上形成多个第一连接垫211，并于该第一连接垫211上形成导电柱213。
于本实施例中，如图2B所示，先于该离型件20的第一表面20a上形成具有第一开口210a的第一阻层210，再于该第一开口210a中填充导电材料，以形成该第一连接垫211，接着，于该第一阻层210上形成具有外露出部分该第一连接垫211的第二开口212a的第二阻层212。
如图2C所示，于该第二开口212a中填充导电材料，以形成该导电柱213。
于本实施例中，对于该导电材料的材质并未有特殊限制，包括但不限于铜。
如图2D所示，移除该第一阻层210及第二阻层212，以外露出该导电柱213与第一连接垫211，并于该离型件20上形成绝缘体214，使该导电柱213与第一连接垫211嵌埋于该绝缘体214中。该绝缘体214具有相对的顶面21a及底面21b，且该底面21b连接该离型件20。
于本实施例中，于形成包覆该导电柱213与第一连接垫211的该绝缘体214后，研磨该绝缘体214的顶面21a，以使该顶面21a外露出该导电柱213的端面213a，而得到外露有导电柱213的端面213a的基板21。
请参阅图3A至图3I，其为显示本发明的封装结构的制法剖视图，其中，图3G’为图3G的另一实施例。
如图3A所示，其延续自图2D。先提供一具有相对的顶面21a及外露有该等第一连接垫211的底面21b的该基板21，并于该基板21的顶面21a上形成具有多个外露出该导电柱213的端面213a的开口22a的聚合物层22。
于本实施例中，该基板21的底面21b连接至该离型件20。于本实施例中，该聚合物层22的材料并未有特殊限制，该聚合物层22可为环氧树脂等电性隔绝的薄型(lowprofile)聚合胶材。
如图3B所示，于该聚合物层22上形成导电层23。
于本实施例中该导电层23的材料为沉积铜，本发明可藉由该聚合物层22达到提升导电层23与该基板21间的接着能力的功效。
接着，依据图3C至图3F所示的步骤，于该导电层23上形成多个第一凸块25及第二凸块27。
如图3C所示，于该导电层23上形成第三阻层24，该第三阻层24具有多个外露出该导电层23对应于该导电柱213的端面213a的部分的第三开口24a以及多个外露出部分未对应于该导电柱213的端面213a的该导电层23的第四开口24b。
于本实施例中该第三开口24a的宽度小于该第四开口24b的宽度。
如图3D所示，于该第三开口24a与第四开口24b中填充导电材料，以构成与该导电柱213电性连接的第一凸块25及支撑部270。
于本实施例中，该第一凸块25的高度等于该支撑部270的高度，且该第一凸块25的宽度小于该支撑部270的宽度。
如图3E所示，于该第三阻层24上形成第四阻层26，且该第四阻层26形成有外露出该支撑部270的第五开口26a；于该第五开口26a中填充导电材料，以于该支撑部270上形成连接部271，俾由该支撑部270与连接部271构成第二凸块27。
于本实施例中，该支撑部270的宽度大于或等于该连接部271的宽度。
如图3F所示，移除该第三阻层24与第四阻层26，以外露出该第一凸块25及第二凸块27。
于本实施例中，该第二凸块27的高度大于该第一凸块25，且该第一凸块25的宽度小于该第二凸块27的宽度。
如图3G所示，移除该导电层23未为该第一凸块25及第二凸块27所覆盖的部分，以外露出部分该聚合物层22。
于本实施例中，由于该基板21形成于离型件20上，因此，于移除该离型件20后，即外露出该第一连接垫211及该基板21的底面21b。
另外，于本实施例的另一实施方式中，通过于该第一凸块25、第二凸块27及第一连接垫211上形成表面处理层29，例如有机保焊层(OSP)。于前述实施例中，于移除该离型件20时，可仅移除部份该离型件20，以外露出该第一连接垫211，并保留部分该离型件20’以防止所欲形成的该表面处理层29发生溢流并提供刚性支撑，如图3G’所示。
如图3H所示，其接续图3G的步骤，设置并电性连接至少一第一电子元件30于该第一凸块25上。
于本实施例中，各该第二凸块27的高度大于各该第一凸块25与第一电子元件30的高度的总和。于本实施例，该第一电子元件30为半导体晶片、经封装或未经封装的半导体元件，较佳者为经测试为良晶片的半导体晶片。
如图3I所示，设置并电性连接至少一第二电子元件3至该第二凸块27，使该第二凸块27与该第二电子元件3间形成一容置空间3a以供收纳该第一电子元件30，即该第一电子元件30位于该基板21与该第二电子元件3之间。
于本实施例中，该第二电子元件3为基板、半导体晶片、中介板、经封装或未经封装的半导体元件。
请参阅图3H，本发明的封装结构具有：基板21，其具有多个第一连接垫211及相对的顶面21a及外露有该多个第一连接垫211的底面21b；多个导电柱213，其嵌埋于该基板21中，且与该第一连接垫电性连接211，该导电柱213的端面213a外露于该基板21的顶面21a；多个第一凸块25，其形成于该导电柱213的端面213a；多个第二凸块27，其形成于该基板21的顶面21a，该第二凸块27的高度大于该第一凸块25的高度；以及至少一第一电子元件30，其设置于该基板21的顶面21a上方，且与该第一凸块25电性连接。
于本实施例中，本发明的封装结构还包括聚合物层22与导电层23，该聚合物层22形成于该基板21的顶面21a，并外露出该导电柱213的端面213a，该导电层23形成于该导电柱213的端面213a与第一凸块25间以及该聚合物层22与第二凸块27间。
于本实施例中，该第二凸块27包括形成于该基板21的顶面21a的支撑部270与形成于该支撑部270上的连接部271，该第二凸块27的高度大于该第一凸块25与第一电子元件30的高度的总和。
于本发明的封装结构及其制法中，该基板21的顶面21a还可形成有线路层(未图示)，其用于将该第一凸块25与该第二凸块27电性连接至该导电柱213。
综上所述，本发明的封装结构及其制法藉由第二凸块的高度大于第一凸块的高度，使得于该封装结构的第二凸块上接置第二电子元件(如，外部元件)时，第一电子元件能收纳于基板与该第二电子元件之间，藉以在现有封装技术下，不需改变或增加机台即能避免电性连接区域的大小受到限制，进而能提升电路布局性。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修饰与改变。因此，本发明的权利保护范围，应如权利要求书所列。

Claims (16)

1.一种封装结构的制法，包括：
提供一具有多个第一连接垫及相对的顶面及外露有该多个第一连接垫的底面的基板，该基板中嵌埋有多个与该第一连接垫电性连接的导电柱，且该导电柱外露于该基板的顶面，其中提供该基板的步骤包括：
提供一具有相对的第一表面与第二表面的离型件；
于该离型件的第一表面上形成该多个第一连接垫；
于该第一连接垫上形成该导电柱；
于该离型件的第一表面上形成绝缘体，以使该多个第一连接垫及导电柱嵌埋于该绝缘体中，而得到具有相对的外露出该导电柱的端面的顶面与底面的该基板，该基板以该底面与该离型件的第一表面接触；及
移除部分该离型件以使该第一连接垫外露于该基板的底面，且保留部分该离型件以提供刚性支撑；
于该基板的顶面上形成外露出该导电柱的端面的聚合物层；
于该聚合物层与外露出该聚合物层的该导电柱的端面上形成导电层；
于该导电层上形成多个第一凸块及第二凸块，该第二凸块的高度大于该第一凸块的高度；
移除该导电层未为该第二凸块及第一凸块所覆盖的部分；以及
设置并电性连接至少一第一电子元件于该第一凸块上。
2.如权利要求1所述的封装结构的制法，其特征在于，形成该多个第一连接垫与导电柱的步骤包括：
于该离型件的第一表面上形成具有第一开口的第一阻层；
于该第一开口中形成该多个第一连接垫；
于该第一阻层与该多个第一连接垫上形成具有外露出部分该第一连接垫的第二开口的第二阻层；
于该第二开口中形成该多个导电柱；以及
移除该第一阻层及第二阻层。
3.如权利要求1所述的封装结构的制法，其特征在于，于形成该绝缘体之后，还包括研磨该绝缘体，以使该导电柱的端面外露出该顶面。
4.如权利要求1所述的封装结构的制法，其特征在于，形成该多个第一凸块及第二凸块的步骤包括：
于该导电层上形成具有多个第三开口与多个第四开口的第三阻层，以供部分对应于该导电柱的端面的该导电层外露于该第三开口，及供部分未对应于该导电柱的端面的该导电层外露于该第四开口；
于该第三开口与第四开口中分别形成与该导电柱电性连接的该第一凸块及支撑部；
于该第三阻层上形成具有多个外露出该支撑部的第五开口的第四阻层；
于该第五开口中的该支撑部上形成连接部，以供该支撑部与连接部构成该第二凸块；以及
移除该第三阻层与第四阻层。
5.如权利要求1所述的封装结构的制法，其特征在于，该制法还包括于设置该第一电子元件前，于该第一凸块、第二凸块及第一连接垫上形成表面处理层。
6.如权利要求1所述的封装结构的制法，其特征在于，该制法还包括设置并电性连接至少一第二电子元件至该第二凸块，而令该第一电子元件位于该基板与该第二电子元件之间。
7.如权利要求1所述的封装结构的制法，其特征在于，该基板的顶面还形成有线路层，以由该线路层将该第一凸块与该第二凸块电性连接至该导电柱。
8.一种封装结构，包括：
基板，其具有多个第一连接垫及相对的顶面及外露该多个第一连接垫的底面；
部分离型件，其形成该基板的底面，且外露出该第一连接垫；
多个导电柱，其嵌埋于该基板中，且与该第一连接垫电性连接，该导电柱的端面外露于该基板的顶面；
聚合物层，其形成于该基板的顶面，并外露出该导电柱的端面；
多个第一凸块，其形成于该导电柱的端面上；
多个第二凸块，其形成于该聚合物层上，且该第二凸块的高度大于该第一凸块的高度；
导电层，其形成于该导电柱的端面与第一凸块间及该聚合物层与第二凸块间；以及
至少一第一电子元件，其设置于该基板的顶面上方，且与该第一凸块电性连接。
9.如权利要求8所述的封装结构，其特征在于，各该第二凸块的高度大于各该第一凸块与该第一电子元件的高度的总和。
10.如权利要求8所述的封装结构，其特征在于，该第二凸块包括形成于该基板的顶面的支撑部与形成于该支撑部上的连接部。
11.如权利要求10所述的封装结构，其特征在于，该支撑部的宽度大于或等于该连接部的宽度。
12.如权利要求8所述的封装结构，其特征在于，该第一电子元件为半导体晶片、经封装或未经封装的半导体元件。
13.如权利要求8所述的封装结构，其特征在于，该封装结构还包括至少一第二电子元件，其接合至并电性连接于该第二凸块，而令该第一电子元件位于该基板与该第二电子元件之间。
14.如权利要求13所述的封装结构，其特征在于，该第二电子元件为基板、半导体晶片、中介板、经封装或未经封装的半导体元件。
15.如权利要求8所述的封装结构，其特征在于，该封装结构还包括表面处理层，其形成于该第一凸块、第二凸块及第一连接垫上。
16.如权利要求8所述的封装结构，其特征在于，该封装结构还包括线路层，其形成于该基板的顶面，以将该第一凸块与该第二凸块电性连接至该导电柱。
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