CN108695284A - 包括纵向集成半导体封装体组的半导体设备 - Google Patents

包括纵向集成半导体封装体组的半导体设备 Download PDF

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Publication number
CN108695284A
CN108695284A CN201710224640.4A CN201710224640A CN108695284A CN 108695284 A CN108695284 A CN 108695284A CN 201710224640 A CN201710224640 A CN 201710224640A CN 108695284 A CN108695284 A CN 108695284A
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China
Prior art keywords
semiconductor
semiconductor package
group
package body
substrate
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CN201710224640.4A
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English (en)
Inventor
刘扬名
邱进添
姬忠礼
董少鹏
周增钰
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SanDisk Information Technology Shanghai Co Ltd
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SanDisk Information Technology Shanghai Co Ltd
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Priority to CN201710224640.4A priority Critical patent/CN108695284A/zh
Priority to US15/620,471 priority patent/US10236276B2/en
Priority to KR1020180030303A priority patent/KR102020723B1/ko
Publication of CN108695284A publication Critical patent/CN108695284A/zh
Pending legal-status Critical Current

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Abstract

公开了一种半导体设备，所述半导体设备至少包括第一组和第二组纵向堆叠且互连的半导体封装体。所述第一组和第二组半导体封装体可以在封装体数量以及功能上彼此不同。

Description

包括纵向集成半导体封装体组的半导体设备
背景技术
对便携式消费者电子设备需求的强烈增长正在驱动对高容量存储设备的需要。非易失性半导体存储器设备(比如闪存存储卡)正变得广泛用于满足对数字信息存储和交换的日益增长的需求。它们的便携性、多功能性和坚固的设计与其高可靠性和大容量一起使得此类存储器设备对用于许多电子设备是理想的，包括例如数码相机、数字音乐播放器、视频游戏控制台、PDA和蜂窝电话。
虽然许多不同的封装配置是已知的，闪存存储卡一般可以被制造成***级封装(SiP)或多芯片模块(MCM)，其中，多个裸片安装和互连在小足迹衬底上。所述衬底总体上可以包括刚性电介质基底，所述刚性电介质基底具有在一侧和两侧上蚀刻出的导电层。所述裸片与所述(多个)导电层之间形成了电连接，并且所述(多个)导电层提供了用于将所述裸片连接至主机设备的电引线结构。一旦进行了所述裸片与衬底之间的电连接，组件将则通常被包入提供保护性封装的模制化合物中。
为了最高效地使用封装覆盖区(footprint)，已知将半导体裸片堆叠在彼此顶部上。为了提供对半导体裸片上键合焊盘的访问，将裸片堆叠，或者利用相邻裸片之间的间隔层完整地覆盖彼此，或者利用偏移。在偏移配置中，将裸片堆叠在另一裸片的顶部上，从而使得下部裸片的键合焊盘在左侧被暴露。
随着半导体裸片变得更薄，并且为了提高半导体封装体内的存储器容量，半导体封装体内所堆叠的裸片量继续增加。然而，这可有助于从上部裸片向下至衬底的长键合接线。长接线键合容易被损坏或者电短路到其他接线键合，并且比较短键合接线具有更高的信噪比。此外，封装体中大量的半导体裸片会不利地影响成品率。
附图说明
图1是根据本技术的实施例的半导体设备的整体制造过程的流程图。
图2是根据本技术的实施例的所述制造过程中第一步的半导体设备的侧视图。
图3是根据本技术的实施例的所述制造过程中第二步的半导体设备的顶视图。
图4是根据本技术的实施例的所述制造过程中第三步的半导体设备的侧视图。
图5是根据本技术的实施例的所述制造过程中第四步的半导体设备的侧视图。
图6是根据本技术的实施例的所述制造过程中第五步的半导体设备的侧视图。
图7是根据本技术的实施例的所述制造过程中第五步的半导体设备的简化透视图。
图8是根据本技术的实施例的所述制造过程中第六步的半导体设备的侧视图。
图9是根据本技术的实施例的所述制造过程中第六步的半导体设备的简化透视图。
图10是用于包封半导体设备的模套(mold chase)内的半导体设备的横截面图。
图11是根据本技术的实施例的第一完整半导体封装体的侧视图。
图12至图18根据本技术的示例实施例示出了各种配置中安装至一组一个或多个第二半导体封装体的第一半导体封装体。
具体实施方式
现在将参照附图对本技术加以描述，在实施例中，本技术涉及一种包括纵向堆叠且互连的半导体封装体组的半导体设备。所述第一组和第二组半导体封装体可以在封装体数量以及功能上彼此不同。
要理解的是，本技术可以采用许多不同形式来实施并且不应解释为局限于在此阐述的所述实施例。相反，提供这些实施例使得本公开将是彻底和完整的，并且将本技术的范围完全地传达给本领域技术人员。的确，本技术意在涵盖这些实施例的多种替代形式、修改形式以及等同形式，它们包括在所附权利要求书定义的本技术的范围和精神内。而且，在本技术的以下详细描述中，给出了很多具体细节以提供对本技术的透彻理解。然而，对于本领域的技术人员显而易见的是：可以在没有此类具体细节的情况下实施本技术。
如在此可使用的术语“顶部”和“底部”、“上部”和“下部”以及“竖直”和“水平”被举例并仅出于示意性目的，并且不意在限制本技术的描述，因为所引用的项在位置和取向上可以交换。同样，如在此所使用的，术语“基本上”、“几乎”和/或“约”意味着指定的尺寸或参数可以在给定应用的可接受制造容差内变化。在一个实施例中，所述可接受制造容差为±.25％。
现在将参照图1的流程图以及图2至图18的顶视图、侧视图和透视图解释本技术的实施例。虽然图2至图18各自示出了单独半导体封装体100和/或170、或其一部分，要理解的是，封装体100和170可以与衬底面板上的多个其他封装体一起被分批处理，从而实现规模经济。衬底面板上的封装体100、170的行和列的数量可以不同。
用于制造半导体封装体100的衬底面板以多个衬底102开始(再次，图2至图18中示出了一个这样的衬底)。衬底102可以是各种不同芯片承载介质，包括印刷电路板(PCB)、引线框或带式自动焊接(TAB)带。当衬底102是PCB时，所述衬底可以由如图2中所示具有顶部导电层105和底部导电层107的内核103形成。内核103可以由各种电介质材料形成，比如例如聚酰亚胺层压材料、环氧树脂(包括RF4和RF5)、双马来酰亚胺三嗪树脂(BT)等。所述内核可以具有40微米(μm)至200μm之间的厚度，但是在替代性实施例中所述内核的厚度可以在这个范围之外变化。在替代性实施例中，内核103可以是陶瓷或有机的。
环绕内核的导电层105、107可以由铜或铜合金、镀铜或镀铜合金、合金42(42Fe/58Ni)、镀铜钢、或其他适用于衬底面板的金属和材料形成。所述导电层可以具有约10μm至25μm的厚度，但是在替代性实施例中所述层的厚度可以在这个范围之外变化。
图1是根据本技术的实施例的用于形成半导体设备180的制造过程的流程图。在步骤200中，可以对第一半导体封装体100的衬底102进行钻孔以在衬底102中限定通孔过孔104。所述过孔104是举例而言，并且衬底102可以比附图中所示的包括更多的过孔104，并且它们与附图中所示的相比可以处于不同位置。接下来在步骤202中在顶部和底部导电层中的一者或两者上形成电导图案。所述(多个)电导图案可以包括电迹线106、衬底的顶表面上的接触焊盘109以及衬底的底表面上的接触焊盘108，如例如图3和图4中所示。迹线106和接触焊盘109、108(仅其中一部分在附图中编号)是举例而言的，并且衬底102可以比附图中所示的包括更多迹线和/或接触焊盘，并且它们与附图中所示的相比可以处于不同位置。在一个实施例中，衬底102可以包括处于衬底102的相对边的一行或多行接触焊盘109，如图3中所示。进一步的实施例可以采用多层衬底，除了所述顶表面和/或底表面上的那些之外，所述多层衬底包括内部电导图案。
在各实施例中，成品半导体设备可以用作BGA(球栅阵列)封装体。衬底102的下表面可以包括如下文所解释的用于接收焊球的接触焊盘108。在各实施例中，成品半导体设备180可以是LGA(平面栅格阵列)封装体，所述LGA封装体包括用于将成品设备180可移除地耦合在主机设备内的触指。在此类实施例中，所述下表面可以包括触指，而非接收焊球的接触焊盘。衬底102的顶表面和/底表面上的电导图案可以通过各种适当工艺形成，包括例如各种光刻工艺。
再次参照图1，接下来在步骤204中可以对衬底102进行检查。此步骤可以包括自动光学检查(AOI)。一旦被检查，在步骤206中可以将焊接掩模110(图4)施涂至衬底。在施涂阻焊掩模之后，在步骤208中，可以通过已知的电镀或薄膜沉积工艺为接触焊盘、以及电导图案上的任何其他有待焊接区域镀上例如Ni/Au、合金42等。然后在步骤210中衬底102经历操作测试。在步骤212，可以在视觉上检查衬底，包括例如自动化视觉检查(AVI)和最终视觉检查(FVI)从而检查杂质、擦伤和变色。这些步骤中的一个或多个可以省略或以不同的顺序执行。
假定衬底102通过检查，接下来在步骤214中可以将无源部件112(图3)附接至衬底102。所述一个或多个无源部件可以包括例如一个或多个电容器、电阻器和/或电感器，但是可以考虑其他部件。所示的无源部件112仅是举例而言，并且在进一步的实施例中数量、类型和位置可以不同。
参照图5，接下来在步骤220中可以将许多半导体裸片124堆叠在衬底102上。半导体裸片124可以例如是存储器裸片(比如NAND闪存裸片)，但是可以使用其他类型的裸片124。这些其他类型的半导体裸片包括但不限于控制器裸片，比如ASIC、或RAM(比如SDRAM)。半导体裸片124可以进一步替代性地用于将封装体100形成为功率半导体设备(比如例如开关或整流器)中。当包括多个半导体裸片124时，半导体裸片124可以以偏移阶梯式配置被堆叠在彼此顶部上从而形成裸片堆叠120。可以存在不止一个裸片堆叠120，其中交替的堆叠在相反方向成阶梯式。实施例可以包括不同数量的半导体裸片，包括例如1个、2个、4个、8个、16个、32个或64个裸片。在进一步的实施例中，可以存在其他数量的裸片。所述裸片可以使用裸片粘贴膜固定至衬底和/或彼此。作为一个示例，裸片粘贴膜可以是来自汉高股份有限公司(Henkel AG&Co.KGaA)的8988UV环氧基树脂，被固化至B级以初步固定堆叠120中的裸片124，并随后固化至最终C级以初步固定堆叠120中的裸片124。
在步骤222，再分布层(RDL)126可以固定至裸片堆叠的顶部。RDL 126可以是例如由FR4和FR5形成的刚性层、或例如由聚酰亚胺带形成的柔性层。参照图5至图7，RDL 126可以具有沿着RDL 126的边缘的键合焊盘134，在尺寸和配置上与半导体裸片124上所设置的键合焊盘132类似。(为了简化起见，图7和图9各自示出了堆叠120中的单个半导体裸片124，但是图7和图9中所示的半导体封装体100可以与所展示的其他实施例中一样包括多个半导体裸片124)。键合焊盘134被示为沿着单个边缘，但键合焊盘134可以被设置为沿两个相对或相邻边、沿三个边或沿RDL 126的所有边。
RDL 126可以进一步在上表面上包括再分布焊盘130的图案。在实施例中，电迹线可以设置在RDL键合焊盘134与再分布焊盘130之间从而有效地将键合焊盘134再分布于RDL126的上表面上方。可以存在比所示出的更多的键合焊盘134，从而使得每个键合焊盘134可以连接至再分布焊盘130。可以将钝化层136施涂于电迹线和再分布焊盘130上方，所述钝化层136然后被蚀刻或另外显影以显露再分布焊盘130。在步骤224，焊球140可以施涂于再分布焊盘130，如图6和图7中所示。附图中所示的再分布焊盘130和焊球140的图案是举例而言，并且在进一步的实施例中可以不同。可以提供其他电连接器代替焊球140，包括但不限于焊膏。
现在参照图8和图9的视图，堆叠120中的对应裸片124接下来可以彼此电连接，在步骤230中衬底102和RDL 126使用接线键合138。如所示的，每个半导体裸片124可以包括沿着裸片124的边缘的一行裸片键合焊盘132。要理解的是，每个裸片124可以比图9中所示的包括更多的裸片键合焊盘132。半导体裸片的所述行中每个裸片键合焊盘132可以使用接线键合138电连接至下一相邻半导体裸片的所述行中的相应的键合焊盘132。底部半导体裸片124的每个裸片键合焊盘132可以使用接线键合138电连接至衬底102上的一行接触焊盘中的相应的键合焊盘109。
虽然接线键合138可以通过各种技术形成，在一个实施例中，接线键合138可以形成为球焊，但是可以考虑其他类型的焊接。接线键合138总体上被示为裸片堆叠120中从一层到下一层、并且到衬底102和RDL 126的竖直列。然而，在替代性实施例中，所述接线键合中的一个或多个可以对角线地从一层延伸至下一层。进一步，情况可以的是，接线键合跳过裸片堆叠120中的一层或多层。可想到的是，在进一步的实施例中，在球焊步骤224之前执行接线键合步骤230。
在裸片堆叠120的电连接和在RDL 126上形成焊球之后，可以在步骤234中并如图10和图11中所示将半导体封装体100包封在模制化合物142中。可以将半导体设备放置在包括上模板146和下模板148的模套144内。然后可以将融化的模制化合物142注入模套144以将半导体封装体100的部件包入保护性壳体中，例如在压缩模塑工艺中。模制化合物142可以包括例如固态环氧树脂、酚树脂、熔融二氧化硅、结晶二氧化硅、碳黑和/或金属氢氧化物。此类模制化合物是例如从住友集团(Sumitomo Corp)和日东电工集团(Nitto-DenkoCorp.)(均在日本设立总部)可获得的。可以考虑来自其他制造商的其他模制化合物。可以根据其他已知工艺施涂所述模制化合物，例如通过传递模塑或注射模塑技术。
本技术的一种特征是RDL 126的焊球140(在此还被称为“RDL焊球140”)的多个部分保持暴露在模制化合物142的外表面。因此，下部模板148可以与脱模膜150一致。当半导体封装体100被放置在模套144内时，RDL焊球140的尖端嵌入脱模膜150内。所述脱模膜可以例如是聚合物，所述聚合物是柔性的并且到一定柔软程度，从而使得当封装体100被***模套144内时，RDL焊球140的尖端嵌入脱模膜150。所述脱模膜在整个包封过程中保持其结构，从而使得模制化合物142将RDL 126、裸片124和接线键合138暴露，但在包封过程完成时，RDL焊球140的尖端保持通过模制化合物142的表面而暴露。在完成时，所述脱模膜150可以轻易地从RDL焊球移除。合适的脱模膜150的一个示例是含氟聚合物，比如像由在美国宾夕法尼亚州(Pennsylvania,USA)有办公司的美洲AGC化学品有限公司(AGC ChemicalsAmericas,Inc)出售的ETFE薄膜(ETFE film)。对脱模膜150而言其他聚合物是可能的。
在步骤236，焊球154(图11)可以固定至封装体100的衬底102的下表面上的接触焊盘108上。焊球154(在此还称为“衬底焊球154”)可以用于将半导体封装体100固定至主机设备(未示出)，比如印刷电路板。如下面所解释的，焊球154可以替代性地用于将半导体封装体100固定至一个或多个其他半导体封装体。
如上所述，半导体封装体100可以形成于衬底的面板上。在形成和包封封装体100之后，在步骤240中可以使封装体100与彼此单片化开来，从而形成如图11中所示的成品半导体封装体100。可以通过各种切割方法中的任何一种对半导体封装体100进行单片化，包括锯切、水射流切割、激光切割、水引导激光切割、干介质切割、以及金刚石涂层线切割。虽然直线切割将限定基本上矩形或正方形的半导体封装体100，要理解的是，在本技术的进一步实施例中，半导体封装体100可以具有矩形和正方形以外的形状。
在形成已包封的半导体封装体100之前、期间或之后，在步骤242中并如例如图12至图18中所示的那样，可以形成一组一个或多个第二半导体封装体170。在实施例中，所述一组一个或多个封装体170与封装体100可以是由相同步骤形成的闪存封装体，比如上述的图3的步骤200至240。然而，本技术的进一步特征是(多个)半导体封装体170不需要与封装体100是相同配置或相同类型的半导体封装体。作为示例，所述一组一个或多个封装体170可以包括其他类型的存储器封装体，比如SDRAM和其他类型的RAM。所述一组一个或多个封装体170可以替代性地或另外地包括控制裸片(比如ASIC)或功率半导体设备(比如开关或整流器)。可以考虑其他类型的半导体封装体包括在所述一组一个或多个封装体170内。
在步骤244中，所述一组一个或多个第二半导体封装体170可以安装至所述第一半导体封装体100。当半导体封装体170在其两个主要表面上都具有电连接(顶表面上的RDL焊球140和底表面上的衬底焊球154)时，本技术的进一步特征是可以将所述一组一个或多个第二半导体封装体170固定在封装体100上方和/或下方。在以下说明中并如在此所使用的，包括延伸穿过模制化合物的表面的RDL焊球140的半导体封装体被称为半导体封装体100。不包括RDL焊球140的封装体被成为半导体封装体170之一。
图12示出了第二组三个半导体封装体170，通过RDL焊球140物理连接且电连接至半导体封装体100从而形成半导体设备180。具体地，半导体封装体170可以在底表面上具有接触焊盘，所述接触焊盘采用与RDL焊球140(接触焊盘与其配对并连接)的图案匹配的图案，如在焊料回流步骤中。半导体设备180通过封装体100上的衬底焊球154物理连接且电连接至主机设备174，比如像印刷电路板(PCB)。因而，这组半导体封装体170与主机设备174之间通过半导体封装体100交换信号和电压。
在实施例中，一旦彼此固定，在进一步的包封过程中可以将设备180的两个封装体100和170包封在一起。替代性地，可以用环氧树脂176回填封装体100与170之间的任何空间。在进一步的实施例中，不执行进一步的包封或回填步骤，并且简单地通过焊球140将封装体100和170固定在一起。
在一个示例中，图12中的半导体封装体100可以包括多个非易失性存储器裸片，比如像NAND闪存裸片。如上文所指示的，封装体100可以替代性地包括一个或多个半导体裸片，并且可以替代性地是非易失性存储器封装体、控制器、功率半导体封装体或某种其他类型的半导体封装体。在一个示例中，单独半导体封装体170可以包括一个或多个半导体裸片，并且可以被配置为非易失性存储器封装体、易失性存储器封装体、控制器和/或功率半导体封装体。针对封装体170可以考虑其他类型的半导体设备。封装体170可以各自是相同类型的，或者可以是不同类型的。例如，所述封装体中的一个可以是控制器，一个可以是易失性存储器并且一个可以是功率半导体封装体。针对封装体170可以考虑其他组合。
在图12中所示的示例中，三个半导体封装体170中的每一个被示为安装至半导体封装体100的表面上的三行RDL焊球140。这仅仅是举例而言，并且半导体封装体170可以使用其他行数的RDL焊球140安装至封装体100。进一步可以考虑到，封装体170可以是不同尺寸和/或使用不同行数的RDL焊球140来固定至封装体100。虽然图12的示例中示出了三个封装体170，可以存在更多或更少数量的封装体170固定至封装体100的RDL焊球140，包括例如1个、2个、4个、5个或6个封装体170。虽然所有行的RDL焊球140被示为安装至封装体170，RDL焊球140中的一些可以被留下而不附接至封装体170。
如上所述，半导体封装体100可以被单片化为单独半导体封装体，每一个包括安装在衬底102上的单组纵向堆叠的半导体裸片。然而，如例如图13和图14中所示，单个半导体封装体100可以替代性地被单片化以包括衬底102上的多组纵向堆叠的半导体裸片。图13和图14的半导体封装体100可以如上所述地制造，但被单片化为包括多个半导体裸片堆叠而不是单个半导体裸片堆叠。
在图13的实施例中，单个半导体封装体170可以安装至半导体封装体100的分开的RDL 126上的RDL焊球140，从而形成成品半导体设备180。在图14的实施例中，多个半导体封装体170可以安装至半导体封装体100的多个RDL 126的RDL焊球140，从而形成成品半导体设备180。图13和图14中的封装体100和170中的每一个可以包括单个半导体裸片或多个半导体裸片(封装体100、170中的一个或多个可以具有不同数量的半导体裸片)。图13和图14中的封装体100和170中的每一个可以用作易失性存储器、非易失性存储器、控制器、功率设备或者具有某些其他功能(封装体100、170中的一个或多个可以具有不同功能)。
图13和图14的实施例示出了半导体封装体100中的三个半导体裸片堆叠，但在进一步的实施例中可以存在多于或少于三个堆叠。图14的实施例示出了安装至半导体封装体100的三个半导体封装体170，但在进一步的实施例中，可以存在多于或少于三个半导体封装体170，包例如1个、2个、4个、5个或6个封装体。在图14的实施例中，半导体设备180可以用作单个集成半导体设备，或者它可以用作三个分开且独立的半导体设备。
在图13和图14的实施例中，一旦彼此固定，在进一步的包封过程中可以将设备180的封装体100和170包封在一起。替代性地，可以用环氧树脂176回填封装体100与170之间的任何空间。在进一步的实施例中，不执行进一步的包封或回填步骤，并且简单地通过焊球140将封装体100和170固定在一起。图13和图14的半导体设备180可以通过封装体100的衬底焊球154被安装至主机设备(未示出)比如PCB。
图15示出了进一步的实施例，其中，单个半导体封装体170被安装至三个分开且独立的半导体封装体100的RDL焊球140。图15可以包括图13中所示实施例的相同部件和特征，除了图15中的单独半导体裸片堆叠被单片化为分开的半导体封装体。
上文相对于图12至图14所描述的实施例包括半导体设备180，所述半导体设备包括两个堆叠的且纵向集成的半导体封装体层级。本技术的进一步实施例可以包括半导体设备，所述半导体设备包括不止两个堆叠的且纵向集成的半导体封装体层级。例如，图16和图17各自示出了三个纵向集成的半导体封装体层级。底部层级可以包括通过衬底焊球154安装至主机设备(未示出)的一个或多个半导体封装体100。第二层级可以包括安装至所述(多个)底部层级半导体封装体100的RDL焊球140的一个或多个半导体封装体100。注意，在这种配置中，可以从所述(多个)第二层级半导体封装体100中省略衬底焊球154，从而使得底部层级的RDL焊球140焊接至所述(多个)第二级半导体封装体100的所述(多个)衬底102上的接触焊盘108。第三层级可以包括安装至所述(多个)第二层级半导体封装体170的RDL焊球140的一个或多个半导体封装体100。
虽然图16和图17示出了包括三个层级半导体封装体的半导体设备180的特定示例，要理解的是，图16和图17的半导体设备180具有各种其他配置。每一层级可以具有一个或多个半导体封装体，并且每个半导体封装体可以包括一个或多个半导体裸片。虽然给定层级上的半导体封装体包括多个半导体裸片，但是半导体裸片可以设置在单个竖直堆叠或多个并排的竖直堆叠中。图16和图17中的封装体100和170中的每一个可以用作易失性存储器、非易失性存储器、控制器、功率设备或者具有某些其他功能(封装体100、170中的一个或多个可以具有不同功能)。
在图16和图17的实施例中，一旦彼此固定，在进一步的包封过程中可以将设备180的封装体100和170包封在一起。替代性地，可以用环氧树脂176对封装体100与170之间的任何空间进行回填，在本实施例中两个分开的层。在进一步的实施例中，不执行进一步的包封或回填步骤，并且简单地通过这两个封装体100中的焊球140将封装体100和170固定在一起。图16和图17的半导体设备180可以通过底部封装体100的衬底焊球154被安装至主机设备(未示出)比如PCB。虽然图16和图17中示出了三个层级的纵向集成半导体封装体100、170，在进一步的实施例中，可以存在不止三个层级的纵向集成半导体封装体100、170。
半导体封装体100中的RDL焊球140的图案(包括数量、安排和间隔)可以协调第二层级封装体170的数量和所述第二层级封装体170中的衬底接触焊盘108的图案来设置。例如，图18示出了半导体封装体100的顶表面，包括RDL焊球140的图案。在本示例中，RDL焊球140被安排成六组，从而接收六个不同的第二层级半导体封装体170(其中之一在底部视图中示出)。如所示的，每一组具有与有待安装至封装体100的封装体170的衬底接触焊盘108的图案协调的RDL焊球140的图案。具体地，RDL焊球140的数量、安排和间隔可以被配置成与衬底接触焊盘108的数量、安排和间隔匹配。在图18的示例中，另一封装体170(未示出)中的衬底接触焊盘108可以与所示的这组衬底接触焊盘108具有相同的图案。
在完成对应的封装体100和170期间和之后(但在彼此固定之前)，可以针对运行和质量对封装体100和170中的每一个进行测试。本技术的一项特征是提供高成品率的半导体设备。例如，在各种半导体裸片(比如非易失性存储器、易失性存储器和控制器)被封装在一起时，缺陷可能会要求丢弃整个封装体。然而，通过将单独部件组装并测试成为封装体，并且然后将所述封装体整合在一起，不得不丢弃整个半导体设备的可能性被最小化。
另外，所制造的半导体封装体的缺陷通常不是致命的，但是导致了具有不同质量的成品半导体封装体。可以在“装箱(binning)”过程中对成品半导体封装体进行测试，并基于其性能对其进行分类。本技术的进一步特征是装箱允许具有类似质量的半导体封装体彼此固定。与包括具有相同数量半导体裸片的单个封装体的设备相比，这允许较高整体质量的生产的半导体设备180。
总而言之，在一个示例中，本技术涉及一种半导体设备，所述半导体设备包括：第一半导体封装体，所述第一半导体封装体包括：第一衬底，第一组一个或多个半导体裸片，再分布层，所述再分布层具有固定至所述再分布层的表面的多个焊球，以及第一模制化合物，所述第一模制化合物包封所述第一半导体封装体的至少一部分，所述焊球的至少一部分延伸穿过所述第一模制化合物的表面；以及一组一个或多个第二半导体封装体，包括：至少一个第二衬底，包括在所述至少一个第二衬底的至少一个表面上的接触焊盘，第二组一个或多个半导体裸片，以及至少一个第二模制化合物，所述至少一个第二模制化合物包封所述至少一个第二半导体封装体的至少一部分；延伸穿过所述第一模制化合物的所述表面的所述焊球的图案与所述至少一个第二衬底的所述至少一个表面上的所述接触焊盘的图案匹配，所述焊球固定至所述接触焊盘从而将所述第一半导体封装体耦合至所述一组一个或多个第二半导体封装体。
在另一示例中，本技术涉及一种半导体设备，所述半导体设备包括：第一组一个或多个第一半导体封装体，包括：至少一个第一衬底，第一组一个或多个第一半导体裸片，再分布层，所述再分布层具有固定至所述再分布层的表面的多个焊球，以及第一模制化合物，所述第一模制化合物包封所述第一组一个或多个第一半导体封装体中的至少一部分，所述焊球通过所述第一模制化合物的表面而暴露；以及第二组一个或多个第二半导体封装体，包括：至少一个第二衬底，包括在所述至少一个第二衬底的至少一个表面上的接触焊盘，第二组一个或多个第二半导体裸片，以及至少一个第二模制化合物，所述至少一个第二模制化合物包封所述第二组一个或多个第二半导体封装体中的至少一部分；所述再分布层的所述焊球的图案与所述至少一个第二衬底上的所述接触焊盘的图案匹配，所述焊球固定至所述接触焊盘从而将所述第一组一个或多个第一半导体封装体耦合至所述第二组一个或多个第二半导体封装体。
在进一步的示例中，本技术涉及一种半导体设备，所述半导体设备包括：第一组一个或多个第一半导体封装体，包括：至少一个第一衬底装置，用于向和从半导体裸片传递信号，安装在所述衬底装置上的第一组一个或多个第一半导体裸片，再分布装置，用于将所述再分布装置上的多个接触焊盘电连接至多个焊接装置，所述多个焊接装置固定至所述再分布装置的表面，以及第一包封装置，用于包封所述第一组一个或多个第一半导体封装体中的至少一部分，所述焊装置通过所述第一包封装置的表面而暴露；以及第二组一个或多个第二半导体封装体，包括：至少一个第二衬底装置，用于向和从半导体裸片传递信号，所述至少一个第二衬底装置包括在所述至少一个第二衬底的至少一个表面上的电连接器装置，第二组一个或多个第二半导体裸片，以及第二包封装置，所述第二包封装置包封所述第二组一个或多个第二半导体封装体中的至少一部分；所述再分布装置的所述焊接装置的图案与所述至少一个第二衬底上的所述电连接器装置的图案匹配，所述焊接装置固定至所述电连接器装置从而将所述第一组一个或多个第一半导体封装体耦合至所述第二组一个或多个第二半导体封装体。
在另一示例中，本技术涉及一种半导体设备，所述半导体设备包括：至少一个第一半导体封装体，包括：第一衬底，所述第一衬底包括第一多个互连特征，其中，所述第一多个互连特征产生第一图案；至少一个第一组半导体裸片，电连接至所述第一多个互连特征；第一层，所述第一层连接至所述第一组半导体裸片，所述第一层具有固定至所述第一层的表面的第二多个互连特征，其中，所述第二多个互连特征电连接至所述第一组半导体裸片，进一步地，进一步其中，所述第二多个互连特征产生第二图案；以及包封层，所述包封层定位在所述第一半导体封装体周围，其中，所述第一多个互连特征通过所述第一包封层的表面而暴露；以及至少一个第二半导体封装体，包括：第二衬底，所述第二衬底包括在所述第二衬底的第一表面上的多个接触焊盘，其中，所述多个接触焊盘产生第三图案；至少一个第二组半导体裸片；以及第二包封层，所述第二包封层定位在所述至少一个第二半导体封装体周围；其中，所述第一和第二多个互连特征的所述图案中的至少一个图案与所述多个接触焊盘的所述第三图案匹配，从而使得所述第一或第二多个互连特征能够电连接至所述多个接触焊盘。
以上对技术的详细描述是出于展示和说明的目的呈现的。其并不旨在穷举或将技术限制为所公开的精确形式。鉴于以上的教导内容，许多修改和变体都是可能的。选择所描述的所述实施例是为了最佳地说明技术原理及其实际应用，从而由此使得本领域其他技术人员能够以不同的实施例和具有适合于所考虑到的实际用途的不同修改来最佳地利用所述技术。旨在使技术范围由所附权利要求来限定。

Claims (27)

1.一种半导体设备，包括：
第一半导体封装体，所述第一半导体封装体包括：
第一衬底，
第一组一个或多个半导体裸片，
再分布层，所述再分布层具有固定至所述再分布层的表面的多个焊球，以及
第一模制化合物，所述第一模制化合物包封所述第一半导体封装体的至少一部分，所述焊球的至少一部分延伸穿过所述第一模制化合物的表面；以及
一组一个或多个第二半导体封装体，包括：
至少一个第二衬底，包括在所述至少一个第二衬底的至少一个表面上的接触焊盘，
第二组一个或多个半导体裸片，以及
至少一个第二模制化合物，所述至少一个第二模制化合物包封所述至少一个第二半导体封装体的至少一部分；
延伸穿过所述第一模制化合物的所述表面的所述焊球的图案与所述至少一个第二衬底的所述至少一个表面上的所述接触焊盘的图案匹配，所述焊球固定至所述接触焊盘从而将所述第一半导体封装体耦合至所述一组一个或多个第二半导体封装体。
2.如权利要求1所述的半导体设备，其中，在所述一组一个或多个第二半导体封装体与主机设备之间传达的信号通过所述第一半导体封装体而发生。
3.如权利要求1所述的半导体设备，其中，所述第一半导体封装体中的所述第一组一个或多个半导体裸片具有与所述一组一个或多个第二半导体封装体中的所述第二组半导体裸片不同数量的半导体裸片。
4.如权利要求1所述的半导体设备，其中，所述第一封装体的功能与所述一组一个或多个第二半导体封装体的功能不同。
5.如权利要求1所述的半导体设备，其中，所述一组一个或多个第二半导体封装体包括安装至所述第一半导体封装体的表面的多个半导体封装体。
6.如权利要求5所述的半导体设备，其中，所述多个第二半导体封装体中的两个或更多个封装体具有相同的功能。
7.如权利要求5所述的半导体设备，其中，所述多个第二半导体封装体中的两个或更多个封装体具有彼此不同的功能。
8.如权利要求1所述的半导体设备，其中，所述第一半导体封装体中的所述一组一个或多个半导体裸片包括在所述第一衬底上堆叠成单个堆叠的多个半导体裸片。
9.如权利要求1所述的半导体设备，其中，所述第一半导体封装体中的所述一组一个或多个半导体裸片包括在所述第一衬底上堆叠成多个堆叠的多个半导体裸片。
10.一种半导体设备，包括：
第一组一个或多个第一半导体封装体，包括：
至少一个第一衬底，
第一组一个或多个第一半导体裸片，
再分布层，所述再分布层具有固定至所述再分布层的表面的多个焊球，以及
第一模制化合物，所述第一模制化合物包封所述第一组一个或多个第一半导体封装体中的至少一部分，所述焊球通过所述第一模制化合物的表面而暴露；以及
第二组一个或多个第二半导体封装体，包括：
至少一个第二衬底，包括在所述至少一个第二衬底的至少一个表面上的接触焊盘，
第二组一个或多个第二半导体裸片，以及
至少一个第二模制化合物，所述至少一个第二模制化合物包封所述第二组一个或多个第二半导体封装体中的至少一部分；
所述再分布层的所述焊球的图案与所述至少一个第二衬底上的所述接触焊盘的图案匹配，所述焊球固定至所述接触焊盘从而将所述第一组一个或多个第一半导体封装体耦合至所述第二组一个或多个第二半导体封装体。
11.如权利要求10所述的半导体设备，其中，所述第一组一个或多个第一半导体封装体具有与所述第二组一个或多个第二半导体封装体相同数量的半导体封装体。
12.如权利要求10所述的半导体设备，其中，所述第一组一个或多个第一半导体封装体具有与所述第二组一个或多个第二半导体封装体不同数量的半导体封装体。
13.如权利要求10所述的半导体设备，其中，所述第一组一个或多个第一半导体封装体具有与所述第二组一个或多个第二半导体封装体相比更多的半导体封装体。
14.如权利要求10所述的半导体设备，其中，所述第一组一个或多个第一半导体封装体具有与所述第二组一个或多个第二半导体封装体相比更少的半导体封装体。
15.如权利要求10所述的半导体设备，其中，所述第一组第一半导体封装体的功能与所述第二组一个或多个第二半导体封装体的功能不同。
16.如权利要求10所述的半导体设备，其中，所述第一组一个或多个第一半导体封装体包括多个第一半导体封装体。
17.如权利要求16所述的半导体设备，其中，所述多个第一半导体封装体中的两个或更多个封装体具有相同的功能。
18.如权利要求16所述的半导体设备，其中，所述多个第一半导体封装体中的两个或更多个封装体具有彼此不同的功能。
19.如权利要求10所述的半导体设备，其中，所述第二组一个或多个第二半导体封装体包括多个第二半导体封装体。
20.如权利要求19所述的半导体设备，其中，所述多个第二半导体封装体中的两个或更多个封装体具有相同的功能。
21.如权利要求19所述的半导体设备，其中，所述多个第二半导体封装体中的两个或更多个封装体具有彼此不同的功能。
22.一种半导体设备，包括：
第一组一个或多个第一半导体封装体，包括：
至少一个第一衬底装置，用于向半导体裸片传递信号和传递来自半导体裸片的信号，
安装在所述衬底装置上的第一组一个或多个第一半导体裸片，
再分布装置，用于将所述再分布装置上的多个接触焊盘电连接至多个焊接装置，所述多个焊接装置固定至所述再分布装置的表面，以及
第一包封装置，用于包封所述第一组一个或多个第一半导体封装体中的至少一部分，所述焊装置通过所述第一包封装置的表面而暴露；以及
第二组一个或多个第二半导体封装体，包括：
至少一个第二衬底装置，用于向半导体裸片传递信号和传递来自半导体裸片的信号，所述至少一个第二衬底装置包括在所述至少一个第二衬底的至少一个表面上的电连接器装置，
第二组一个或多个第二半导体裸片，以及
第二包封装置，所述第二包封装置包封所述第二组一个或多个第二半导体封装体中的至少一部分；
所述再分布装置的所述焊接装置的图案与所述至少一个第二衬底上的所述电连接器装置的图案匹配，所述焊接装置固定至所述电连接器装置从而将所述第一组一个或多个第一半导体封装体耦合至所述第二组一个或多个第二半导体封装体。
23.如权利要求22所述的半导体设备，其中，所述第一组一个或多个第一半导体封装体具有与所述第二组一个或多个第二半导体封装体相同数量的半导体封装体。
24.如权利要求22所述的半导体设备，其中，所述第一组一个或多个第一半导体封装体具有与所述第二组一个或多个第二半导体封装体不同数量的半导体封装体。
25.如权利要求22所述的半导体设备，其中，所述第一组一个或多个第一半导体封装体具有与所述第二组一个或多个第二半导体封装体相比更多的半导体封装体。
26.如权利要求22所述的半导体设备，其中，所述第一组一个或多个第一半导体封装体具有与所述第二组一个或多个第二半导体封装体相比更少的半导体封装体。
27.一种半导体设备，包括：
至少一个第一半导体封装体，包括：
第一衬底，所述第一衬底包括第一多个互连特征，其中，所述第一多个互连特征产生第一图案；
至少一个第一组半导体裸片，电连接至所述第一多个互连特征；
第一层，所述第一层连接至所述第一组半导体裸片，所述第一层具有固定至所述第一层的表面的第二多个互连特征，其中，所述第二多个互连特征电连接至所述第一组半导体裸片，进一步地，其中，所述第二多个互连特征产生第二图案；以及
包封层，所述包封层定位在所述第一半导体封装体周围，其中，所述第一多个互连特征通过所述第一包封层的表面而暴露；以及
至少一个第二半导体封装体，包括：
第二衬底，所述第二衬底包括在所述第二衬底的第一表面上的多个接触焊盘，其中，所述多个接触焊盘产生第三图案；
至少一个第二组半导体裸片；以及
第二包封层，所述第二包封层定位在所述至少一个第二半导体封装体周围；
其中，所述第一和第二多个互连特征的所述图案中的至少一个图案与所述多个接触焊盘的所述第三图案匹配，从而使得所述第一或第二多个互连特征能够电连接至所述多个接触焊盘。
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