CN104037142B - 封装对准结构及其形成方法 - Google Patents
封装对准结构及其形成方法 Download PDFInfo
- Publication number
- CN104037142B CN104037142B CN201310224396.3A CN201310224396A CN104037142B CN 104037142 B CN104037142 B CN 104037142B CN 201310224396 A CN201310224396 A CN 201310224396A CN 104037142 B CN104037142 B CN 104037142B
- Authority
- CN
- China
- Prior art keywords
- substrate
- aligning parts
- group
- top surface
- connecting part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 218
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 238000010992 reflux Methods 0.000 claims description 12
- 229920001223 polyethylene glycol Polymers 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 239000003822 epoxy resin Substances 0.000 claims description 6
- 229920000620 organic polymer Polymers 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 229920000647 polyepoxide Polymers 0.000 claims description 6
- 238000007493 shaping process Methods 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000002202 Polyethylene glycol Substances 0.000 claims description 5
- 229920001296 polysiloxane Polymers 0.000 claims description 5
- 125000000118 dimethyl group Chemical group [H]C([H])([H])* 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 229920005573 silicon-containing polymer Polymers 0.000 claims description 4
- 239000010426 asphalt Substances 0.000 claims 1
- 239000000463 material Substances 0.000 description 30
- 238000004806 packaging method and process Methods 0.000 description 11
- 230000009471 action Effects 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000000465 moulding Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005452 bending Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 241000218202 Coptis Species 0.000 description 2
- 235000002991 Coptis groenlandica Nutrition 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000004205 dimethyl polysiloxane Substances 0.000 description 2
- 235000013870 dimethyl polysiloxane Nutrition 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- CXQXSVUQTKDNFP-UHFFFAOYSA-N octamethyltrisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)O[Si](C)(C)C CXQXSVUQTKDNFP-UHFFFAOYSA-N 0.000 description 2
- 238000004987 plasma desorption mass spectroscopy Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 241000500881 Lepisma Species 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 210000000262 cochlear duct Anatomy 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- -1 poly dimethyl silicon Oxygen alkane Chemical class 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000003223 protective agent Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/10165—Alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8114—Guiding structures outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1076—Shape of the containers
- H01L2225/1082—Shape of the containers for improving alignment between containers, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本发明提供了封装对准结构及其形成方法,其中一个实施例是一种半导体器件,包括:第一接合焊盘,位于第一衬底上,第一接合焊盘的第一中心线穿过第一接合焊盘的中心且垂直于第一衬底的顶面;以及第一导电连接件,位于第二衬底上,第一导电连接件的第二中心线穿过第一导电连接件的中心且垂直于第二衬底的顶面,第二衬底位于第一衬底上方,其中第一衬底的顶面面向第二衬底的顶面。该半导体器件还包括:第一对准部件,与第一衬底上的第一接合焊盘相邻,第一对准部件被配置为使第一中心线与第二中心线对准。
Description
技术领域
本发明总的来说涉及半导体领域,更具体地,涉及封装对准结构及其形成方法。
背景技术
电子设备可被划分为包括诸如集成电路(IC)芯片、封装件、印刷电路板(PCB)的器件的简单层级和***。封装件是诸如计算机芯片的电子器件和PCB之间的接口。器件由诸如硅的半导体材料制成。使用引线接合(WB)、带式自动接合(TAB)或倒装芯片(FC)凸块组装技术将集成电路组装成诸如四方扁平封装(QFP)、管脚阵列(PGA)或球栅阵列(BGA)的封装件。然后,封装后的器件直接附接至印刷线路板或附接至另一类型的衬底,这被定义为第二级封装。
球栅阵列(BGA)封装技术通常是先进的半导体封装技术,其特征在于,在衬底的正面安装半导体芯片,并且以矩阵阵列(通常称为球栅阵列)形式将诸如焊球的多个导电元件配置在衬底的背面。球栅阵列允许半导体封装件接合并电连接至外部PCB或其他电子器件。BGA封装件可应用于诸如动态随机存取存储器等的存储器。
基本的倒装芯片(FC)封装技术包括IC、互连***和衬底。功能芯片连接至具有多个焊料凸块的衬底,其中焊料凸块形成芯片和衬底之间的金属互连。功能芯片、焊料凸块和衬底形成倒装芯片封装件。此外,多个焊球形成球栅阵列(BGA)。
引线接合可用于形成从诸如芯片电阻器或芯片电容器的芯片部件到衬底的电连接。两个功能芯片堆叠在多个衬底层的顶部。通过多条接合金线将芯片连接至衬底。也可使用诸如铝线的其他形式的引线。功能芯片、金线和衬底形成引线接合(WB)封装件。
发明内容
根据本发明的一个方面,提供了一种半导体器件,包括:第一接合焊盘,位于第一衬底上,第一接合焊盘的第一中心线穿过第一接合焊盘的中心且垂直于第一衬底的顶面;第一导电连接件,位于第二衬底上,第一导电连接件的第二中心线穿过第一导电连接件的中心且垂直于第二衬底的顶面,第二衬底位于第一衬底上方,并且第一衬底的顶面面向第二衬底的顶面;以及第一对准部件,与第一衬底上的第一接合焊盘相邻,第一对准部件被配置为使第一中心线与第二中心线对准。
优选地,对准部件具有凸形顶面。
优选地,第一对准部件具有凹形顶面。
优选地,第一对准部件包括光刻胶、环氧树脂、硅树脂、聚二甲基硅氧烷、有机聚合物、聚乙二醇或它们的组合。
优选地,该半导体器件还包括:第二接合焊盘,位于第一衬底上,第二接合焊盘的第三中心线穿过第二接合焊盘的中心且垂直于第一衬底的顶面,第二接合焊盘与第一对准部件相邻,第一对准部件横向位于第一接合焊盘和第二接合焊盘之间;以及第二导电连接件,位于第二衬底上,第二导电连接件的第四中心线穿过第二导电连接件的中心且垂直于第二衬底的顶面,第一对准部件进一步被配置为使第三中心线与第四中心线对准。
优选地,第一对准部件横向位于第一导电连接件和第二导电连接件之间。
优选地,该半导体器件还包括:第二对准部件,位于第二衬底上,第二对准部件位于第一对准部件上方并与第一对准部件接触。
优选地,第一对准部件和第二对准部件被配置为控制第一衬底的顶面和第二衬底的顶面之间的距离。
优选地,第一对准部件和第二对准部件具有凸形顶面。
优选地,第一对准部件具有凹形顶面,并且第二对准部件具有凸形顶面,第二对准部件的凸形顶面的顶点与第一对准部件的凹形顶面的最低点对准并与最低点接触。
根据本发明的另一方面,提供了一种半导体器件,包括:第一组接合焊盘,位于第一衬底的第一侧;第一组导电连接件,位于第二衬底的第一侧,第二衬底的第一侧面向第一衬底的第一侧,第一组导电连接件连接至第一组接合焊盘;第一组对准部件,位于第一衬底的第一侧,第一组对准部件中的每一个均与第一组接合焊盘中的至少一个相邻,第一组对准部件被配置为使第一组导电连接件对准于第一组接合焊盘;第二组导电连接件,位于第一衬底的第二侧,第二侧与第一衬底的第一侧相对;以及第二组对准部件,位于第三衬底的第一侧,第三衬底的第一侧面向第一衬底的第二侧,第二组对准部件中的每一个均与第二组导电连接件中的至少一个相邻,第二组对准部件被配置为使第二组导电连接件对准于第三衬底。
优选地,第一组对准部件和第二对准部件均具有凸形顶面。
优选地,该半导体器件还包括:第三组对准部件,位于第一衬底的第一侧,第三组对准部件中的每一个均小于第一组对准部件中的每一个;以及管芯,利用第三组导电连接件安装至第一衬底的第一侧,第三组对准部件中的每一个都与第三组导电连接件中的至少一个相邻,第三组对准部件被配置为使第三组导电连接件对准于第一衬底。
优选地,该半导体器件还包括:第四组对准部件,位于第二衬底的第一侧,第四组对准部件中的每一个都位于第一组对准部件中的一个上方且与这一个对准部件接触,第四组对准部件中的每一个均具有凸形顶面,并且第一组对准部件中的每一个均具有凹形顶面。
根据本发明的又一方面,提供了一种形成半导体器件的方法,包括:在第一衬底上形成第一接合焊盘;在第二衬底上形成第一导电连接件;在第一衬底上形成第一对准部件,第一对准部件与第一接合焊盘相邻;利用对准部件使第一衬底与第二衬底对准;以及将第一衬底接合至第二衬底,第一接合焊盘被接合至第一导电连接件。
优选地,形成第一对准部件还包括:在第一衬底上方沉积第一层,第一层具有基本平坦的顶面;图案化第一层以形成具有基本平坦表面的第一层的第一部分;以及使第一部分成形为具有非平坦的顶面。
优选地,第一层包括光刻胶、环氧树脂、硅树脂、聚二甲基硅氧烷、有机聚合物、聚乙二醇或它们的组合。
优选地,使第一部分成形还包括对第一部分执行回流工艺,在回流工艺之后第一部分具有凸形顶面。
优选地,使第一部分成形还包括:对第一部分执行回流工艺;以及在回流工艺过程中,将模具施加于第一部分,在施加模具之后第一部分具有凹形顶面。
优选地,该方法还包括:在第二衬底上形成第二对准部件,第二对准部件具有凸形顶面,并且第一对准部件具有凹形顶面,第二对准部件的凸形顶面的顶点与第一对准部件的凹形顶面的最低点对准且与最低点接触。
附图说明
为了更完整地理解本实施例及其优点,现在结合附图作为参考进行以下描述,其中:
图1示出了根据一个实施例的具有对准部件的半导体器件的截面图;
图2示出了根据另一个实施例的具有对准部件的另一个半导体器件的截面图;
图3示出了根据一个实施例的制造具有对准部件的半导体器件的方法的流程图;
图4A和图4B示出了根据一个实施例的形成对准部件的中间阶段;
图5A和图5B示出了根据一个实施例的使用对准部件形成半导体器件的中间阶段;
图6示出了根据另一个实施例的具有对准部件的另一个半导体器件的截面图;
图7A至图7C示出了根据另一个实施例的形成对准部件的中间阶段;以及
图8A和图8B示出了根据另一个实施例的使用对准部件形成半导体器件的中间阶段。
具体实施方式
现在将详细参考附图中示出的实施例。只要有可能,相同的参考标号用在附图和说明书中以表示相同或类似的元件。在附图中,为了清楚和方便可以夸大形状和厚度。根据本发明,具体地,本说明书将引导元件形成部分方法和装置或者与方法和装置直接组合。应该理解,没有具体示出或描述的元件可采取本领域技术人员公知的各种形式。一旦被告知本发明,则对本领域技术人员而言许多变更和修改将很明显。
本说明书中提到的“一个实施例”或“实施例”意思是至少一个实施例包括与实施例相关的所述具体特征、结构或特性。因此,在本说明书各处出现的短语“在一个实施例中”或“在实施例中”不一定全部是指同一实施例。而且,在一个或多个实施例中,可以用任何适合的方式来组合具体特征、结构或特性。应该明白,以下各图没有按比例绘制;相反,这些图仅用于说明。
将参照具体条件描述实施例,即用于叠层封装(POP)结构、倒装芯片结构、表面安装结构、三维集成电路(3DIC)封装件、二维半集成电路(2.5DIC)封装件等的对准和连接件形状控制部件。然而,其他实施例也可应用于对准和连接件形状控制很重要的其他结构。
现在参照图1,根据一个实施例示出了半导体器件10。半导体器件10可包括底部封装件200,顶部封装件300利用第二组导电接头210附接至底部封装件200,并且底部封装件200利用第一组导电接头110附接至第一衬底100。在一个实施例中,半导体器件的总厚度可在约0.9mm至约1.6mm之间。
顶部封装件300可包括连接至第三衬底302的诸如管芯350的一个或多个堆叠管芯。在所示实施例中,管芯350通过引线接合310连接至第三衬底302,虽然还可以使用接触凸块的其他连接。
管芯350可密封在第三衬底302的顶面上的模制料340中。模制料340可包括聚合物、模制底部填充物等或它们的组合。可通过注射模制料340围绕管芯350和引线接合310来形成模制料340。在其他实施例中,顶部封装件300和底部封装件200可封装在第一衬底100的顶面上的模制料中。
顶部封装件300可通过第三衬底302的底面上的多个接合焊盘330、导电接头210和第二衬底202的顶面上的接合焊盘230连接至底部封装件。
底部封装件200可包括:一个或多个管芯400,通过导电连接件410附接至第二衬底202的顶面和/或底面;第二组对准部件220,在第二衬底202上与第二组导电接头210横向相邻;第四组对准部件420,在第二衬底202上与导电连接件410横向相邻;以及底部填充物440,位于第二衬底202和管芯400之间。
在将顶部封装件300安装至底部封装件200的过程中,第二组对准部件220可用于使顶部封装件300上的导电接头210与第二衬底202上的接合焊盘230对准。对准部件220可具有凸形或圆形顶面。如以下进一步讨论的,对准部件220可使导电接头210与接合焊盘230(见图5A和图5B)自对准。对准部件220可包括光刻胶、环氧树脂、硅树脂(例如,聚二甲基硅氧烷(PDMS))或其他有机聚合物(诸如聚乙二醇(PEG))等或它们的组合。可以以块体沉积对准部件220,然后通过回流工艺、蚀刻、压模等或它们的组合来使其成形。
管芯400可包括集成电路或芯片,并且可通过导电连接件410安装至第二衬底202的顶面和/或底面。在所示实施例中,管芯400可安装至第二衬底202,其中导电连接件410是与第二衬底202上的接合焊盘430接触的接触凸块,接合焊盘430又电连接至顶部封装件300和/或第一衬底100。在另一个实施例中,可使用诸如表面安装的技术将管芯400安装至第二衬底202以将管芯400的管脚连接至第二衬底202上的管芯接合焊盘阵列。
第四组对准部件420可用于在安装管芯400的过程中使管芯400上的导电连接件410与接合焊盘430对准。第四组对准部件420可具有圆形或弯曲的顶面,并且可由与以上描述的第二组对准部件220类似的材料和工艺形成。尽管第二组对准部件220和第四组对准部件420不必具有相同材料或者通过相同的工艺形成。
可通过第二衬底202的底面上的多个接合焊盘230、导电连接件110、第一衬底100的顶面上的接合焊盘(未示出)和第一衬底100的顶面上的第一组对准部件120将底部封装件200连接至第一衬底100。
第一衬底100可具有位于第一衬底100的顶面上的接合焊盘(未示出)。在一个实施例中,第一衬底100可以是硅衬底、硅或玻璃中介片、PCB、有机层压衬底等。在一些实施例中,第一衬底100可包括形成在其上的电子部件和元件,或者在可选实施例中,第一衬底100可以不具有电子部件和元件。
第一组对准部件120可用于在将底部封装件200安装至第一衬底100过程中,使第二衬底202上的导电连接件110与第一衬底100上的接合焊盘(未示出)对准。在第一衬底100上没有接合焊盘来连接至导电连接件110的另一实施例中,对准部件120可用于使底部封装件200对准于第一衬底100上的特定位置。第一组对准部件120可具有圆形或弯曲的顶面,并且可由与以上描述的第二组对准部件220类似的材料和工艺形成。尽管第一、第二和第四组对准部件120、220和420不必具有相同材料或者通过相同工艺形成。
已发现实施例(诸如以上讨论的实施例)可在半导体器件的组装工艺过程中减少对工具、夹具、模具等的需要。对准部件所提供的自对准可减少需要确保使半导体器件的部件对准的组装成本和步骤。此外,由于对准部件可位于导电连接件之间,所以对准部件可有助于在回流工艺期间减少导电连接件之间的桥接。
图2示出了根据另一个实施例的半导体器件12。在本实施例中,半导体器件12包括位于第二衬底202的顶面上的第二组对准部件220以及位于第三衬底302的底面上的第三组对准部件320,其中对准部件320位于对准部件220上并与其接触。虽然图2中未示出,但是本实施例还可包括第一组对准部件120和第四组对准部件420(见图1)。可通过第二组对准部件220和第三组对准部件320的高度精确地控制第二衬底202和第三衬底302之间的高度250。在一个实施例中,高度250可基本等于第二组对准部件220顶点处的高度加上第三组对准部件320顶点处的高度。
对准部件220和320可具有圆形或弯曲的顶面,并且可由与以上描述的第二组对准部件220类似的材料和工艺形成。尽管第一、第二和第三组对准部件120、220和320不必具有相同材料或者通过相同工艺形成。
通过在底部封装件的顶面以及顶部封装件的底面上具有对准部件,可以更好地控制封装件之间的间隙(见高度250),并且可以提高封装件之间的导电连接件的形状的可靠性。
图3示出了根据一个实施例的制造半导体器件的方法500的流程图。虽然在下文中以一系列动作或事件示出并描述方法500,但是应该理解,所示的动作或事件的顺序不限于具体实施例。例如,一些动作可以以不同的顺序发生和/或与除本文示出和/或描述的动作之外的其他动作或事件同时发生。此外,不是所有示出的动作都被要求实施本发明描述中的一个或多个方面或实施例。而且,可在一个或多个独立的动作和/或阶段中执行本发明所述的一个或多个动作。
在步骤502中,在第一衬底20上形成接合焊盘22。在以下所述的图4中示出了步骤502。
现在参照图4,示出了第一衬底20,其中接合焊盘22位于第一衬底20的顶面,并且对准部件26与接合焊盘22相邻并位于第一衬底20的顶面。在一个实施例中,第一衬底20可以是硅衬底、硅或玻璃中介片、印刷电路板(PCB)、有机层压衬底等。在一些实施例中,第一衬底20可包括在其上形成的电子部件和元件,或者在可选实施例中,第一衬底20可以不具有电子部件和元件。
第一衬底20可包括金属层(未示出)。金属层可包括衬底通孔(TSV)连接第一衬底20上方和下方的器件和部件(例如,管芯、芯片、封装件等)来形成功能电路。金属层可由介电材料(例如,低k介电材料)和导电材料(例如,铜)的交替层形成,并且其可通过任何适合的工艺(诸如沉积、镶嵌、双镶嵌等)形成。金属层和介电层可包括金属线和通孔以电连接器件和部件。在图中仅示出第一衬底20的一部分,因为它足以充分描述示例性实施例。
接合焊盘22可包括诸如铝、铜、金、镍等或它们的组合的导电材料。在一些实施例中,有机可焊保护剂(OSP)可施加于接合焊盘22。在其他实施例中,可使用化学镀镍化学镀钯与浸金技术(ENEPIG)形成接合焊盘22。
在步骤504中,可在第一衬底的顶面上沉积并图案化对准材料24。如以下所述,图4A示出了步骤504。
对准材料24可包括光刻胶、环氧树脂、硅树脂(例如,PDMS)或其他有机聚合物(诸如PEG)等或它们的组合。可以以块体或其他适合方法沉积对准材料24。可通过蚀刻或其他适合方法图案化对准材料24以与接合焊盘22相邻。在一个实施例中,对准材料24可具有与第一衬底20的主面基本平行的顶面。
在步骤506中,对准部件26由对准材料24形成。如以下所述,图4B示出了步骤506。
对准部件26可成形为具有圆形或弯曲的顶面。在一个实施例中,可通过在约160℃至约200℃的温度条件下,对对准材料执行持续约8分钟至12分钟的回流工艺来使对准部件26成形。在另一个实施例中,可通过蚀刻、模制(见以下讨论的图7A至图7C)或其他适合方法来使对准部件26成形。如以下所讨论的,对准部件26的凸形顶面26A可朝接合焊盘22的方向引导导电连接件32(见图5A和图5B)。对准部件26的边缘可与接合焊盘22的边缘对准,对准部件26可与接合焊盘22部分重叠,或者对准部件26可与接合焊盘22横向隔开。
在步骤508中,在第二衬底30上形成导电连接件32。在步骤510中,对准第一衬底20与第二衬底30。如以下所述,图5A示出了步骤508和510。
图5A示出了具有两个接合焊盘22和与接合焊盘22相邻的三个对准部件26的第一衬底20。一个对准部件26位于接合焊盘22之间,而其他两个对准部件均与接合焊盘22的外缘相邻。每个导电连接件32的中心线32C均垂直于第二衬底30的顶面且穿过导电连接件32的中心,并且每个接合焊盘22的中心线22C均垂直于第一衬底20的顶面且穿过接合焊盘22的中心。导电连接件32可以是焊球、微凸块、可控坍塌芯片连接(C4)凸块等,并且可包括诸如锡、银、无铅锡、铜等或它们的组合的材料。
在第二衬底上形成导电连接件32之后,第二衬底30可与第一衬底20对准以使衬底接合在一起。在一个实施例中,第二衬底30可朝着第一衬底20降低直到导电连接件32接触对准部件26。如图5B所示,对准部件26的凸形顶面和导电连接件32的凸形顶面使得导电连接件32的中心线32C朝接合焊盘22的中心线22C自对准。
在步骤512中,第一衬底20接合至第二衬底30。如以下所述,图5B示出了步骤512。
图5B示出了在导电连接件32与接合焊盘22对准之后的导电连接件32。然后,可通过例如回流工艺将导电连接件32接合至接合焊盘22。接合将使导电连接件32与接合焊盘22电连接和物理连接。虽然图4A至图5B示出了对准部件26位于每个接合焊盘22的两侧,但是可有更多的对准部件26与每个接合焊盘22相邻,例如,在棋盘状图案中,每个接合焊盘22均可被接合焊盘22四侧的四个对准部件26围绕。在其他实施例中,如图2所示,对准部件可位于第一衬底20和第二衬底30两者上。
图6示出了根据另一个实施例的半导体器件14。在本实施例中,半导体器件14包括位于第二衬底202的顶面上的第二组凹形对准部件222以及位于第三衬底302的底面上的第三组对准部件320,其中,对准部件320具有凸形或圆形形状,并且位于凹形对准部件222上方且与其接触。虽然图6未示出,但该实施例还可包括第一组对准部件120和第四组对准部件420(见图1)。第二衬底202和第三衬底302之间的高度250可由第二组凹形对准部件222和第三组对准部件320的高度精确地控制。在一个实施例中,高度250可基本等于第二组凹形对准部件222的凹形表面的最低点处的高度加上第三组对准部件320的顶点处的高度。
通过底部封装件的顶面上的凹形对准部件和顶部封装件的底面上的凸形或圆形对准部件,可控制封装件之间的间隙(见高度250),并且顶部和底部封装件还可自对准。本实施所提供的自对准可减少需要确保使半导体器件的部件对准的组装成本和步骤,同时还允许更多的控制以及顶部和底部封装件之间潜在更大的高度250。而且,由于对准部件位于导电连接件之间,所以在回流工艺过程中,对准部件可有助于减少导电连接件之间的桥接。
图7A至图7C示出了根据一个实施例的形成凹形对准部件的方法。之前已参照图4描述了第一衬底20和对准材料24,因此这里将不再重复。第一衬底20可进一步包括一个或多个与对准材料24(见图4A)相邻的接合焊盘。具有模具42的模制基底40位于第一衬底20和对准材料24上方。模制基底40和模具42可包括金属或适合于模制工艺的压力和温度的任何材料。在一个实施例中,如图7A所示,模具42可具有凸形或圆形表面。在另一个实施例中,模具42的表面可以是三角形、正方形、其他多边形等。
图7B示出了形成凹形对准部件28的模制工艺。对准材料24可成形为具有凹形顶面。在一个实施例中,可通过对对准材料24执行回流工艺同时降低模具42以接触并成形对准材料24来使对准材料24成形。模具42的凸形表面转印至对准部件28的顶面从而使对准部件28具有凹形顶面28A。可在约160℃至约200℃的温度条件下执行回流工艺约8分钟至12分钟。在另一个实施例中,可通过蚀刻或其他适合方法使凹形对准部件28成形。如以下所讨论的,对准部件28的凹形顶面28A可朝凹形对准部件28的中心方向引导对准部件44(见图8A和图8B)。凹形对准部件28的边缘可与相邻的接合焊盘(未示出)的边缘对准,凹形对准部件28可与相邻的接合焊盘部分重叠,或者凹形对准部件28可与相邻的接合焊盘横向分隔开。
图7C示出了在移除模具42之后的凹形对准部件28。凹形对准部件28的顶面可具有从模具42的圆形表面转印的凹形顶面。
图8A和图8B示出了第一衬底20与第二衬底30对准。在本实施例中,第二衬底30上的凸形对准部件44的中心线44C与第一衬底上的凹形对准部件28的中心线28C基本对准(见图8B)。第二衬底30与第一衬底20的对准可使衬底接合在一起。在一个实施例中,第二衬底30可朝第一衬底20的方向降低直到凸形对准部件44接触凹形对准部件28。凸形对准部件44的凸形顶面和凹形对准部件28的凹形顶面使得凸形对准部件44的中心线44C朝凹形对准部件28的中心线28C自对准。在一个实施例中,凸形对准部件44的凸形顶面的顶点与凹形对准部件28的凹形顶面的最低点对准且与其接触。通过使对准部件44和28自对准,第一衬底20和第二衬底30上的连接件和接合焊盘(例如,图6中的导电接头210和接合焊盘230)也可自对准。
本发明的一个实施例是一种半导体器件,其包括:第一接合焊盘,位于第一衬底上,第一接合焊盘的第一中心线穿过第一接合焊盘的中心且垂直于第一衬底的顶面;以及第一导电连接件,位于第二衬底上,第一导电连接件的第二中心线穿过第一导电连接件的中心且垂直于第二衬底的顶面,第二衬底位于第一衬底上方,并且第一衬底的顶面面向第二衬底的顶面。该半导体器件还包括:第一对准部件,与第一衬底上的第一接合焊盘相邻,第一对准部件配置为使第一中心线与第二中心线对准。
本发明的另一个实施例是一种半导体器件,其包括:第一组接合焊盘,位于第一衬底的第一侧;第一组导电连接件,位于第二衬底的第一侧,第二衬底的第一侧面向第一衬底的第一侧,第一组导电连接件连接至第一组接合焊盘;以及第一组对准部件,位于第一衬底的第一侧,第一组对准部件中的每一个均与第一组接合焊盘中的至少一个相邻,第一组对准部件被配置为使第一组导电连接件对准于第一组接合焊盘。该半导体器件还包括:第二组导电连接件,位于第一衬底的第二侧,第二侧与第一衬底的第一侧相对;以及第二组对准部件,位于第三衬底的第一侧,第三衬底的第一侧面向第一衬底的第二侧,第二组对准部件中的每一个均与第二组导电连接件中的至少一个相邻,第二组对准部件配置为使第二组导电连接件对准于第三衬底。
本发明的又一个实施例是一种形成半导体器件的方法,该方法包括:在第一衬底上形成第一接合焊盘;在第二衬底上形成第一导电连接件;以及在第一衬底上形成第一对准部件,第一对准部件与第一接合焊盘相邻。该方法还包括:用对准部件使第一衬底对准于第二衬底;对准部件使第一导电连接件对准于第一接合焊盘;以及将第一衬底接合至第二衬底,第一接合焊盘被接合至第一导电连接件。
虽然已详细描述了本实施例及其优点,但是应该理解可进行各种改变、替换和变更而不背离所附权利要求限定的本发明的精神和范围。而且,本申请的范围不旨在限于本说明书中描述的工艺、机械装置、制造、物质组成、工具、方法和步骤的具体实施例。正如本领域技术人员很容易从本发明可知,根据本发明可以使用与本文描述的对应实施例执行基本相同的功能或实现基本的相同结果的目前现有或即将开发的工艺、机械装置、制造、物质组成、工具、方法或步骤。因此,所附权利要求旨在将这种工艺、机械装置、制造、物质组成、工具、方法或步骤包括在其保护范围内。
Claims (15)
1.一种半导体器件,包括:
第一接合焊盘,位于第一衬底上,所述第一接合焊盘的第一中心线穿过所述第一接合焊盘的中心且垂直于所述第一衬底的顶面;
第一导电连接件,位于第二衬底上,所述第一导电连接件的第二中心线穿过所述第一导电连接件的中心且垂直于所述第二衬底的顶面,所述第二衬底位于所述第一衬底上方,并且所述第一衬底的顶面面向所述第二衬底的顶面;以及
第一对准部件,与所述第一衬底的顶面上的所述第一接合焊盘相邻,所述第一对准部件具有凸形顶面,所述第一对准部件与所述第一衬底的顶面直接接触,并且所述第一对准部件与所述第一导电连接件的侧壁直接接触,所述第一对准部件被配置为使所述第一中心线与所述第二中心线对准;
第二对准部件,位于所述第二衬底上,所述第二对准部件位于所述第一对准部件上方并与所述第一对准部件接触,所述第二对准部件具有凸形顶面并且所述第二对准部件与所述第一导电连接件的侧壁直接接触,其中,所述第二对准部件的凸形顶面与所述第一对准部件的凸形顶面直接接触。
2.根据权利要求1所述的半导体器件,其中,所述第一对准部件包括有机聚合物。
3.根据权利要求1所述的半导体器件,还包括:
第二接合焊盘,位于所述第一衬底上,所述第二接合焊盘的第三中心线穿过所述第二接合焊盘的中心且垂直于所述第一衬底的顶面,所述第二接合焊盘与所述第一对准部件相邻,所述第一对准部件横向位于所述第一接合焊盘和所述第二接合焊盘之间;以及
第二导电连接件,位于所述第二衬底上,所述第二导电连接件的第四中心线穿过所述第二导电连接件的中心且垂直于所述第二衬底的顶面,所述第一对准部件进一步被配置为使所述第三中心线与所述第四中心线对准。
4.根据权利要求3所述的半导体器件,其中,所述第一对准部件横向位于所述第一导电连接件和所述第二导电连接件之间。
5.根据权利要求1所述的半导体器件,其中,所述第一对准部件和所述第二对准部件被配置为控制所述第一衬底的顶面和所述第二衬底的顶面之间的距离。
6.根据权利要求1或2所述的半导体器件,其中,所述第一对准部件包括光刻胶、环氧树脂、硅树脂、聚二甲基硅氧烷、聚乙二醇或它们的组合。
7.一种半导体器件,包括:
第一组接合焊盘,位于第一衬底的第一侧;
第一组导电连接件,位于第二衬底的第一侧,所述第二衬底的第一侧面向所述第一衬底的第一侧,所述第一组导电连接件连接至所述第一组接合焊盘;
第一组对准部件,位于所述第一衬底的第一侧,所述第一组对准部件中的每一个均与所述第一组接合焊盘中的至少一个相邻,所述第一组对准部件中的每一个均具有凹形顶面,所述第一组对准部件与所述第一衬底的第一侧直接接触,并且所述第一组对准部件的每一个与所述第一组导电连接件的至少一个的侧壁直接接触,所述第一组对准部件被配置为使第一组导电连接件对准于所述第一组接合焊盘;
第二组导电连接件,位于所述第一衬底的第二侧,所述第二侧与所述第一衬底的第一侧相对;以及
第二组对准部件,位于第三衬底的第一侧,所述第三衬底的第一侧面向所述第一衬底的第二侧,所述第二组对准部件中的每一个均与所述第二组导电连接件中的至少一个相邻,所述第二组对准部件被配置为使所述第二组导电连接件对准于所述第三衬底;
第四组对准部件,位于所述第二衬底的第一侧,并且所述第四组对准部件中的每一个均具有凸形顶面,所述第四组对准部件中的每一个都位于所述第一组对准部件中的一个上方并且与所述第一组导电连接件的至少一个的侧壁直接接触,并且所述第四组对准部件中的每一个的凸形顶面的顶点与所述第一组对准部件中的一个的凹形顶面的最低点对准且与所述最低点接触。
8.根据权利要求7所述的半导体器件,其中,所述第二组对准部件具有凸形顶面。
9.根据权利要求7所述的半导体器件,还包括:
第三组对准部件,位于所述第一衬底的第一侧,所述第三组对准部件中的每一个均小于所述第一组对准部件中的每一个;以及
管芯,利用第三组导电连接件安装至所述第一衬底的第一侧,所述第三组对准部件中的每一个都与所述第三组导电连接件中的至少一个相邻,所述第三组对准部件被配置为使所述第三组导电连接件对准于所述第一衬底。
10.一种形成半导体器件的方法,所述方法包括:
在第一衬底上形成第一接合焊盘;
在第二衬底上形成第一导电连接件;
在所述第一衬底上形成第一对准部件,所述第一对准部件与所述第一接合焊盘相邻;
利用所述第一对准部件使所述第一衬底与所述第二衬底对准;以及
将所述第一衬底接合至所述第二衬底,所述第一接合焊盘被接合至所述第一导电连接件;
在所述第二衬底上形成第二对准部件,所述第二对准部件具有凸形顶面,并且所述第一对准部件具有凹形顶面,所述第二对准部件的凸形顶面的顶点与所述第一对准部件的凹形顶面的最低点对准且与所述最低点接触;
其中,所述第一对准部件与所述第一衬底的顶面直接接触,所述第一对准部件与所述第一导电连接件的侧壁直接接触,并且所述第二对准部件与所述第一导电连接件的侧壁直接接触。
11.根据权利要求10所述的方法,其中,形成所述第一对准部件还包括:
在所述第一衬底上方沉积第一层,所述第一层具有基本平坦的顶面;
图案化所述第一层以形成具有基本平坦表面的所述第一层的第一部分;以及
使所述第一部分成形为具有非平坦的顶面。
12.根据权利要求11所述的方法,其中,所述第一层包括有机聚合物。
13.根据权利要求11所述的方法,其中,使所述第一部分成形还包括对所述第一部分执行回流工艺,在所述回流工艺之后所述第一部分具有凸形顶面。
14.根据权利要求11所述的方法,其中,使所述第一部分成形还包括:
对所述第一部分执行回流工艺;以及
在所述回流工艺过程中,将模具施加于所述第一部分,在施加所述模具之后所述第一部分具有凹形顶面。
15.根据权利要求11或12所述的方法,其中,所述第一层包括光刻胶、环氧树脂、硅树脂、聚二甲基硅氧烷、聚乙二醇或它们的组合。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/787,630 | 2013-03-06 | ||
US13/787,630 US9627325B2 (en) | 2013-03-06 | 2013-03-06 | Package alignment structure and method of forming same |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104037142A CN104037142A (zh) | 2014-09-10 |
CN104037142B true CN104037142B (zh) | 2017-04-12 |
Family
ID=51467861
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310224396.3A Active CN104037142B (zh) | 2013-03-06 | 2013-06-06 | 封装对准结构及其形成方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9627325B2 (zh) |
KR (1) | KR101522770B1 (zh) |
CN (1) | CN104037142B (zh) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI597809B (zh) * | 2015-03-23 | 2017-09-01 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
JP6478853B2 (ja) * | 2015-07-14 | 2019-03-06 | 新光電気工業株式会社 | 電子部品装置及びその製造方法 |
KR102457119B1 (ko) | 2015-09-14 | 2022-10-24 | 삼성전자주식회사 | 반도체 패키지의 제조 방법 |
US10451863B2 (en) * | 2016-08-05 | 2019-10-22 | Verily Life Sciences Llc | Interposer for integration of multiple image sensors |
US10879260B2 (en) * | 2019-02-28 | 2020-12-29 | Sandisk Technologies Llc | Bonded assembly of a support die and plural memory dies containing laterally shifted vertical interconnections and methods for making the same |
US11538778B2 (en) * | 2020-12-18 | 2022-12-27 | Advanced Semiconductor Engineering, Inc. | Semiconductor package including alignment material and method for manufacturing semiconductor package |
US11916004B2 (en) * | 2021-09-03 | 2024-02-27 | Advanced Semiconductor Engineering, Inc. | Electronic device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1397092A (zh) * | 2000-02-02 | 2003-02-12 | 康宁股份有限公司 | 用倾斜壁基座进行的被动对齐 |
CN102142402A (zh) * | 2010-02-02 | 2011-08-03 | 力成科技股份有限公司 | 维持焊接定位的覆晶封装构造 |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004265888A (ja) * | 2003-01-16 | 2004-09-24 | Sony Corp | 半導体装置及びその製造方法 |
US6821878B2 (en) * | 2003-02-27 | 2004-11-23 | Freescale Semiconductor, Inc. | Area-array device assembly with pre-applied underfill layers on printed wiring board |
JP2005311250A (ja) | 2004-03-26 | 2005-11-04 | Optrex Corp | 半導体チップの実装構造 |
TWI230989B (en) * | 2004-05-05 | 2005-04-11 | Megic Corp | Chip bonding method |
US20060278979A1 (en) | 2005-06-09 | 2006-12-14 | Intel Corporation | Die stacking recessed pad wafer design |
US7382057B2 (en) * | 2006-03-29 | 2008-06-03 | Phoenix Precision Technology Corporation | Surface structure of flip chip substrate |
JP5042591B2 (ja) * | 2006-10-27 | 2012-10-03 | 新光電気工業株式会社 | 半導体パッケージおよび積層型半導体パッケージ |
US7982297B1 (en) * | 2007-03-06 | 2011-07-19 | Amkor Technology, Inc. | Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same |
KR101329355B1 (ko) * | 2007-08-31 | 2013-11-20 | 삼성전자주식회사 | 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치 |
US9136259B2 (en) | 2008-04-11 | 2015-09-15 | Micron Technology, Inc. | Method of creating alignment/centering guides for small diameter, high density through-wafer via die stacking |
US20110024899A1 (en) * | 2009-07-28 | 2011-02-03 | Kenji Masumoto | Substrate structure for cavity package |
US8461036B2 (en) * | 2009-12-22 | 2013-06-11 | Intel Corporation | Multiple surface finishes for microelectronic package substrates |
KR20110085481A (ko) * | 2010-01-20 | 2011-07-27 | 삼성전자주식회사 | 적층 반도체 패키지 |
US20110186899A1 (en) | 2010-02-03 | 2011-08-04 | Polymer Vision Limited | Semiconductor device with a variable integrated circuit chip bump pitch |
KR101667656B1 (ko) * | 2010-03-24 | 2016-10-20 | 삼성전자주식회사 | 패키지-온-패키지 형성방법 |
US8482111B2 (en) * | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
US8415792B2 (en) * | 2010-08-04 | 2013-04-09 | International Business Machines Corporation | Electrical contact alignment posts |
KR101677739B1 (ko) | 2010-09-29 | 2016-11-21 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조방법 |
KR101828386B1 (ko) * | 2011-02-15 | 2018-02-13 | 삼성전자주식회사 | 스택 패키지 및 그의 제조 방법 |
US8936967B2 (en) * | 2011-03-23 | 2015-01-20 | Intel Corporation | Solder in cavity interconnection structures |
US8569167B2 (en) * | 2011-03-29 | 2013-10-29 | Micron Technology, Inc. | Methods for forming a semiconductor structure |
US20120267782A1 (en) * | 2011-04-25 | 2012-10-25 | Yung-Hsiang Chen | Package-on-package semiconductor device |
KR101852601B1 (ko) * | 2011-05-31 | 2018-04-27 | 삼성전자주식회사 | 반도체 패키지 장치 |
JP5803014B2 (ja) * | 2011-06-28 | 2015-11-04 | 新光電気工業株式会社 | 半導体装置の製造方法 |
US20130113118A1 (en) * | 2011-11-04 | 2013-05-09 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Sloped Surface in Patterning Layer to Separate Bumps of Semiconductor Die from Patterning Layer |
US8658464B2 (en) * | 2011-11-16 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mold chase design for package-on-package applications |
US8823180B2 (en) * | 2011-12-28 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US9502360B2 (en) * | 2012-01-11 | 2016-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress compensation layer for 3D packaging |
US8907469B2 (en) * | 2012-01-19 | 2014-12-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package assembly and method of forming the same |
KR101874803B1 (ko) * | 2012-01-20 | 2018-08-03 | 삼성전자주식회사 | 패키지 온 패키지 구조체 |
US8749043B2 (en) * | 2012-03-01 | 2014-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package structure |
US8642384B2 (en) * | 2012-03-09 | 2014-02-04 | Stats Chippac, Ltd. | Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability |
US8963311B2 (en) * | 2012-09-26 | 2015-02-24 | Apple Inc. | PoP structure with electrically insulating material between packages |
US9659891B2 (en) * | 2013-09-09 | 2017-05-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having a boundary structure, a package on package structure, and a method of making |
-
2013
- 2013-03-06 US US13/787,630 patent/US9627325B2/en active Active
- 2013-06-06 CN CN201310224396.3A patent/CN104037142B/zh active Active
- 2013-06-20 KR KR1020130070992A patent/KR101522770B1/ko active IP Right Grant
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1397092A (zh) * | 2000-02-02 | 2003-02-12 | 康宁股份有限公司 | 用倾斜壁基座进行的被动对齐 |
CN102142402A (zh) * | 2010-02-02 | 2011-08-03 | 力成科技股份有限公司 | 维持焊接定位的覆晶封装构造 |
Also Published As
Publication number | Publication date |
---|---|
CN104037142A (zh) | 2014-09-10 |
US9627325B2 (en) | 2017-04-18 |
KR20140109779A (ko) | 2014-09-16 |
KR101522770B1 (ko) | 2015-05-26 |
US20140252657A1 (en) | 2014-09-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104037142B (zh) | 封装对准结构及其形成方法 | |
TWI588949B (zh) | 具有整合式承載表面的微電子封裝 | |
KR101536045B1 (ko) | 팬 아웃 웨이퍼 레벨 패키지 구조 | |
CN101252096B (zh) | 芯片封装结构以及其制作方法 | |
CN102903691B (zh) | 半导体器件、封装方法和结构 | |
KR101750713B1 (ko) | 마이크로스프링 접점을 갖는 인터포저 및 그 제조 및 사용 방법 | |
TWI647790B (zh) | 以聚合物部件爲主的互連體 | |
KR20150012285A (ko) | 와이어 본드 상호연결을 이용하여 기판 없이 적층가능한 패키지 | |
CN109003963B (zh) | 半导体封装及制造其的方法 | |
CN103117279A (zh) | 形成芯片在晶圆的总成的方法 | |
EP3168864A1 (en) | Packaged devices with multiple planes of embedded electronic devices | |
US20160189983A1 (en) | Method and structure for fan-out wafer level packaging | |
US10297552B2 (en) | Semiconductor device with embedded semiconductor die and substrate-to-substrate interconnects | |
KR102223245B1 (ko) | 패키징된 반도체 디바이스 | |
US9324633B2 (en) | Multi-level package assembly having conductive vias coupled to chip carrier for each level and method for manufacturing the same | |
CN104659000B (zh) | 具有球焊盘的基板、半导体封装体以及制造方法 | |
CN108962871A (zh) | 半导体装置封装 | |
US10734345B2 (en) | Packaging through pre-formed metal pins | |
TW201517187A (zh) | 具有嵌入在延伸基板和底部基板之間的半導體晶粒的半導體裝置 | |
US20120306064A1 (en) | Chip package | |
KR20160045609A (ko) | 반도체 패키지 및 그 제조 방법 | |
KR102050011B1 (ko) | 반도체 패키지용 상호 연결 구조체 및 상호 연결 구조체의 제조 방법 | |
CN105225975B (zh) | 封装结构及其制法 | |
US8988893B2 (en) | Method for electrical connection between elements of a three-dimensional integrated structure and corresponding device | |
CN106876340B (zh) | 半导体封装结构及其制作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |