CN103996662B - 半导体装置 - Google Patents
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Abstract
本发明公开一种半导体装置,该装置具有引线,该引线与树脂外壳一体成型而被设置于树脂外壳内。该半导体装置可防止水分从引线与树脂外壳之间的间隙渗入,由此提高半导体装置的可靠性。半导体装置(10)具有:树脂外壳(13),具有安装有绝缘电路基板(12)的底面部(13a)以及侧面部(13b);引线(14),与树脂外壳(13)成型为一体,以位于树脂外壳(13)内的底面部(13a)的表面的方式被设置于绝缘电路基板(12)的周围,并让一部分从树脂外壳(13)内延伸向外;封固树脂(17),填充于树脂外壳(13)内。其中,沿着树脂外壳(13)内的底面部(13a)的外周边缘而在引线(14)的两侧形成有凹部(18)。
Description
技术领域
本发明涉及一种半导体装置,尤其涉及一种在用于收容半导体器件的树脂外壳内将引线与该树脂外壳一体化设置的、可靠性得到提高的半导体装置。
背景技术
作为控制马达等的半导体装置,已知有将绝缘栅双极型晶体管(IGBT:InsulatedGate Bipolar Transistor)及续流二极管(FWD:Free Wheeling Diode)等多个功率半导体器件收容于树脂外壳中的半导体模块。
在该半导体模块的一例中,通过焊接而将功率半导体器件电连接于由绝缘电路基板表面的导电层形成的电路,并通过传递模塑而将引线与树脂外壳一体化地设置于树脂外壳内。该引线的一部分通过树脂外壳的侧面部而延伸到树脂外壳之外,并与外部端子连接。收容于树脂外壳内的绝缘电路基板的电路、功率半导体器件在树脂外壳内通过焊线而与引线电连接。另外,向已利用焊线布线的树脂外壳内注入封固树脂,以借助于该封固树脂而防止水分等渗入到树脂外壳内,从而将功率半导体器件等保护起来。
树脂外壳由聚苯硫醚树脂(PPS树脂)、聚对苯二甲酸丁二醇酯树脂(PBT树脂)、聚酰胺树脂(PA树脂)或者丙烯腈-丁二烯-苯乙烯共聚物树脂(ABS树脂)等构成,引线为铜等导电性薄板或者是对其进行了金属镀覆而形成之物。使树脂外壳的材料与引线材料密接并不容易。因此,对于通过传递模塑而与树脂外壳一体成型的引线而言,该引线与该树脂外壳之间有时会产生微小的间隙。如果这一间隙沿着从树脂外壳内侧延伸到外侧的引线形成,则存在水分从外部渗入到树脂外壳内的隐患,从而导致半导体模块的可靠性降低。
另外,由于使树脂外壳与引线密接并不容易,因此如果引线与树脂外壳之间产生了微小间隙,则在借助于超声波仪器而将焊线接合于该引线之时,难以实现良好的接合。
作为现有技术中的树脂密封型半导体装置,有一种半导体装置,其中为了防止水分从绝缘树脂封装与金属支撑板界面上的间隙渗入而在金属支撑板上形成环状沟槽部,并且,该环状沟槽部的入口具有短于底边部的形状(专利文献1)。另外,有一种半导体装置,其中为了提高引线框架与封固树脂之间的密着性,如形成不规则结晶之类地在引线框架表面上设置了镀银被覆膜(专利文献2)。而且,还有一种半导体装置,是利用从设置于树脂外壳的内部端子的侧面一直到上表面与树脂外壳一体化成型的突起部来夹持以固定该内部端子,从而提高了接合时的可靠性(专利文献3)。
记载于专利文献1的半导体装置是用来提高搭载有半导体器件的金属支撑板与绝缘树脂封装之间界面的密着性,而不是用于防止水分从一体设置于树脂外壳的引线与该树脂外壳之间的间隙渗入。而且,即使如专利文献2中记载的那样对引线框架的表面进行粗糙化镀覆,要防止水分从一体设置于树脂外壳的引线与该树脂外壳之间的间隙渗入并提高引线与树脂外壳之间的密着性也还困难。并且,对于记载于专利文献3的半导体装置而言,防止水分从一体成型于树脂外壳的引线与该树脂外壳之间的间隙渗入并非易事。
专利文献
专利文献1:日本特开2000-236048号公报
专利文献2:日本特开2010-199166号公报
专利文献3:日本特开2000-332179号公报
发明内容
本发明可有效地解决上述技术问题,其目的在于提供一种引线与树脂外壳一体成型并设置于树脂外壳内的半导体装置,尤其是其中可通过防止水分从引线与树脂外壳之间的间隙渗入而提高半导体装置的可靠性的半导体装置。
为了达到上述目的,提供如下的半导体装置。
该半导体装置,具有:绝缘电路基板,搭载有至少一个半导体器件;树脂外壳,具有安装有该绝缘电路基板的底面部以及围绕该底面部周围的侧面部;引线,与该树脂外壳成型为一体,以位于该树脂外壳内的底面部的表面的方式被设置于该绝缘电路基板的周围,并且将一部分从该树脂外壳内延伸到树脂外壳之外;封固树脂,填充于所述树脂外壳内,其中,沿着所述树脂外壳内的底面部的外周边缘而在所述引线的两侧形成有凹部。
该半导体装置的另一种形态为,具有:绝缘电路基板,搭载有至少一个半导体器件;树脂外壳,具有安装有该绝缘电路基板的底面部以及围绕在该底面部周围的侧面部;引线,与该树脂外壳成型为一体,以位于与该树脂外壳内的底面部的表面相同的平面上被设置于该绝缘电路基板的周围,并且将一部分从该树脂外壳内延伸到树脂外壳之外;封固树脂,填充于该树脂外壳内,其中,沿着该树脂外壳内的底面部的外周边缘而在该引线的两侧形成凹部,而且,在与该凹部所在处不同的位置上设置有该引线的固定部件。
根据本发明,沿着树脂外壳内的底面部的外周边缘而在引线的两侧形成有凹部,因此可通过向该凹部充入封固树脂而提高树脂外壳与封固树脂之间的密着性。据此,可防止水分通过引线与树脂外壳之间的间隙而从树脂外壳的外部渗入到内部,进而可提高半导体装置的可靠性。
附图说明
图1为本发明的半导体装置的一种实施方式的俯视图。
图2为沿着图1的II-II线剖切的剖面图。
图3为用于图1的半导体装置的树脂外壳与引线框架的俯视图。
图4为固定部件的说明图。
图5为固定部件的另一例的说明图。
图6为图1的VI部分的放大图。
图7为图1的VII部分的放大图。
图8为引线的示意性剖面图。
图9为引线及其周围的示意性剖面图。
符号说明:
具体实施方式
使用附图具体说明本发明的半导体装置的实施方式。
对于本发明的一种实施方式的半导体装置10,在图1中以俯视图表示,并在图2中以沿着图1的II-II线剖切的剖面图表示。本发明的一种实施方式的半导体装置10是一种作为功率半导体模块而构成的要素,有多个半导体器件11A、11B搭载于绝缘电路基板12上。半导体器件11A、11B分别为绝缘栅双极型晶体管(IGBT:Insulated Gate BipolarTransistor)和续流二极管(FWD:Free Wheeling Diode)。
如图2的剖面图所示,绝缘电路基板12是由绝缘层12a、以及分别形成于绝缘层12a的一侧面和另一侧面的导体层12b、12c构成。半导体器件11A、11B通过焊接而电连接于形成有电路图案的导体层12b,从而作为逆变器电路的主电路而例如构成U相、V相、W相各自的上桥臂和下桥臂。
搭载有半导体器件11A、11B的绝缘电路基板12被收容于树脂外壳13中。树脂外壳13内设置有引线14。半导体器件11A、11B以及绝缘电路基板12的导体层12b通过焊线而电连接于该引线14。在图1、图2中,为了有助于理解本发明,省略了关于焊线的记载。
该引线14与树脂外壳13成型为一体,并通过借助于模具的传递模塑而使其位于与树脂外壳13内的底面部13a的表面一致的平面上。在图3中示出将引线框架15一体成型的树脂外壳13。引线框架15的引线14的一部分贯通了树脂外壳13的侧面部13b而从树脂外壳13内延伸到树脂外壳13外。引线框架15经模具的塑造并通过传递模塑而与树脂外壳13一体成型。引线框架15的系杆15a在成型后被切除。
树脂外壳13具有近长方体的箱型形状,该大致为长方体的箱型形状的树脂外壳13具有底面部13a、以及围绕在该底面部13a的周围的侧面部13b。优选地,树脂外壳13由从聚苯硫醚树脂(PPS树脂)、聚对苯二甲酸丁二醇酯树脂(PBT树脂)、聚酰胺树脂(PA树脂)以及丙烯腈-丁二烯-苯乙烯共聚物树脂(ABS树脂)中选择的一种树脂构成。在树脂外壳13的底面部13a设置有开口部13c(参照图3),绝缘电路基板12紧密安装于该开口部13c。
另外,用于控制由半导体器件11A、11B构成的主电路的控制电路芯片16A、16B被设置于引线14上。
另外,如图2的剖面图所示,向已将焊线布线之后的树脂外壳13内注入由环氧树脂、硅树脂、聚氨酯树脂等构成的封固树脂17并使之固化,从而保护该树脂外壳13内的半导体器件11A、11B、引线14以及控制电路芯片16A、16B等。另外,在图1中,为了有助于对本发明的理解,图示出除了封固树脂17以外的树脂外壳13的内部。
对于本实施形态的半导体装置10而言,沿着树脂外壳13内的底面部13a的外周边缘,在引线14的至少一侧,优选为两侧,形成有凹部18。可通过在借助于传递模塑而将树脂外壳13与引线14成型为一体时使用的模具上设置对应于该凹部的凸部而形成该凹部18。
沿着树脂外壳13内的底面部13a的外周边缘,优选为沿着底面部13a与侧面部13b的边界,在引线14的两侧形成凹部18,从而可以减小引线14与树脂外壳13之间的间隙。关于其理由进行如下说明:使引线14与树脂外壳13密接是一件并不容易的事,相比之下树脂外壳13与封固树脂17之间的密着性却良好。因此,针对成型为与引线14的表面呈同一平面的树脂外壳13的底面部13a,由于在引线14的两侧形成了凹部18,因此树脂外壳13与封固树脂17之间的接触面积相比于没有形成凹部18的情形而言将会增加,故两者将牢固地密接。尤其是因为在引线14的两侧形成了凹部,因此该引线14的两侧部的密着性将提高,所以能够减少引线14与树脂外壳13之间的间隙。并且,由于凹部18为沿着树脂外壳13内的底面部的外周边缘形成,因此可以在远离树脂外壳13内的绝缘电路基板12的位置上防止水分的渗入。
通过以上措施,可以有效地防止水分通过树脂外壳13与引线14之间的间隙而从树脂外壳13的外部渗入到树脂外壳13内。
凹部18的深度与树脂外壳13的大小等也相关,只是作为一例,可以取0.3~0.5mm左右。凹部18的宽度可以取1.0mm左右。
其次对本发明的半导体装置的另一实施方式进行说明。在本实施形态中,沿着引线14具有前述的凹部18的同时,如图1~3所示,在与凹部18所在处不同的位置上设置有引线14的固定部件19。在图4(A)示出该固定部件19的放大俯视图,并在图4(B)示出放大侧视图。在图4所示的示例中,固定部件19是一个从引线14的侧部至引线14的上表面延续形成的突起物,其通过从侧面夹持引线14而固定引线14。固定部件19是由与树脂外壳13相同的材料构成,并与树脂外壳13的底面部13a形成为一体。可通过在借助于传递模塑而将树脂外壳13与引线14形成为一体之时使用的模具上设置对应于该固定部件19的凹部而形成(即通过该传递模塑而形成)固定部件19。
关于设置固定部件19的位置,如果从防止引线14摇晃的观点出发,则优选将其设置于引线14的延伸方向前端附近,尤其是优选与在引线14上接合焊线时使用的超声波仪器之间不发生干扰的位置。而且,固定部件19为近圆柱状,其圆柱的直径以及从引线表面的高度是与引线14的宽度、厚度、引线14的间隔等也相关,可以分别取1mm以下的程度。
固定部件19并不局限于在每一个引线14的两侧分别只予设置一个固定部件的示例。可以沿着一个引线14的延伸方向设置多个固定部件19。
在图5中以俯视图表示出固定部件的变形例。图5(A)中所示的固定部件19A是形成为在引线14的整个宽度方向上覆盖的固定部件。图5(B)中所示的固定部件19B是形成为在多个引线14的整个宽度方向上覆盖的固定部件。
借助于上述的固定部件19、19A、19B而可以使引线14密接于树脂外壳13的底面部13a,从而可以提高半导体装置的可靠性。并且,可在导线接合时防止引线14的摇晃,进而可以提高接合时的可靠性(导线接合性)。
接着,对本发明的半导体装置的又一实施方式进行说明。在本实施形态中,如图1、3所示,在与沿着树脂外壳13内的底面部13a的外周边缘设置的凹部18所在处不同的位置上,具体地,在引线14的延伸方向的中间点、引线的前端部,沿着引线14的侧部设置有凹部20。可通过在借助于传递模塑而将树脂外壳13与引线14成型为一体时使用的模具上预先设置对应于该凹部20的凸部而形成凹部20。
由于形成这样的凹部20,因此树脂外壳13与封固树脂17之间的接触面积相比于没有形成凹部20的情形而言将会增加,所以树脂外壳13与封固树脂17在引线14附近将会牢固地密接,从而可以减少邻近凹部20的部分的引线14与树脂外壳13之间的间隙。进而可以防止水分从这些位置的渗入。即,通过形成凹部18和凹部20,能够双重地防止水分的渗入。
作为凹部20设定位置的优选例,将图1的VI部分附近的放大图示于图6。在图6中,在树脂外壳13的底面部13a上有多个引线14并排延伸。设置于这些引线14附近的凹部20并没有在引线14的宽度方向上整齐地配置,而是采用交错配置。通过采用交错配置,可将引线14与树脂外壳13之间的密着性进一步提高。
至于凹部20,可将作为销的印迹形成于树脂外壳13内的凹部直接利用,该销是一种在通过传递模塑而将树脂外壳13成型之时为了使引线14找准位置而设置于模具的销。在此情况下,不需要在通常的销之外另在模具上形成用于设置凹部20的凸部的工夫、成本。
然后对本发明的别一实施方式进行说明。
图7表示图1的VII部分的放大图。在引线14上有多个控制电路芯片16A相邻设置的情况下,这些控制电路芯片16A之间部分的引线14的宽度要比搭载有控制电路芯片16A的部分的引线14宽度还窄。由于控制电路芯片16之间的引线14宽度变窄,因此与没有使引线14宽度变窄的情形相比而言树脂外壳13的底面部13a与引线14之间的密着性将会得到提高,进而可以提高半导体装置10的可靠性。
然后利用图8对本发明另外的实施方式进行说明。
图8是以垂直于引线14延伸方向的方向进行剖切的示意性剖面图。引线14是通过对金属箔进行冲压加工而制造。通过该冲压加工,从而使得引线14具有梯形截面。使上边比下边短的梯形截面的引线14的上边位于树脂外壳13的底面部13a的表面。据此,引线14变得难以从树脂外壳13的底面部13a脱落,从而可以提高引线14与树脂外壳13之间的密着性。
另外,图9是以垂直于引线14延伸方向的方向进行剖切而使得包含沿着树脂外壳13内的底面部13a的外周边缘形成的凹部18的示意性剖面图。引线14同样具有梯形截面。
如图9(A)所示,引线14两侧的倾斜面被引线14与凹部18之间的树脂外壳13所覆盖。夹设有树脂外壳13的树脂,并有封固树脂17密接于引线14的侧面,据此可以进一步防止经由引线14与树脂外壳13之间缝隙的水分入侵。封固树脂17与引线14的密着性较差时更显有效。而且,在图9(A)中,一个引线14的两侧连接形成两个凹部18,相邻的引线14之间共用一凹部18。如图9(B)所示,对于每一个引线14,还可以使凹部18形成为连接于引线14的两侧,并使多个凹部18配置于引线14之间。在相邻引线14分离的情况下,树脂外壳13与封固树脂17的密着性可得到提高。另外,在图9中是将凹部18形成为连接于引线14的两侧,然而也可以配置为只连接于引线14的至少一侧。
[实施例]
针对图1、图2所示的半导体装置10(本发明实施例)与除了不具有凹部18、固定部件19以外则与半导体装置10构成为相同的半导体装置(比较例),进行树脂密着性评估并研究了导线接合性。关于树脂密着性评估,在130℃、湿度为85%、压力为0.23Mpa的试验条件下对半导体装置10进行了96个小时的压力锅试验,并在经过这些时间以后根据是否存在树脂剥落而进行了评估。关于这是否存在树脂剥落,是通过超声波探伤法而对树脂界面的密着状态进行了评估。另外,关于导线接合性,则是在对引线14进行导线接合之后根据导线接合性良好的产品的比例而进行了评估。
树脂密着性评估结果,沿着树脂外壳13内的底面部13a的外周边缘而在引线14的两侧形成了凹部18的本发明实施例中并没有出现树脂剥落,相比之下没有形成凹部18的比较例中却出现树脂剥落。
导线接合性评估结果,具有固定部件19的本发明实施例中导线接合性良好的产品的比例为100%,而在不具有固定部件19的比较例中导线接合性良好的产品的比例为95%。
Claims (11)
1.一种半导体装置,其特征在于,具有:
绝缘电路基板,搭载有至少一个半导体器件;
树脂外壳,具有安装有该绝缘电路基板的底面部以及围绕该底面部周围的侧面部;
引线,与该树脂外壳成型为一体,以位于该树脂外壳内的底面部的表面的方式被并排地设置于该绝缘电路基板的周围,并且将一部分从该树脂外壳内贯通所述侧面部而延伸到树脂外壳之外;
封固树脂,填充于该树脂外壳内,
其中,所述引线的上表面与所述底面部的表面呈同一平面,沿着所述底面部与所述侧面部的边界而在该引线的两侧分别形成凹部,所述封固树脂填入所述凹部并固化。
2.一种半导体装置,其特征在于,具有:
绝缘电路基板,搭载有至少一个半导体器件;
树脂外壳,具有安装有该绝缘电路基板的底面部以及围绕该底面部周围的侧面部;
引线,与该树脂外壳成型为一体,以位于与该树脂外壳内的底面部的表面相同的平面上的方式被并排地设置于该绝缘电路基板的周围,而且将一部分从该树脂外壳内贯通所述侧面部而延伸到树脂外壳之外;
封固树脂,填充于该树脂外壳内,
其中,所述引线的上表面与所述底面部的表面呈同一平面,沿着所述底面部与所述侧面部的边界而在该引线的两侧分别形成凹部,所述封固树脂填入所述凹部并固化,而且,在与该凹部所在处不同的位置上沿着该引线的延伸方向设置有固定部件。
3.如权利要求2所述的半导体装置,其中,所述固定部件是从所述引线的侧部一直形成到该引线的上表面的突起物。
4.如权利要求2或3所述的半导体装置,其中,所述固定部件是由与所述树脂外壳相同的材料构成,并与该树脂外壳一体成型。
5.如权利要求1~3中的任意一项所述的半导体装置,其中,在与沿着所述底面部与所述侧面部的边界设置的凹部所在处不同的位置中,沿着所述引线的延伸方向在所述引线的侧部形成有凹部。
6.如权利要求5所述的半导体装置,其中,形成于所述引线侧部的凹部沿着并排延伸的多个引线的延伸方向交错配置。
7.如权利要求5所述的半导体装置,其中,形成于所述引线侧部的凹部为成型模具的销的印迹。
8.如权利要求1~3中的任意一项所述的半导体装置,其中,所述引线包含搭载有控制电路芯片的部分,且与搭载有该控制电路芯片的部分的引线宽度相比,该部分之间的引线的宽度更窄。
9.如权利要求1~3中的任意一项所述的半导体装置,其中,所述引线在垂直于延伸方向的剖面中具有上边比下边短的梯形形状,且该上边位于树脂外壳的底面部的表面。
10.如权利要求1~3中的任意一项所述的半导体装置,其中,所述树脂外壳由从聚苯硫醚树脂、聚对苯二甲酸丁二醇酯树脂、聚酰胺树脂、以及丙烯腈-丁二烯-苯乙烯共聚物树脂中选择的一种树脂构成。
11.如权利要求1~3中的任一项所述的半导体装置,其中,所述封固树脂由环氧树脂、硅树脂或聚氨酯树脂构成。
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2578530Y2 (ja) * | 1992-06-08 | 1998-08-13 | サンケン電気株式会社 | 端子接続構造 |
JP2956363B2 (ja) * | 1992-07-24 | 1999-10-04 | 富士電機株式会社 | パワー半導体装置 |
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JP4219448B2 (ja) * | 1998-08-28 | 2009-02-04 | 富士電機デバイステクノロジー株式会社 | 半導体装置 |
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JP2000236048A (ja) | 1999-02-16 | 2000-08-29 | Shindengen Electric Mfg Co Ltd | 樹脂封止型半導体装置 |
JP2000332179A (ja) * | 1999-05-18 | 2000-11-30 | Fujitsu Ten Ltd | 端子の固定構造 |
US6696749B1 (en) * | 2000-09-25 | 2004-02-24 | Siliconware Precision Industries Co., Ltd. | Package structure having tapering support bars and leads |
JP3888228B2 (ja) * | 2002-05-17 | 2007-02-28 | 株式会社デンソー | センサ装置 |
JP3715590B2 (ja) * | 2002-06-17 | 2005-11-09 | 三菱電機株式会社 | インサート成形ケース及び半導体装置 |
US6844621B2 (en) * | 2002-08-13 | 2005-01-18 | Fuji Electric Co., Ltd. | Semiconductor device and method of relaxing thermal stress |
WO2006059828A1 (en) * | 2004-09-10 | 2006-06-08 | Seoul Semiconductor Co., Ltd. | Light emitting diode package having multiple molding resins |
JP4459883B2 (ja) * | 2005-04-28 | 2010-04-28 | 三菱電機株式会社 | 半導体装置 |
KR101203466B1 (ko) * | 2006-04-20 | 2012-11-21 | 페어차일드코리아반도체 주식회사 | 전력 시스템 모듈 및 그 제조 방법 |
JP5060074B2 (ja) * | 2006-05-11 | 2012-10-31 | 東レ・ダウコーニング株式会社 | 接着促進剤、硬化性オルガノポリシロキサン組成物、および半導体装置 |
JP2007305962A (ja) * | 2006-05-12 | 2007-11-22 | Honda Motor Co Ltd | パワー半導体モジュール |
JP4985116B2 (ja) * | 2007-03-08 | 2012-07-25 | 富士電機株式会社 | 半導体装置およびその製造方法 |
JP5061717B2 (ja) | 2007-05-18 | 2012-10-31 | 富士電機株式会社 | 半導体モジュール及び半導体モジュールの製造方法 |
US7763970B2 (en) * | 2008-02-27 | 2010-07-27 | Infineon Technologies Ag | Power module |
JP2010199166A (ja) | 2009-02-24 | 2010-09-09 | Panasonic Corp | 光半導体装置用リードフレームおよび光半導体装置用リードフレームの製造方法 |
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2013
- 2013-02-15 JP JP2013027960A patent/JP6115172B2/ja active Active
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2014
- 2014-02-13 CN CN201410049540.9A patent/CN103996662B/zh active Active
- 2014-02-14 US US14/180,874 patent/US9064818B2/en active Active
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US20140231975A1 (en) | 2014-08-21 |
US9064818B2 (en) | 2015-06-23 |
JP2014157925A (ja) | 2014-08-28 |
CN103996662A (zh) | 2014-08-20 |
JP6115172B2 (ja) | 2017-04-19 |
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