CN205428897U - 电子装置 - Google Patents

电子装置 Download PDF

Info

Publication number
CN205428897U
CN205428897U CN201520739701.7U CN201520739701U CN205428897U CN 205428897 U CN205428897 U CN 205428897U CN 201520739701 U CN201520739701 U CN 201520739701U CN 205428897 U CN205428897 U CN 205428897U
Authority
CN
China
Prior art keywords
electronic installation
region
top surface
lead wire
nude film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201520739701.7U
Other languages
English (en)
Inventor
F·科庞
A·米诺蒂
F·萨拉莫内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of CN205428897U publication Critical patent/CN205428897U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • H01L21/566Release layers for moulds, e.g. release layers, layers against residue during moulding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49568Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45014Ribbon connectors, e.g. rectangular cross-section
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73221Strap and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/84801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/8485Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/4952Additional leads the additional leads being a bump or a wire
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/183Connection portion, e.g. seal
    • H01L2924/18301Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本公开涉及一种电子装置,具有顶表面和底表面,装置包括:半导体裸片,集成了电子部件,具有正面以及与正面相对的背面,正面具有用于电接入至电子部件的第一电接入区域;引线框架结构,包括支撑区域,支撑区域在对应于半导体裸片的背面并且电耦合至半导体裸片的背面的区域中容纳半导体裸片;保护本体,其横向地并且在顶部处围绕半导体裸片以及至少部分地围绕引线框架结构,从而限定电子装置的顶表面、底表面和厚度;以及至少一个第一导电引线,电耦合至第一电接入区域,第一导电引线被成形为延伸遍布保护本体的厚度以用于形成从电子装置的顶表面可接入的正面电接触,以及从电子装置的底表面可接入的背面电接触。

Description

电子装置
技术领域
本实用新型涉及一种具有改进的电可接入性的包括封装结构的电子装置。
背景技术
如已知的那样,在半导体装置的制造中,封装或包装是将半导体衬底转换为可以安装在印刷电路板(PCB)上的功能部件的最终步骤。通常,半导体衬底形式为半导体裸片。封装为半导体裸片提供了保护并且提供了必要的电连接,通过电连接其能够向半导体裸片提供信号并且获取来自半导体裸片的信号。
为了满足越来越高度集成和尺寸缩减的需求,当前使用的封装方法包括裸片级或晶片级封装(WLP)和3D封装。其他解决方案构思了表面安装装置(SMD),其能够进一步缩减封装的尺寸和组件的成本。例如,考虑已知为PowerFlatTM的封装。该类型封装使得当安装在PCB上时减小了由封装自身占据的空间,并且同时通过在封装底部与PCB之间金属连接而提高了与PCB自身的热交换。实际上,如借由图1中示例的方式所示,通过延伸在封装底表面中的平坦区域而获得电连接。参照图1,由附图标记1标注封装。构成了用于裸片3的支撑基座并且设计用于在裸片3和封装1外侧之间提供电连接的结构2已知为“引线框架”,并且以此方式延伸使得其底表面区域2b位于与封装1的底表面1b相同的平面中,因此自身构成了封装1的底表面1b的一部分。裸片3接合(例如由粘合层4)至引线框架2的顶表面区域2a。该顶表面区域2a具有明确地专用于与裸片3耦合的平坦表面,更好地已知为“裸片连接焊盘”。引线框架2的顶表面区域2a与引线框架2的底表面区域2b相对。
引线框架2在底表面区域2b上形成了多个电接触区域5a、5b,其相互电绝缘并且每个设计用于传输来自和/或发送至PCB的信号。例如,如果裸片3提供了MOS晶体管,电接触区域5a将例如电耦合至MOSFET的源极区域S,而电接触区域5b将例如电耦合至MOS晶体管的漏极区域D。在该示例中必须提供其他电接触(未示出)以形成栅极电接触。
树脂层7、特别是环氧树脂延伸在引线框架2的顶表面区域2a之上以覆盖并保护裸片3,并且设计用于确保引线框架2和裸片3的顶部电绝缘。树脂7进一步延伸在引线框架2的穿孔区域中,直至其到达底表面区域2b所在平面,并且因此完成了封装1的底表面1b的形成。
因为电接触区域5a、5b均延伸在封装1的底表面1b中,因此在封装1的底表面1b处获得了与PCB(在此未示出)的电耦合。通常,引线框架2的整个底表面区域2b被设计用于面向PCB,并且因此同样地提供了用于在封装1和PCB之间热交换的表面。
当前的封装并且特别是参照图1所述的封装展示某些缺点。特别地,对于功率应用而言,与PCB获得的热交换可能不足以确保裸片3的良好冷却。此外,用于测试封装1的操作证明是复杂和昂贵的,在它们仅可以通过提供专用于测试工序的PCB而执行的范围内,封装1将要通过底表面1b的接合而耦合至PCB。
实用新型内容
本实用新型的目的在于提供一种将能够克服现有技术的关键方面并且扩展其功能的电子装置。
根据本公开的一个方面,通过一种电子装置,具有顶表面,距所述顶表面一定距离并且与所述顶表面平行的底表面,以及作为沿着垂直于所述顶表面和所述底表面的方向的在所述顶表面和所述底表面之间的所述距离的厚度,所述装置包括:-半导体裸片,集成了电子部件,具有正面以及与所述正面相对的背面,所述正面具有用于电接入至所述电子部件的第一区域;-引线框架结构,包括支撑区域,所述支撑区域在对应于所述半导体裸片的背面并且电耦合至所述半导体裸片的背面的区域中容纳所述半导体裸片;-保护本体,其横向地并且在顶部处围绕所述半导体裸片以及至少部分地围绕所述引线框架结构,从而限定所述电子装置的所述顶表面、所述底表面和所述厚度;以及-至少一个第一导电引线,电耦合至所述第一电接入区域,所述第一导电引线被成形为延伸遍布所述保护本体的厚度以用于形成从所述电子装置的顶表面可接入的正面电接触,以及从所述电子装置的底表面可接入的背面电接触。
可选地,电子装置进一步包括,热耦合至所述第一电接入区域的导电薄片,所述导电薄片在对应于所述电子装置的顶表面的区域处朝向所述保护本体的外侧暴露。
可选地,所述导电薄片进一步电耦合至所述裸片的所述第一电接入区域。
可选地,在所述裸片的所述正面和所述背面之间的至少一个具有用于电接入至所述电子部件的第二区域,所述电子装置进一步包括与所述第一导电引线电绝缘并且电耦合至所述第二电接入区域的第二导电引线,其中所述第二导电引线被模制为延伸遍布所述保护本体的厚度以用于形成从所述电子装置的顶表面可接入的相应正面电接触以及从所述电子装置的底表面可接入的相应背面电接触。
可选地,在所述裸片的所述正面和所述背面之间的另一个具有用于电接入至所述电子部件的第三区域,所述电子装置进一步包括与所述第一导电引线和所述第二导电引线电绝缘并且电耦合至所述第三电接入区域的第三导电引线,其中所述第三导电引线被成形为延伸遍布所述保护本体的厚度以用于形成从所述电子装置的顶表面可接入的相应正面电接触以及从所述电子装置的底表面可接入的相应背面电接触。
可选地,所述引线框架结构在对应于所述电子装置的底表面的区域处朝向所述保护本体的外侧暴露,并且电耦合至延伸进入所述裸片的背面中的电接入区域。
可选地,所述电子部件是MOS晶体管,以及所述第一电接入区域、所述第二电接入区域和所述第三电接入区域是所述MOS晶体管的源极、栅极和漏极。
可选地,所述第一导电引线包括突出导电部分,所述突出导电部分与其自身的正面电接触和背面电接触一体成型并且以悬臂方式从所述保护本体延伸。
附图说明
为了更好的理解本实用新型,现在参照附图描述纯借由非限定性示例方式提供的优选实施例,其中:
图1示出了根据已知类型实施例的具有封装的电子装置;
图2A和图2B分别以立体图和以俯视图示出了根据本实用新型一个方面的引线框架结构;
图3示出了在中间制造步骤中电子装置的结构,其包括容纳了半导体裸片的图2A的引线框架;
图4示出了在模塑步骤结束处图3的电子装置,其具有根据本实用新型一个方面的封装;
图5A-图5E示出了用于获得图4电子装置的模塑步骤;
图6以俯视图示出了在引线框架分割步骤之前图2B的引线框架的阵列60;
图7示出了沿着截面线VII-VII获取的图4的电子装置的截面图;
图8示出了根据对图3实施例的变形例的、在中间制造步骤中电子装置的结构;
图9示出了对图5D的模塑步骤的变形例的、图8的中间结构的模塑的步骤;
图10A和图10B示出了在模塑步骤结束处图8电子装置的相应示图,其具有根据本实用新型另一方面的封装;以及
图11A和图11B示出了根据本实用新型另一方面的电子装置的相应示图。
具体实施方式
参照图2A,立体图中展示的是被设计用于承载裸片(也即为其提供机械支撑)并且被设计用于在裸片和封装1外侧之间提供电连接的一部分的结构12。结构12已知为“引线框架”。图2B以俯视图示出了图2A的引线框架12。
参照图2A和图2B,引线框架12包括中心区域13,具有基本平坦的暴露表面12a,其被设计用于容纳裸片并且称作“裸片焊盘”或“裸片附接焊盘”。引线框架12的后表面12b与表面12a相对延伸,后表面12b是基本平坦的并且被设计用于与一部分PCB(未示出)形成引线框架12的驻留或耦合基底。
多个“引线”14、15从中心区域13在电学上去耦地延伸,而引线16机械并且电耦合至中心区域13而延伸(特别地,它们与中心区域13一体成形)。
更详细地,引线框架12的中心区域13具有基本上四边形的形状并且在平面XY中延伸,具有沿着垂直于平面XY的轴线Z测量的厚度,厚度被包括大约在100μm和300μm之间、特别是大约200μm。根据一个实施例,引线框架12的中心区域13沿着X延伸介于3和6mm之间(例如3.22mm)的距离并且沿着Y延伸介于4和5mm(例如4.61mm)之间的距离。中心区域13的尺寸可以相对于其指示的尺寸而改变,并且根据其必须覆盖的裸片尺寸而选择。
引线14和15面向中心区域13的侧边13a而延伸(沿着Y延伸)。引线14和15均具有沿着轴线X的正向的主延伸方向,并且由沟槽19与中心区域13机械和电分隔。引线14包括直接面向沟槽19的支撑部分14a,以及机械和电耦合至支撑部分14a的多个突出元件14b,多个突出元件14b从支撑部分14a以悬臂方式沿着X延伸以形成叉指14b。支撑部分14a沿着X延伸大约1-2mm。
引线15类似于引线14,并且包括直接面向沟槽19的支撑部分15a,以及机械和电耦合至支撑部分15a、以悬臂方式沿着X从支撑部分15a开始延伸以形成叉指15b的仅一个突出元件15b。引线15由额外沟槽21与引线14机械和电分隔。支撑部分15a沿着X延伸大约1-2mm,类似于支撑部分14a。
叉指14b、15b均被设计用于沿着Y具有包括大约在200和400μm之间(例如大约350μm)的厚度,以及沿着Z具有包括大约在0.5mm和1.5mm之间(例如大约0.8mm)的厚度。特别地,叉指14b和15b沿着Z的厚度基本上等于在制造步骤结束处被设计或被设想用于容纳引线框架12的封装的厚度。
叉指14b、15b均沿着Y面向另一叉指14b、15b,并且沿着Y以大约1mm的距离而相互分隔。图2A和图2B中所示为三个叉指14b和仅一个叉指15b。然而,能够提供从一个开始的任何所需数目的叉指14b、15b。
引线16从中心区域13的沿方向X与侧边13a相对的侧边13b延伸,与中心区域13机械和电接触,并且沿轴线X的负方向前进。根据图2的实施例,引线16沿着轴线Y延伸遍布侧边13b的长度。然而,明显的是,可以设想变形例。例如,引线16可以沿着Y延伸短于侧边13b长度的距离。备选地,也可以在对应于侧边13b的区域中提供与引线14和/或15相同类型的引线。此外,引线16具有沿着轴线Z等于引线14、15厚度的厚度。
引线16包括直接耦合至中心部分13的支撑部分16a,以及从支撑部分16a以悬臂方式沿着轴线X分支的多个叉指16b。
图3示出了中间封装结构23,包括图2A和图2B的引线框架12以及容纳在引线框架12的中心区域13中的裸片25。裸片25是之前设计加工类型,并且实施了例如MOS晶体管。为此目的,裸片25使得可应用外部金属接触,也即:源极接触25a;栅极接触25b,由绝缘区域26与源极接触25a电绝缘;以及漏极接触25c,延伸在裸片25的背面上并且与引线框架12的中心区域13电接触。源极接触25a、栅极接触25b和漏极接触25c以本质上已知的方式由金属材料制成,例如铝或铜或者包括铝或铜的金属合金,或者另外其他金属。
源极区域25a由例如铝的金属条带28电耦合至引线14的支撑部分14a。导电条带28在功率应用中优选地为导电引线。明显的是,根据需要,对于图中所示的备选例是可能的。栅极区域25b由导电引线30电耦合至引线15的支撑部分15a。集成在裸片25中晶体管的漏极端子由以本质上已知方式形成的金属接合接触或导电粘合层而耦合至引线框架12的中心部分13。因为引线16与引线框架12的中心部分13直接电接触,因此引线16与集成在裸片25中晶体管的漏极端子电连接。
图4示出了具有封装40的电子装置41,封装密封了裸片25并且部分地密封了图3的引线框架12。通过将图3的引线框架12和裸片25经受模塑步骤、由聚合物层42(通常为环氧树脂)完全覆盖引线框架的中心部分13、引线14、15的支撑部分14a、15a以及电连接28、30而获得了电子装置41。也采用聚合物层42填充沟槽19和21。引线14、15和16并未完全由聚合物层42覆盖,并且突出至封装40外侧,使得能从封装40自身外侧电接入。
封装40包括位于与平面XY平行的平面中的顶侧40a,以及沿方向Z与顶侧40a相对并且位于与平面XY平行的相应平面中的底侧40b。封装40进一步包括位于与平面XY平行的平面中的侧表面特别是侧表面40c,以及沿着X与侧表面40c相对并且位于与平面YZ平行的相应平面中的侧表面40d。
如可以从图4注意到的那样,叉指14b、15b和16b的相应顶表面部分14’、15’和16’并未由聚合物层42覆盖,并且基本上位于与封装40的顶侧40a相同平面中。可在封装40的底侧40b上获得叉指14b、15b、16b的类似底表面部分(图中未示出)。
此外,引线14和15可以封装40的侧表面40c接入(通过接入叉指14b、15b的侧向突出),并且引线16也可以从封装40的与侧边40c相对的侧表面40d而接入(通过接入叉指16b的侧向突出)。
在可以由Boschman技术获得的薄膜辅助模塑(FAM)工艺之后执行用于完成封装40形成的模塑步骤。薄膜辅助模塑工艺使得在其一个或多个表面上封装了超薄的半导体部件。
参照图5A,薄膜辅助模塑工艺设计使用了包括第一模具52和第二模具54的封装***50。第二模具54设计用于在引线框架12的背面(在此,引线框架12的背面被定义为在裸片25所驻留的区域中与区域13的表面相对的引线框架12的表面)上支撑引线框架12(如图3的情形中)。第一模具被成形为容纳引线框架12(特别是引线14-16)的顶表面,以及裸片25和由条带28和由导电引线30形成的电连接。
第一模具52为此目的包括空腔55,在模塑步骤结束处至少部分地限定了聚合物层42的最终形状。第二模具54在该示例中具有平坦的静止表面。
封装***50进一步设计使用模塑薄膜56,其设计用于遵循第一模具52的空腔55的形状,如参照图5B和图5C更清晰所示。为此目的,模塑薄膜56可以由可模塑材料构成,其设计用于粘合至空腔55的壁或者可以预形成和预模塑以使得它们呈现与空腔55相同的形状。
第一模具52、模塑薄膜56和空腔55以此方式限定尺寸和/或建模以使得引线14、15、16的叉指14b、15b、16b的顶表面14’、15’、16’在第一模具设置为接触第二模具时与模塑薄膜56直接接触,如图5C的箭头57所示。图5D示出了通过模塑薄膜56而相互接触的第一和第二模具。更特别地,在图5D的步骤期间,叉指14b、15b、16b的顶表面14’、15’、16’部分地嵌入在模塑薄膜56中以在后续模塑步骤中被保护。换言之,由叉指14b、15b、16b的顶表面14’、15’、16’局部地模压了模塑薄膜56。
图5E示出了模塑步骤,其中聚合物材料、更特别地热塑性聚合物或树脂注入至空腔55中以形成聚合物层42,特别是在裸片25以及电接触28和30的顶部上。由模塑薄膜56保护的引线14-16的部分并未由聚合物材料所覆盖。与第二模具54接触的、引线框架12的底表面部分也并未由聚合物材料覆盖。
接着,执行聚合物材料的固化步骤以促进其硬化。在热塑性材料的情形中,执行加热至取决于所使用材料类型的温度。例如,在环氧树脂的情形中,在烤炉中在175℃下执行烘培的步骤8h。
随后,执行封装清洁的任选步骤(去除毛刺步骤)以用于移除来自引线框架12的应该保留暴露以从外侧联接的区域之上的任何可能的聚合物材料残留。
为了表达的简明,已经参照仅容纳一个裸片的一个引线框架而示出和描述了图5A-图5E的模塑步骤。然而,通常对与图6中借由示例方式(在俯视图中)示出类型机械地接合在一起的引线框架12的阵列执行模塑操作。在俯视图中,图6示出了引线框架的阵列60,其中为了表达的简明,已经省略了裸片25以及电连接28、30。
在聚合物材料的模塑和硬化步骤之后,通过在切割区域61中执行切割步骤(以本质上已知的方式)将每个引线框架12与相邻的引线框架12分隔。以此方式,每个封装40与其他封装40分隔。
图7示出了沿着截面线VII-VII获取的并且在图5E步骤之后获得的图4的封装40的侧截面图。
如从图7可注意到的那样,封装40的底侧40b通过接触引线框架12背面的暴露部分而可电接入,背面暴露部分也即引线框架12的沿着轴线Z与其上驻留了裸片25的中心区域13相对的表面,并且其代表了裸片25自身的漏极接触。封装40的顶侧40a也通过接触引线框架12的正面的暴露部分而可电接入。
图8示出了本实用新型的另一实施例。在该情形中,在具有图2所示类型并且已经参照该附图描述了的引线14-16的引线框架12设置在合适位置处之后,接下来,在引线框架12的中心区域13中耦合裸片25的步骤,如已经参照图3所述。
根据图8的实施例,接下来是在裸片25的顶部上耦合例如金属(特别是铜)的导电薄片70的另一步骤,导电薄片与源极金属化结构25a电接触但是并未与栅极金属化结构25b电接触。导电薄片70延伸直至其到达并且电接触了引线14的支撑部分14a,因此替代了图3中所示的条带28。栅极金属化结构25b替代地由之前所述导电引线30而电耦合至引线15的支撑部分15a。导电薄片70借由例如导电粘胶层而机械地耦合至源极金属化结构25a。其他实施例是可能的,例如金属接合或者另外其他。
导电薄片70的厚度被选择为使得在与裸片25机械耦合的步骤之后,其沿着轴线Z正向测得的最大高度基本上等于沿着轴线Z正向由引线14、15和16所到达的最大高度。换言之,导电薄片70的顶表面70’基本上与引线14、15和16的相应顶表面14’、15’和16’共平面。由导电薄片70沿着Z达到高度相对于所需高度的可能变化可以削减至例如产品散差(productionspread)。
例如根据一个实施例,引线框架12在中心部分13中具有沿着Z的大约200μm±10μm的厚度,耦合在中心区域13和裸片25之间的层(例如焊料凸块或导电粘胶)具有沿着Z的大约40μm±10μm的厚度,裸片25具有沿着Z的大约200μm±10μm的厚度,在裸片25的源极金属化结构25a(例如焊料凸块或导电粘胶)与导电薄片70之间的另外耦合层具有沿着Z的大约40μm±10μm的厚度,并且最终,选择导电薄片70的厚度以便于达到由引线14-16所达到的沿着Z的最大高度。例如,考虑到均具有相同厚度的等于0.8μm的引线14-16,导电薄片70选择具有240μm的厚度。
以此方式,根据图5A-图5E步骤,获得了中间引线框架结构73,其遵循与参照中间引线框架23所述的相同模塑工艺。参照图6做出的相同考虑同样在此适用。在考虑了之前所示的容差的情形下,由导电薄片70达到的最大高度、与由引线14-16所达到最大高度相比之间的可能差值由制造散差引起。在任何情形中,因为在模塑步骤期间导电薄片70和引线14-16挤压抵接模塑薄膜56,从而部分地沉入其中,因此补偿了由于制造散差导致的厚度的可能变化,并且在模塑步骤期间保护了导电薄片70的顶表面70’以及引线14-16的顶表面14’-16’,并且导电薄片70的顶表面70’以及引线14-16的顶表面14’-16’并未由聚合物层所覆盖。
图9示出了在中间引线框架结构73的情形中图5D的模塑步骤。应该指出,在图9的情形中,导电薄片70也在其顶表面70’中与模塑薄膜56直接接触。更特别地,在图9的步骤期间,叉指14b、15b、16b的顶表面14’、15’、16’以及导电薄片70的顶表面70’部分地嵌入模塑薄膜56中以在后续模塑步骤期间(根据图5E的类型)受保护。换言之,模塑薄膜56由叉指14b、15b、16b的顶表面14’、15’、16’以及由导电薄片70的顶表面70’而被局部地挤压。
图10A示出了在图9的模塑步骤之后的具有密封了图8的中间引线框架结构73的封装90的电子装置91。通过由聚合物层92(具有与参照聚合物层42所述的相同特性)完全覆盖引线框架12的中心部分13、引线14、15的支撑部分14a、15a、裸片25以及导电引线30而获得电子装置91。也采用聚合物层92填充沟槽19和21。
封装90包括位于平行于平面XY的平面中的顶侧90a,以及沿方向Z与顶侧90a相对、并且位于平行于平面XY的相应平面中的底侧90b。封装90进一步包括位于平行于平面YZ的平面中的侧表面,特别是侧表面90c,以及沿着X与侧表面90c相对、并且位于平行于平面YZ的相应平面中的侧表面90d。
关于导电薄片70,注意其并未由聚合物层92完全覆盖。特别地,导电薄片70的顶表面70’在对应于顶侧90a的区域中朝向封装90的外侧而暴露,并且可电接入。沿着Z延伸至其高度低于顶表面70’高度的薄片70的那部分替代地由聚合物层92所覆盖(可能地,除了在图9的步骤期间嵌入在模塑薄膜中的箔片70的那部分之外)。
引线14、15和16并未由聚合物层92完全覆盖,并且突出至封装90外侧,使得可在顶侧90a和底侧90b上从封装90外侧电接入,或者在侧表面90c(引线14、15)和侧表面90d(引线16)上横向地电接入。如从图9中可以注意,叉指14b、15b、16b的顶表面的部分14’、15’、16’并未由聚合物层92覆盖,并且基本上位于与封装90的顶侧90a相同的平面中,与导电薄片70的暴露表面70’共面。
为了说明的完整性,可以注意,引线14和15进一步可以从封装90的侧表面90c可接入,并且引线16也可以从封装90的与侧边90c相对的侧表面90d可接入。
图10B示出了围绕轴线X旋转180°的图10A的电子装置91以用于示出底面90b。可以注意,叉指14b、15b、16b的底表面部分14”、15”、16”,其可以从封装90的底侧90b电接入。引线框架12的底表面(沿着Z与裸片25所在中心区域13相对)进一步延伸并且暴露在封装90的底侧90b上。以此方式,除了存在引线14-16之外,封装90还在对应于顶侧90a的区域中以及在对应于底侧90b的区域中均存在两个导电表面(特别是金属导电表面)。
图11A和图11B分别示出了根据本实用新型另一实施例的具有封装100的电子装置101的俯视图和底视图。
封装100包括位于平行于平面XY的平面中的顶侧100a,以及沿方向Z与顶侧100a相对并且位于平行于平面XY的相应平面中的底侧100b。封装100进一步包括侧表面,特别是位于平行于平面YZ的平面中的侧表面100c,以及沿着X与侧表面100c相对并且位于平行于平面YZ的相应平面中的侧表面100d。
在该情形中,存在引线114-116,被成形为使得在模塑步骤之后,它们在侧表面100c和100d上并未从聚合物层突出,但是位于与侧表面100c和100d的基本上相同的相应平面中(也即在平行于平面YZ的平面中)。封装100密封了图8中所示类型的中间引线框架结构,并且除了存在均可从顶侧100a和底侧100b可联接的引线114-116之外因此也存在可以从顶侧100a和底侧100b电接入的导电区域。
根据之前所述任一个实施例的本实用新型可以适用于许多技术分区。特别地,能够在导电薄片70的暴露表面70’上和/或在引线框架12的暴露表面12b上安装热交换器。
此外,参照图4以及图10A-图10B,因为引线14-16具有以悬臂方式从封装突出的狭长形状,它们使得垂直于PCB所在平面而安装封装,也即通过将引线14-15或者备选地16***有意提供在PCB上的孔洞中。
从检查根据本公开所获得的本实用新型的特征,其提供的优点是明显的。
从封装自身两侧接入封装的管脚的可能性允许设计者在设计阶段的更大灵活性,例如在用于密封在封装中裸片的电源以及用于发送其控制信号的相互不同并且相互独立的电路的研发中。可以进一步减小用于测试步骤的印刷电路的复杂性(能够在顶部接入裸片,而无需执行其与测试PCB的键合)。
此外,增大了用于热交换的面积,这优化了在散热方面的性能。导电薄片70(暴露在封装顶侧上并且因此用作热交换器)与裸片25的最热部分接触,也即与处理了功率信号的金属化结构接触(在晶体管的情形中,在产生最多热量的MOS结附近,与源极金属化结构接触),则在图10A-图10B以及图11A-图11B的实施例的情形中这均更有效。
最终,明显的是,可以对在此所述和所示的本实用新型做出修改和改变而并未由此脱离如所附权利要求中所限定的本实用新型的范围。
例如,导电薄片70可以不电耦合至引线14。在该情形中,除了导电薄片70之外,同样存在了在源极区域和引线14之间形成电连接的条带28。导电薄片70延伸在裸片25之上,与其热接触,并且排他地具有朝向封装外侧热交换器的功能。
此外,可以省略耦合至晶体管的漏极接触的导电引线16。在该情形中,在任何情形中可以从引线框架12的底表面12b实现至漏极接触的电接入。
此外,在图5A-图5E中所示的模塑步骤期间,能够将类似于模塑薄膜56的另一模塑薄膜也***在第二模具54和中间封装结构23、73之间,以使得引线框架12和引线14-16保持在所述另一模塑薄膜上并且在模塑步骤期间更好地被保护。

Claims (8)

1.一种电子装置,其特征在于,具有顶表面,距所述顶表面一定距离并且与所述顶表面平行的底表面,以及作为沿着垂直于所述顶表面和所述底表面的方向的在所述顶表面和所述底表面之间的所述距离的厚度,所述装置包括:
-半导体裸片,集成了电子部件,具有正面以及与所述正面相对的背面,所述正面具有用于电接入至所述电子部件的第一电接入区域;
-引线框架结构,包括支撑区域,所述支撑区域在对应于所述半导体裸片的背面并且电耦合至所述半导体裸片的背面的区域中容纳所述半导体裸片;
-保护本体,其横向地并且在顶部处围绕所述半导体裸片以及至少部分地围绕所述引线框架结构,从而限定所述电子装置的所述顶表面、所述底表面和所述厚度;以及
-至少一个第一导电引线,电耦合至所述第一电接入区域,
所述第一导电引线被成形为延伸遍布所述保护本体的厚度以用于形成从所述电子装置的顶表面可接入的正面电接触,以及从所述电子装置的底表面可接入的背面电接触。
2.根据权利要求1所述的电子装置,其特征在于,进一步包括,热耦合至所述第一电接入区域的导电薄片,所述导电薄片在对应于所述电子装置的顶表面的区域处朝向所述保护本体的外侧暴露。
3.根据权利要求2所述的电子装置,其特征在于,所述导电薄片进一步电耦合至所述裸片的所述第一电接入区域。
4.根据权利要求1-3中任一项所述的电子装置,其特征在于,在所述裸片的所述正面和所述背面之间的至少一个具有用于电接入至所述电子部件的第二电接入区域,所述电子装置进一步包括与所述第一导电引线电绝缘并且电耦合至所述第二电接入区域的第二导电引线,
其中所述第二导电引线被模制为延伸遍布所述保护本体的厚度以用于形成从所述电子装置的顶表面可接入的相应正面电接触以及从所述电子装置的底表面可接入的相应背面电接触。
5.根据权利要求4所述的电子装置,其特征在于,在所述裸片的所述正面和所述背面之间的另一个具有用于电接入至所述电子部件的第三电接入区域,所述电子装置进一步包括与所述第一导电引线和所述第二导电引线电绝缘并且电耦合至所述第三电接入区域的第三导电引线,
其中所述第三导电引线被成形为延伸遍布所述保护本体的厚度以用于形成从所述电子装置的顶表面可接入的相应正面电接触以及从所述电子装置的底表面可接入的相应背面电接触。
6.根据权利要求1-3中任一项所述的电子装置,其特征在于,所述引线框架结构在对应于所述电子装置的底表面的区域处朝向所述保护本体的外侧暴露,并且电耦合至延伸进入所述裸片的背面中的电接入区域。
7.根据权利要求5所述的电子装置,其特征在于,所述电子部件是MOS晶体管,以及所述第一电接入区域、所述第二电接入区域和所述第三电接入区域是所述MOS晶体管的源极、栅极和漏极。
8.根据权利要求1-3中任一项所述的电子装置,其特征在于,所述第一导电引线包括突出导电部分,所述突出导电部分与其自身的正面电接触和背面电接触一体成型并且以悬臂方式从所述保护本体延伸。
CN201520739701.7U 2014-10-24 2015-09-22 电子装置 Active CN205428897U (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
ITTO2014A000872 2014-10-24
ITTO20140872 2014-10-24

Publications (1)

Publication Number Publication Date
CN205428897U true CN205428897U (zh) 2016-08-03

Family

ID=52273419

Family Applications (3)

Application Number Title Priority Date Filing Date
CN201910635591.2A Pending CN110379718A (zh) 2014-10-24 2015-09-22 具有改进电可接入性的封装结构的电子装置和制造方法
CN201520739701.7U Active CN205428897U (zh) 2014-10-24 2015-09-22 电子装置
CN201510609799.9A Active CN105552039B (zh) 2014-10-24 2015-09-22 具有改进电可接入性的封装结构的电子装置和制造方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201910635591.2A Pending CN110379718A (zh) 2014-10-24 2015-09-22 具有改进电可接入性的封装结构的电子装置和制造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201510609799.9A Active CN105552039B (zh) 2014-10-24 2015-09-22 具有改进电可接入性的封装结构的电子装置和制造方法

Country Status (3)

Country Link
US (1) US9570380B2 (zh)
CN (3) CN110379718A (zh)
DE (1) DE102015116152B4 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI453831B (zh) 2010-09-09 2014-09-21 台灣捷康綜合有限公司 半導體封裝結構及其製造方法
US9966330B2 (en) 2013-03-14 2018-05-08 Vishay-Siliconix Stack die package
US9589929B2 (en) * 2013-03-14 2017-03-07 Vishay-Siliconix Method for fabricating stack die package
US9425304B2 (en) 2014-08-21 2016-08-23 Vishay-Siliconix Transistor structure with improved unclamped inductive switching immunity
JP6582678B2 (ja) * 2015-07-27 2019-10-02 三菱電機株式会社 半導体装置
JP2018139263A (ja) 2017-02-24 2018-09-06 株式会社東芝 半導体パッケージおよびその製造方法
DE102017203432B4 (de) 2017-03-02 2019-09-05 Robert Bosch Gmbh 4Verfahren zum Herstellen eines MEMS-Bauelements und entsprechendes MEMS-Bauelement
IT202000008269A1 (it) 2020-04-17 2021-10-17 St Microelectronics Srl Dispositivo elettronico di potenza incapsulato impilabile per montaggio superficiale e disposizione circuitale
US11848244B2 (en) * 2021-09-30 2023-12-19 Texas Instruments Incorporated Leaded wafer chip scale packages
WO2023149891A1 (en) * 2022-02-04 2023-08-10 Hewlett-Packard Development Company, L.P. Fluidic die assemblies
EP4343833A1 (en) * 2022-09-22 2024-03-27 Kabushiki Kaisha Toshiba Semiconductor device

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0424530B1 (en) * 1988-07-08 1996-10-02 Oki Electric Industry Company, Limited Resin-sealed semiconductor device
KR100214463B1 (ko) 1995-12-06 1999-08-02 구본준 클립형 리드프레임과 이를 사용한 패키지의 제조방법
US6040626A (en) * 1998-09-25 2000-03-21 International Rectifier Corp. Semiconductor package
US6256200B1 (en) * 1999-05-27 2001-07-03 Allen K. Lam Symmetrical package for semiconductor die
US6521982B1 (en) * 2000-06-02 2003-02-18 Amkor Technology, Inc. Packaging high power integrated circuit devices
TW535465B (en) * 2000-05-15 2003-06-01 Hitachi Aic Inc Electronic component device and method of manufacturing the same
US6630726B1 (en) * 2001-11-07 2003-10-07 Amkor Technology, Inc. Power semiconductor package with strap
US20040080028A1 (en) * 2002-09-05 2004-04-29 Kabushiki Kaisha Toshiba Semiconductor device with semiconductor chip mounted in package
JP4173751B2 (ja) 2003-02-28 2008-10-29 株式会社ルネサステクノロジ 半導体装置
US7709935B2 (en) * 2003-08-26 2010-05-04 Unisem (Mauritius) Holdings Limited Reversible leadless package and methods of making and using same
US7315077B2 (en) * 2003-11-13 2008-01-01 Fairchild Korea Semiconductor, Ltd. Molded leadless package having a partially exposed lead frame pad
US7262491B2 (en) 2005-09-06 2007-08-28 Advanced Interconnect Technologies Limited Die pad for semiconductor packages and methods of making and using same
DE102006005420B4 (de) * 2006-02-03 2010-07-15 Infineon Technologies Ag Stapelbares Halbleiterbauteil und Verfahren zur Herstellung desselben
US20080157302A1 (en) 2006-12-27 2008-07-03 Lee Seungju Stacked-package quad flat null lead package
US20090179315A1 (en) * 2008-01-14 2009-07-16 Armand Vincent Jereza Semiconductor Die Packages Having Solder-free Connections, Systems Using the Same, and Methods of Making the Same
US20090230519A1 (en) * 2008-03-14 2009-09-17 Infineon Technologies Ag Semiconductor Device
US20100164078A1 (en) * 2008-12-31 2010-07-01 Ruben Madrid Package assembly for semiconductor devices
JP2011040668A (ja) 2009-08-18 2011-02-24 Shin-Etsu Chemical Co Ltd 光半導体装置
US8115287B2 (en) 2009-12-10 2012-02-14 Stats Chippac Ltd. Integrated circuit packaging system with dual row lead-frame having top and bottom terminals and method of manufacture thereof
JP5452210B2 (ja) 2009-12-21 2014-03-26 株式会社日立製作所 半導体装置及びその製造方法
US8193620B2 (en) 2010-02-17 2012-06-05 Analog Devices, Inc. Integrated circuit package with enlarged die paddle
US8581376B2 (en) * 2010-03-18 2013-11-12 Alpha & Omega Semiconductor Incorporated Stacked dual chip package and method of fabrication
US8163601B2 (en) 2010-05-24 2012-04-24 Alpha & Omega Semiconductor, Inc. Chip-exposed semiconductor device and its packaging method
US8362606B2 (en) * 2010-07-29 2013-01-29 Alpha & Omega Semiconductor, Inc. Wafer level chip scale package
CN103400772B (zh) 2013-08-06 2016-08-17 江阴芯智联电子科技有限公司 先封后蚀芯片正装三维***级金属线路板结构及工艺方法

Also Published As

Publication number Publication date
CN110379718A (zh) 2019-10-25
CN105552039A (zh) 2016-05-04
US9570380B2 (en) 2017-02-14
US20160118320A1 (en) 2016-04-28
DE102015116152A1 (de) 2016-04-28
DE102015116152B4 (de) 2022-05-12
CN105552039B (zh) 2019-08-13

Similar Documents

Publication Publication Date Title
CN205428897U (zh) 电子装置
CN205452265U (zh) 电子功率模块
US5869883A (en) Packaging of semiconductor circuit in pre-molded plastic package
US4855868A (en) Preformed packaging arrangement for energy dissipating devices
US4829403A (en) Packaging arrangement for energy dissipating devices
CN102270615B (zh) 功率半导体装置
CN107006132B (zh) 机电部件以及用于生产机电部件的方法
TWI575617B (zh) An electronic component, an electronic component manufacturing method, and an electronic component manufacturing apparatus
CN103515340B (zh) 电源模块封装和用于制造电源模块封装的方法
US20140264801A1 (en) Semiconductor device
US20100170706A1 (en) Electronic module and method for manufacturing an electronic module
CN101521167A (zh) 半导体装置及半导体装置的制造方法
CN109935574A (zh) 半导体模块和用于生产半导体模块的方法
CN103681543A (zh) 倒装芯片封装的矩阵盖散热器
CN106298700A (zh) 半导体装置
JP6805176B2 (ja) 統合されたクリップ及びリード、並びに、回路をつくる方法
CN104425465A (zh) 电子组件模块和制造该电子组件模块的方法
JP2009200415A (ja) 半導体装置および半導体装置の製造方法
US9691697B2 (en) Semiconductor device and method of manufacturing semiconductor device
KR20180083789A (ko) 회로 부품의 제조 방법 및 회로 부품
CN108417499A (zh) 空腔封装结构及其制造方法
CN111834346A (zh) 晶体管功率模块封装结构及其封装方法
EP3428962B1 (en) Semiconductor device and method for manufacturing semiconductor device
US9159644B2 (en) Manufacturing of DSC type electronic devices by means of spacer insert
CN111769090A (zh) 塑封功率模块、塑封模具及塑封方法

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant