CN103928412A - 半导体装置及制造该半导体装置的方法 - Google Patents

半导体装置及制造该半导体装置的方法 Download PDF

Info

Publication number
CN103928412A
CN103928412A CN201410017774.5A CN201410017774A CN103928412A CN 103928412 A CN103928412 A CN 103928412A CN 201410017774 A CN201410017774 A CN 201410017774A CN 103928412 A CN103928412 A CN 103928412A
Authority
CN
China
Prior art keywords
circuit board
semiconductor device
radiator
metal material
manufacture semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410017774.5A
Other languages
English (en)
Inventor
今村武史
清水敦和
藤本康则
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Publication of CN103928412A publication Critical patent/CN103928412A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05583—Three-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2733—Manufacturing methods by local deposition of the material of the layer connector in solid form
    • H01L2224/27334—Manufacturing methods by local deposition of the material of the layer connector in solid form using preformed layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H01L2224/29191—The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81054—Composition of the atmosphere
    • H01L2224/81075—Composition of the atmosphere being inert
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83053—Bonding environment
    • H01L2224/83054—Composition of the atmosphere
    • H01L2224/83075—Composition of the atmosphere being inert
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/83486—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/83487—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1432—Central processing unit [CPU]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H01L2924/164—Material
    • H01L2924/1659—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/166—Material
    • H01L2924/167—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/16738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/16747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本申请提供了一种半导体装置以及制造该半导体装置的方法，该方法包括：在布线基板上安装第一元件；利用设置在第一散热器和所述第一元件之间的金属材料将所述第一散热器置于所述第一元件上；通过加热并熔化所述金属材料而经由所述金属材料将所述第一散热器附接至所述第一元件；以及在将所述第一散热器附接至所述第一元件的步骤之后，将第二元件安装在所述布线基板上。利用本发明，即使不同类型元件被安装在同一基板上，也能够避免降低半导体装置的可靠性。

Description

半导体装置及制造该半导体装置的方法
技术领域
本文描述的实施例涉及半导体装置以及制造该半导体装置的方法。
背景技术
通过将例如中央处理单元（CPU）等元件安装在基板上而形成的半导体装置被用于例如服务器等电子装置中。减小该电子装置的尺寸和提高该电子装置的性能的一种有利方式是通过将与CPU不同类型的元件安装在同一基板上来提高半导体装置的密度。这样缩减了在多种类型元件之间的布线长度，从而也可减小布线阻抗。
然而，不同类型的元件具有不同的特性，例如热阻。因此，将这些元件安装在同一基板上而不考虑它们的特性可能会降低最终半导体装置的可靠性。
在日本特开专利公开号2011-35352和2011-23587中公开了与本申请相关的技术。
本发明的一个目的是提供一种即使不同类型元件被安装在同一基板上也能够避免降低其可靠性的半导体装置，并提供制造该半导体装置的方法。
发明内容
根据本文描述的一个方案，提供了一种制造半导体装置的方法，包括：在布线基板上安装第一元件；利用设置在第一散热器（heat sink）和所述第一元件之间的金属材料将所述第一散热器置于所述第一元件上；通过加热并熔化所述金属材料而经由所述金属材料将所述第一散热器附接至所述第一元件；以及在将所述第一散热器附接至所述第一元件之后，将第二元件安装在所述布线基板上。
根据本文描述的另一个方案，提供了一种半导体装置，包括：布线基板；处理单元，安装在所述布线基板上；稳压器，安装在所述布线基板上；第一散热器，经由金属材料附接在所述处理单元上；以及第二散热器，经由树脂材料附接至所述稳压器。
根据下述公开内容，在将第一散热器附接至第一元件的步骤之后执行将第二元件安装在布线基板上的步骤。因此，第二元件不会暴露于附接第一散热器时所施加的热能。因此，即使在为了保证半导体装置的可靠性而限定了允许用于第二元件的加热次数上限的情况下，在半导体装置完成之前第二元件被加热的次数多于上限次数的可能性也很小。因此，半导体装置的可靠性被降低的可能性很小。
附图说明
图1A至图1F是本申请发明人研究的制造过程中半导体装置的截面图；
图2A至图2I是根据实施例的制造过程中半导体装置的截面图；
图3A至图3H是根据实施例的制造过程中半导体装置的平面图；
图4是图3E中沿线X6-X6得到的截面图；
图5是图3H中沿线X10-X10得到的截面图；
图6是根据改型实施例的半导体装置的平面图；以及
图7是图6中沿线X11-X11得到的截面图。
具体实施方式
在描述实施例之前，给出对本申请发明人研究的半导体装置的描述。
回流（reflow）方法是将元件安装在布线基板上的技术。在回流方法中，例如焊锡的金属材料被加热且被熔化，以经由该金属材料机械地且电性地将元件的每个电极连接至布线基板的对应电极。
图1A至图1F是利用回流方法的制造过程中半导体装置的截面图。
首先，如图1A所示，焊膏2被印刷在布线基板1的预定位置处。
然后，如图1B所示，电子部件3被置于每个焊膏2上，在此状态下，焊膏2通过回流被熔化。因此，电子部件3经由焊膏2连接至布线基板1。
可用作电子部件3的元件例如是无源元件，例如电容器和电阻元件。
接下来，如图1C所示，将设置有多个焊接凸点6的元件5置于布线基板1上。元件5例如是有源元件，例如中央处理单元（CPU）。
然后，通过回流使焊接凸点6熔化，以经由焊接凸点6将元件5连接至布线基板1。
接着，如图1D所示，在布线基板1和元件5之间的空间填充底部充填树脂（underfill resin）8，且底部充填树脂8被固化，从而加强布线基板1与元件5之间的连接强度。可用作底部充填树脂8的树脂为热固树脂和热塑树脂中的任意一种。
接着，如图1E所示，金属材料11和散热器12被以此顺序置于元件5上。然后，布线基板1的边缘经由黏胶13被接合至散热器12。这里，焊料片被用作金属材料11，且铜板被用作散热器12。
然后，在此状态下，通过回流将金属材料11熔化，从而经由金属材料11将散热器12附接至元件5。
散热器12具有将元件5产生的热散至外部的功能，并且将具有良好导热性的铜或类似物用作散热器12提高了散热器12的散热效果。
具体地，在该示例中，将比其他材料（例如树脂）导热性高的金属材料11用作将散热器12附接至元件5的材料。这样使得热量从元件5顺畅地流到散热器12，从而提高散热器12的散热效果。
此后，如图1F所示，多个焊接凸点被接合至布线基板1的表面以作为外部连接端14，其中该表面是与设置散热器12的一侧相对的。由此，完成了球栅阵列（BGA）半导体装置15的基础结构。
虽然半导体装置15仅设置有一个有源元件（例如CPU）作为元件5，但有效的是，将与元件5不同类型的有源元件安装在布线基板1上以提高半导体装置15的性能。
除CPU之外，可被安装在布线基板1上的有源元件例如是稳压器（regulator）。稳压器是被配置为通过使直流电压平滑而输出恒定电压的元件。当稳压器被安装在布线基板1上时，稳压器和元件5之间的布线长度被缩短。因此，预期布线阻抗得以减小，从而提高半导体装置15的性能。
然而，例如稳压器的有源元件可能会被在回流中施加的热损坏，而这可能会降低有源元件的可靠性。该损坏例如包括，由于元件的密封树脂和电极之间的膨胀系数差异而导致元件的密封树脂从元件的电极脱落的现象。
随着回流次数的增加，可靠性下降更为显著。因此，一些元件制造商限定了回流次数的上限，并建议执行上限次数或者更少次数的回流以保证元件的可靠性。
在该示例中，金属材料11在上述图1F的步骤中经受回流。因此，如果稳压器与元件5一起被安装在布线基板1上，则允许用于稳压器的剩余回流次数减少了一次。这样可能形成风险，即在半导体装置15完成之前稳压器经受多于上限次数的回流。因此，将稳压器与元件5一起安装在布线基板1上同时保持稳压器的可靠性是很困难的。
而且，优选地，散热器12也被附接至稳压器以促进散热。然而，因为与CPU及其类似物相比稳压器消耗较小的电能且产生较少的热量，所以用于将散热器12连接至稳压器的材料并不必须是具有良好导热性的金属材料11。然而，利用金属材料11将例如CPU的元件5附接至散热器12以及利用除金属材料11之外的材料将稳压器附接至散热器12并不容易。
下面描述实施例
（实施例）
图2A-图2I是根据实施例的制造过程中半导体装置的截面图，图3A-图3H是对应的平面图。
在该实施例中，不同类型的元件以下述的方式被安装在单个的布线基板上。
首先，如图2A所示，第一焊膏22被印刷在布线基板21的每个第一电极21a上。可替代地，第一焊膏22也可由分配器施加至第一电极21a。
用于第一焊膏22的材料的示例包括在约183℃熔化的Sn-Pb共晶焊料，以及无铅的、Sn-Ag基焊料，例如在约220℃熔化的Sn-Ag-Cu焊料。
图3A是示出该步骤之后的状态的平面图，上述提及的图2A是图3A中沿线X1-X1得到的截面图。
如图3A所示，第一焊膏22以预定的间隔被涂抹至布线基板21。
接着，如图2B所示，电子部件23被置于第一焊膏22上。然后，在此状态下，第一焊膏22通过回流方法被加热，进而被熔化以经由第一焊膏22将电子部件23连接至布线基板21。例如，在245℃至250℃的基板温度、在氮气气氛中执行回流方法。
进一步地，电子部件23不被具体限定，但是该实施例中电子部件23为例如电容器和电阻元件等无源元件。
图3B是示出在此步骤之后状态的平面图，上述提及的图2B是图3B中沿线X2-X2得到的截面图。
如图3B所示，每个电子部件23在平面图中为矩形的，且在两端处都利用第一焊膏22连接至布线基板21。
接着，如图2C所示，准备设置有多个焊接凸点26的第一元件25，并在利用布线基板21的各个第二电极21b调节焊接凸点26的位置后将第一元件25置于布线基板21上。
第一元件25为有源元件。例如，诸如CPU的处理单元、图形处理单元（GPU）或者微处理单元（MPU）可用作第一元件25。
然后，通过回流方法来加热并熔化焊接凸点26，从而将第一元件25安装在布线基板21上。在该实施例中，在245℃至250℃的基板温度、在氮气气氛中实施回流。
图3C是示出该步骤之后的状态的平面图，且上述提及的图2C是图3C中沿线X3-X3得到的截面图。
如图3C所示，第一元件25在平面图中是矩形的，且被安装在邻近布线基板21的中心处。
然后，如图2D所示，在布线基板21和第一元件25之间的空间中填满底部充填树脂28，然后固化底部充填树脂28，从而加强布线基板21和第一元件25之间的连接强度。底部充填树脂28的示例包括热固树脂和热塑树脂。
图3D是示出该步骤之后的状态的平面图，上述提及的图2D是图3D中沿线X4-X4得到的截面图。
接着，如图2E所示，金属材料31和第一散热器32被顺序地置于第一元件25上。
用于金属材料31和第一散热器32的材料不具体限定。在该实施例中，由在约140℃熔化的In-Ag基焊料制成的焊片被用作金属材料31，铜板被用作第一散热器32。
可选地，由Sn-Pb基焊料制成的焊片可被用作金属材料31，由具有良好导热性的铝碳化硅制成的陶瓷板可代替铜板而被用作第一散热器32。
第一散热器32在挨着第一元件25的部分设置有多个突出部32b，所述突出部32b从第一散热器32的表面突出至接近布线基板21的位置点。
然后，在此状态下，通过回流方法加热并熔化金属材料31，从而经由金属材料31将第一散热器32附接至第一元件25。例如，可在约245℃至250℃的基板温度、在氮气气氛中实施回流。
即使金属材料31由此被熔化，第一散热器32的突出部32b也可阻挡熔化的金属材料31的流动。因此，防止了多个电子部件23经由金属材料31彼此电连接。
在改善第一元件25上的金属材料31的可湿性以及由此增加第一元件25和金属材料31之间的接合强度之前，可在第一元件25上形成金属层25a。例如，顺序堆叠钛膜和金膜形成的复合膜（laminated film）、或者顺序堆叠钛膜、镍膜和金膜而形成的复合膜可被形成为金属层25a。
图3E是示出该步骤之后的状态的平面图，上述提及的图2E是图3E中沿线X5-X5得到的截面图。
如图3E所示，第一散热器32具有在平面图中沿布线基板21的边缘设置的框架32a，并且在框架32a内具有两个开口32c。
在该步骤中利用黏胶33（参见图2E）将框架32a接合至布线基板21的边缘21x，框架32a被用作防止布线基板21翘曲的加固件（stiffener）。
图4是图3E中沿线X6-X6的截面图，且示出了框架32a沿着布线基板21的边缘延伸的部分。
如图4所示，框架32a具有与各开口32c连通的两个凹部32d。
接着，如图2F所示，多个焊接凸点被置为布线基板21的表面上的外部连接端34，其中该表面与设置第一散热器32的一侧相对。然后，在此状态下，外部连接端34通过回流方法被加热并熔化，从而被连接至布线基板21。
该步骤中的回流条件不具体限定。在该实施例中，在约220℃熔化的Sn-Ag-Cu焊料被用作外部连接端34的材料，且在约245℃至250℃的基板温度、在氮气气氛中实施回流。
接着，如图2G所示，第二焊膏35被印刷在布线基板21的每个第三电极21c上。第二焊膏35可由分配器施加。
不具体限定用于第二焊膏35的材料。在该实施例中，与第一焊膏22相似，在约183℃熔化的Sn-Pb共晶焊料被用作第二焊膏35的材料。也可使用在约220℃熔化的Sn-Ag-Cu焊料来代替Sn-Pb共晶焊料。
在图2A中的上述步骤中印刷第一焊膏22的同时可印刷第二焊膏35。然而，为了防止第二焊膏35由于在诸如安装电子部件23（参见图2B）的步骤等步骤中施加的热而润湿和蔓延，优选地如本实施例这样在印刷第一焊膏22之后印刷第二焊膏35。
图3F是示出该步骤之后的状态的平面图，上述提及的图2G是图3F中沿线X7-X7得到的截面图。
接着，如图2H所示，第二元件36被置于第二焊膏35上。然后，在此状态下，第二焊膏35通过回流方法被加热并熔化，从而经由第二焊膏35将第二元件36安装在布线基板21上。
例如，可在约245℃至250℃的基板温度、在氮气气氛中实施回流。
每个第二元件36具有电极36a和密封树脂36b，且通过上述回流将电极36a电连接至第二焊膏35。
进一步地，第二元件36为与第一元件25不同类型的有源元件，例如可以是稳压器、存储器等。
如前所述，当例如稳压器的有源元件反复经受回流时，有源元件的可靠性可能降低，例如是因为密封树脂36b可能从电极36a脱落。因此，为了保证第二元件36的可靠性，一些制造商限定了第二元件36上回流次数的上限，且优选地执行不超过上限的回流。
注意，对回流次数的这种限制旨在针对被加热至温度等于或大于基板温度（245℃至250℃）的这种回流，在该步骤中第二元件36在该基板温度被安装，且第二元件36不会被低于该基板温度的温度损坏。因此，在该实施例中，在该步骤之后第二元件36被保持在低于基板温度（245℃至250℃）的温度，直至半导体装置完成，从而第二元件36的可靠性不会被降低。
图3G是示出该步骤之后的状态的平面图，且上述提及的图2H是图3G中沿线X8-X8的截面图。
如图3G所示，第一散热器32的每个开口32c具有在平面图中能够包括第二元件36的尺寸，且第二元件36暴露在开口32c中。
随后，如图2I所示，经由热固树脂材料41将第二散热器42置于每个第二元件36上。然后，在此状态下，树脂材料41被加热并固化，从而经由树脂材料41将第二散热器42附接至第二元件36。
树脂材料41不被具体限定，但优选地是具有低于金属材料31熔点的热固化温度的树脂，从而在热固化中减少对第二元件36的损坏。
在这种情况下，用于加热树脂材料41的温度可被设置为低于金属材料31的熔点，且在该实施例中，树脂材料41在约150℃的基板温度被固化。这种温度水平几乎不会损坏第二元件36，且该步骤不会减少允许用于第二元件36的回流的剩余次数。
第二散热器42用于将第二元件36产生的热量散至外部，且与第一散热器32相似，第二散热器42可以为铜板或由铝碳化硅制成的陶瓷板等。
用于树脂材料41的材料也不被具体限定。为了快速将热量从第二元件36转移至第二散热器42，优选地由具有良好导热性的硅树脂作为树脂材料41。
相比于例如为处理单元的第一元件25，用作第二元件36的稳压器等消耗较少电能且产生较少热量。因此，即使使用的树脂材料41的导热性低于金属材料31的导热性，也能够获得足够的散热效果。
图3H是示出该步骤之后的状态的平面图，且上述提及的图2I是图3H中沿线X9-X9得到的截面图。
如图3H所示，每个第二散热器42在平面图中为矩形，且覆盖第一散热器32的每个开口32c。
图5是图3H中沿线X10-X10得到的截面图。
如图5所示，在该步骤中，第二散热器42通过上述树脂材料41被接合至对应的凹部32d，从而由框架32a稳定地支撑。
通过上述完成了根据该实施例的半导体装置49的基础结构。
根据上述的实施例，在图2E中的步骤中将第一散热器32固定至第一元件25之后，在图2H的步骤中将第二元件36安装在布线基板21上。
据此，第二元件36不会暴露于在图2E的步骤中在金属材料31上执行回流时所施加的热能。因此，即使在为了保证第二元件36的可靠性而限定了用于在第二元件36上执行回流的次数上限的情况下，在完成半导体装置49之前在第二元件36上执行回流的次数超出上限的可能性很小。因此，第一元件25以及与第一元件25不同类型的第二元件36可被安装在布线基板21上，同时保持第二元件36的可靠性。因此，可提高半导体装置49的性能。
虽然在将外部连接端34连接至布线基板21的步骤（参见图2F）中以及在布线基板21上安装电子部件36的步骤（参见图2H）中实施回流，但是在该实施例中是在这些步骤之后将第二元件36安装在布线基板21上。因此，第二元件36不会暴露于回流中施加的热能，且防止了因这些步骤减少允许用于第二元件36的回流的剩余次数。
而且，在图2I中的步骤中，利用不需要任何回流的树脂材料41将第二散热器42附接至第二元件36。因此，该步骤没有浪费允许用于第二元件36的回流的次数。
而且，利用除第一散热器32以外的第二散热器42，使得用金属材料31将第一元件25附接至第一散热器32以及用树脂材料41将第二元件36附接至第二散热器42变得容易。
以上详细描述了实施例，但实施例并不限于以上所描述的。
图6是根据改型实施例的半导体装置的平面图，图7是图6中沿线X11-X11得到的截面图。
如图6和图7所示，在半导体装置50中，没有设置第二散热器42，且因此第二元件36是暴露的。如果第二元件36产生少量的热，则半导体装置50可具有将热量从第二元件36直接散至空气中的结构，而不需要在其中设置第二散热器42。
而且，当布线基板21的翘曲不成问题时，可省去用作加固件的第一散热器32的框架32a，且第一散热器32可在其突出部32b（参见图6）处被接合至布线基板21，如图6和图7中的示例所示。

Claims (14)

1.一种制造半导体装置的方法，包括：
在布线基板上安装第一元件；
利用设置在第一散热器和所述第一元件之间的金属材料将所述第一散热器置于所述第一元件上；
通过加热并熔化所述金属材料而经由所述金属材料将所述第一散热器附接至所述第一元件；以及
在将所述第一散热器附接至所述第一元件之后，将第二元件安装在所述布线基板上。
2.如权利要求1所述的制造半导体装置的方法，还包括：
在将所述第二元件安装在所述布线基板上之后，经由树脂材料将第二散热器附接在所述第二元件上。
3.如权利要求2所述的制造半导体装置的方法，其中，
在将所述第二散热器附接在所述第二元件上时所使用的树脂材料是热固材料，且通过在低于所述金属材料的熔点的温度被加热而固化。
4.如权利要求2或3所述的制造半导体装置的方法，其中，
所述第一散热器包括在平面图中沿着所述布线基板的边缘设置的框架，以及
所述方法还包括：
将所述框架接合至所述边缘。
5.如权利要求1至3中任意一项所述的制造半导体装置的方法，还包括：
在将所述第一散热器置于所述第一元件上之前，在所述第一元件上形成金属层。
6.如权利要求1至3中任意一项所述的制造半导体装置的方法，其中，
所述第一散热器的在所述第一元件旁边的表面设置有延伸靠近所述布线基板的突出部。
7.如权利要求1至3中任意一项所述的制造半导体装置的方法，其中，
所述第二元件比所述第一元件消耗的电能少。
8.如权利要求1至3中任意一项所述的制造半导体装置的方法，其中，
所述第一元件为第一有源元件；以及
所述第二元件为第二有源元件。
9.如权利要求8所述的制造半导体装置的方法，其中，
所述第一元件为处理单元；以及
所述第二元件为稳压器。
10.如权利要求1至3中任意一项所述的制造半导体装置的方法，还包括：
在安装所述第二元件之前，通过加热并熔化焊料而经由所述焊料将电子部件连接至所述布线基板。
11.如权利要求1至3中任意一项所述的制造半导体装置的方法，还包括：
在安装所述第二元件之前，通过加热并熔化外部连接端将所述外部连接端连接至所述布线基板。
12.一种半导体装置，包括：
布线基板；
处理单元，安装在所述布线基板上；
稳压器，安装在所述布线基板上；
第一散热器，经由金属材料附接在所述处理单元上；以及
第二散热器，经由树脂材料附接至所述稳压器。
13.如权利要求12所述的半导体装置，其中，
所述第一散热器包括在平面图中沿着所述布线基板的边缘设置的框架；以及
所述框架接合至所述边缘。
14.如权利要求13所述的半导体装置，其中，
所述第二散热器接合至所述框架。
CN201410017774.5A 2013-01-15 2014-01-15 半导体装置及制造该半导体装置的方法 Pending CN103928412A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013-004465 2013-01-15
JP2013004465A JP6056490B2 (ja) 2013-01-15 2013-01-15 半導体装置とその製造方法

Publications (1)

Publication Number Publication Date
CN103928412A true CN103928412A (zh) 2014-07-16

Family

ID=51146586

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410017774.5A Pending CN103928412A (zh) 2013-01-15 2014-01-15 半导体装置及制造该半导体装置的方法

Country Status (3)

Country Link
US (2) US9224711B2 (zh)
JP (1) JP6056490B2 (zh)
CN (1) CN103928412A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107006138A (zh) * 2014-12-12 2017-08-01 名幸电子有限公司 模制电路模块及其制造方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6314731B2 (ja) * 2014-08-01 2018-04-25 株式会社ソシオネクスト 半導体装置及び半導体装置の製造方法
CN106796923B (zh) * 2014-09-27 2020-05-05 英特尔公司 多芯片自调整冷却解决方案
JP6421050B2 (ja) * 2015-02-09 2018-11-07 株式会社ジェイデバイス 半導体装置
US10312174B2 (en) * 2016-08-29 2019-06-04 Apple Inc. Thermal management system
WO2019040753A1 (en) * 2017-08-23 2019-02-28 Georgia Tech Research Corporation DIRECT LOW TEMPERATURE CONNECTION OF ALUMINUM NITRIDE TO ALSIC SUBSTRATES
CN113380636B (zh) * 2021-04-29 2024-03-26 苏州通富超威半导体有限公司 一种焊接方法及芯片封装方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4696101A (en) * 1985-06-07 1987-09-29 Vanzetti Systems, Inc. Method and apparatus for placing and electrically connecting components on a printed circuit board
JP2003289189A (ja) * 2002-03-28 2003-10-10 Toshiba Corp 電子機器
US20040118500A1 (en) * 2002-12-24 2004-06-24 Sung-Fei Wang [heat sink for chip package and bonding method thereof]
US20090115037A1 (en) * 2007-11-01 2009-05-07 National Semiconductor Corporation Integrated circuit package with integrated heat sink
CN102291933A (zh) * 2010-06-18 2011-12-21 新光电气工业株式会社 布线基板及其制造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07321257A (ja) * 1994-05-20 1995-12-08 Hitachi Ltd マルチチップモジュール
JP2758883B2 (ja) * 1996-06-17 1998-05-28 静岡日本電気株式会社 放熱器
JP2001127218A (ja) * 1999-10-29 2001-05-11 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
JP2001358452A (ja) * 2000-06-15 2001-12-26 Murata Mfg Co Ltd 電子部品の実装方法
JP2007005670A (ja) * 2005-06-27 2007-01-11 Fujitsu Ltd 電子部品パッケージおよび接合組立体
JP2007184351A (ja) * 2006-01-05 2007-07-19 Nec Electronics Corp 半導体装置及びその製造方法
JP4910439B2 (ja) * 2006-03-23 2012-04-04 富士通セミコンダクター株式会社 半導体装置
KR101089084B1 (ko) * 2007-12-28 2011-12-06 이비덴 가부시키가이샤 인터포저 및 인터포저의 제조 방법
US20100019379A1 (en) * 2008-07-24 2010-01-28 Broadcom Corporation External heat sink for bare-die flip chip packages
JP2011023587A (ja) * 2009-07-16 2011-02-03 Shinko Electric Ind Co Ltd 半導体装置
JP2011035352A (ja) * 2009-08-06 2011-02-17 Fujitsu Semiconductor Ltd 半導体装置
US8093714B2 (en) * 2009-12-10 2012-01-10 Semtech Corporation Chip assembly with chip-scale packaging
CN102683221B (zh) * 2011-03-17 2017-03-01 飞思卡尔半导体公司 半导体装置及其组装方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4696101A (en) * 1985-06-07 1987-09-29 Vanzetti Systems, Inc. Method and apparatus for placing and electrically connecting components on a printed circuit board
JP2003289189A (ja) * 2002-03-28 2003-10-10 Toshiba Corp 電子機器
US20040118500A1 (en) * 2002-12-24 2004-06-24 Sung-Fei Wang [heat sink for chip package and bonding method thereof]
US20090115037A1 (en) * 2007-11-01 2009-05-07 National Semiconductor Corporation Integrated circuit package with integrated heat sink
CN102291933A (zh) * 2010-06-18 2011-12-21 新光电气工业株式会社 布线基板及其制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107006138A (zh) * 2014-12-12 2017-08-01 名幸电子有限公司 模制电路模块及其制造方法
CN107006138B (zh) * 2014-12-12 2019-07-05 名幸电子有限公司 模制电路模块及其制造方法

Also Published As

Publication number Publication date
JP6056490B2 (ja) 2017-01-11
US20160071782A1 (en) 2016-03-10
US9224711B2 (en) 2015-12-29
JP2014138018A (ja) 2014-07-28
US9721866B2 (en) 2017-08-01
US20140197533A1 (en) 2014-07-17

Similar Documents

Publication Publication Date Title
CN103928412A (zh) 半导体装置及制造该半导体装置的方法
CN103219299B (zh) 集成电路封装组件及其形成方法
US8866309B2 (en) Chip package structure
US20150187679A1 (en) Lid Design for Heat Dissipation Enhancement of Die Package
EP2477223B1 (en) Method of manufacturing a semiconductor apparatus
CN106684057B (zh) 芯片封装结构及其制造方法
US9324684B2 (en) Semiconductor device and manufacturing method thereof
CN104134636A (zh) 用于半导体模块的直接冷却衬底和相应的制造方法
KR102004785B1 (ko) 반도체모듈 패키지 및 그 제조 방법
CN101821848A (zh) 用于有效热量耗散的无线半导体封装
CN205004324U (zh) 一种智能功率模块芯片
CN101752358A (zh) 带有整合旁路电容器的紧密半导体封装及其方法
CN107078118A (zh) ***器到封装基板的耦合
CN101652856A (zh) 用于改良热性能的具有焊接盖的集成电路封装
WO2012060054A1 (ja) 回路装置およびその製造方法
CN109994433A (zh) 半导体装置封装
JPS622587A (ja) ハイパワ−用混成集積回路
CN103050454A (zh) 堆迭封装构造
CN114649323A (zh) 半导体封装结构及其制备方法
JP2013004912A (ja) 半導体モジュール
CN102403436B (zh) 半导体发光元件的散热座的制作方法
CN214588826U (zh) 半导体器件结构
JP2019121679A (ja) 電子装置及び電子装置の製造方法
CN212322992U (zh) 一种封装基板、封装结构及线路板的焊接结构
CN117766482A (zh) 一种芯片封装结构、封装模组和电子设备

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: SUOSI FUTURE CO., LTD.

Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR CO., LTD.

Effective date: 20150515

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20150515

Address after: Yokohama City, Kanagawa Prefecture, Japan

Applicant after: Co., Ltd. Suo Si future

Address before: Yokohama City, Kanagawa Prefecture, Japan

Applicant before: Fujitsu Semiconductor Co., Ltd.

RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20140716