JP4910439B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4910439B2 JP4910439B2 JP2006080578A JP2006080578A JP4910439B2 JP 4910439 B2 JP4910439 B2 JP 4910439B2 JP 2006080578 A JP2006080578 A JP 2006080578A JP 2006080578 A JP2006080578 A JP 2006080578A JP 4910439 B2 JP4910439 B2 JP 4910439B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- heat
- semiconductor device
- wiring board
- heat spreader
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
かかる構造により、半導体素子1とヒートスプレッダ20は、両者の間に配設された半田合金7により熱的に結合され、半導体素子1に於いて発生した熱はヒートスプレッダ20に有効に伝達される。
本発明の第1の実施の形態にかかる半導体装置について、図2乃至図11を参照して説明する。
図12乃至図16を参照して、本発明の第2の実施の形態にかかる半導体装置について説明する。
(付記1)支持基板と、
前記支持基板の一方の主面に搭載された半導体素子と、
前記半導体素子に熱伝導部が接続された放熱体と
を具備し、
前記半導体素子は、前記支持基板の前記一方の主面に設けられた凹部に於いて当該支持基板に搭載され、
前記半導体素子と前記放熱体の前記熱伝導部は熱伝導材料を介して接続され、
前記支持基板の凹部内に於いて、前記半導体素子を囲繞して、壁状部材が配設されてなることを特徴とする半導体装置。
(付記2)前記壁状部材は、前記半導体素子の側面を囲繞して配設されてなることを特徴とする付記1記載の半導体装置。
(付記3)前記壁状部材は、前記放熱体の熱伝導部の周囲に配設されてなることを特徴とする付記1記載の半導体装置。
(付記4)前記壁状部材には、選択的に貫通部が配設されてなることを特徴とする付記1記載の半導体装置。
(付記5)前記支持基板の、前記一方の主面に設けられた凹部の周囲には、前記半導体素子と電気的に接続される受動素子が搭載されてなることを特徴とする付記1記載の半導体装置。
(付記6)前記半導体素子は、その主面を支持基板に対向させて、当該支持基板の凹部内に搭載されてなることを特徴とする付記1記載の半導体装置。
(付記7)前記放熱体の熱伝導部は、熱伝導材料を介して前記半導体素子の背面に接続されてなることを特徴とする付記1記載の半導体装置。
(付記8)前記半導体素子と前記放熱体の熱伝導部は、融点の低い熱伝導材料を介して接続されてなることを特徴とする付記1記載の半導体装置。
(付記9)前記壁状部材は、前記熱伝導部と一体に放熱体に配設されてなることを特徴とする付記1記載の半導体装置。
31 半導体素子
32 配線基板
35 熱伝導面
36 半田合金
40、60、70、90、110、130 ヒートスプレッダ
44、61、94、111、134 壁部
47 凹部
62、112 貫通孔
Claims (4)
- 支持基板と、
前記支持基板の一方の主面に搭載された半導体素子と、
前記半導体素子に熱伝導部が接続された放熱体と
を具備し、
前記半導体素子は、前記支持基板の前記一方の主面に設けられた凹部に於いて当該支持基板に搭載され、
前記半導体素子と前記放熱体の前記熱伝導部は熱伝導材料を介して接続され、
前記支持基板の凹部内に於いて、前記半導体素子を囲繞して、壁状部材が配設され、
前記壁状部材には、選択的に貫通部が配設されてなることを特徴とする半導体装置。 - 前記壁状部材は、前記半導体素子の側面を囲繞して配設されてなることを特徴とする請求項1記載の半導体装置。
- 前記壁状部材は、前記放熱体の熱伝導部の周囲に配設されてなることを特徴とする請求項1記載の半導体装置。
- 前記支持基板の、前記一方の主面に設けられた凹部の周囲には、前記半導体素子と電気的に接続される受動素子が搭載されてなることを特徴とする請求項1記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006080578A JP4910439B2 (ja) | 2006-03-23 | 2006-03-23 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006080578A JP4910439B2 (ja) | 2006-03-23 | 2006-03-23 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007258430A JP2007258430A (ja) | 2007-10-04 |
JP4910439B2 true JP4910439B2 (ja) | 2012-04-04 |
Family
ID=38632368
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006080578A Expired - Fee Related JP4910439B2 (ja) | 2006-03-23 | 2006-03-23 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4910439B2 (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009246319A (ja) * | 2008-04-01 | 2009-10-22 | Fujikura Ltd | ヒートスプレッダーおよびその製造方法 |
JP2011054640A (ja) * | 2009-08-31 | 2011-03-17 | Funai Electric Co Ltd | シールドパッケージ基板 |
US8617926B2 (en) * | 2010-09-09 | 2013-12-31 | Advanced Micro Devices, Inc. | Semiconductor chip device with polymeric filler trench |
JP5799541B2 (ja) | 2011-03-25 | 2015-10-28 | 株式会社ソシオネクスト | 半導体装置及びその製造方法 |
JP2013115083A (ja) * | 2011-11-25 | 2013-06-10 | Fujitsu Semiconductor Ltd | 半導体装置及びその製造方法 |
JP6056490B2 (ja) * | 2013-01-15 | 2017-01-11 | 株式会社ソシオネクスト | 半導体装置とその製造方法 |
JP5892184B2 (ja) * | 2014-03-18 | 2016-03-23 | トヨタ自動車株式会社 | 半導体装置及び半導体装置の製造方法 |
JP6582669B2 (ja) | 2015-07-22 | 2019-10-02 | Tdk株式会社 | 薄膜キャパシタ及び半導体装置 |
WO2018079328A1 (ja) * | 2016-10-31 | 2018-05-03 | オリンパス株式会社 | 撮像ユニット、及び内視鏡システム |
JP6867243B2 (ja) * | 2017-06-26 | 2021-04-28 | 新光電気工業株式会社 | 放熱板及びその製造方法と電子部品装置 |
DE112021005939T5 (de) | 2020-11-13 | 2023-09-21 | Hitachi Astemo, Ltd. | Elektronische Vorrichtung und Verfahren zur Herstellung einer elektronischen Vorrichtung |
CN117178354A (zh) * | 2021-04-20 | 2023-12-05 | 日立安斯泰莫株式会社 | 车载装置 |
KR20240004533A (ko) * | 2021-04-28 | 2024-01-11 | 소니 세미컨덕터 솔루션즈 가부시키가이샤 | 반도체 장치 |
JP7242824B1 (ja) | 2021-12-16 | 2023-03-20 | レノボ・シンガポール・プライベート・リミテッド | 放熱構造および電子機器 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05183076A (ja) * | 1992-01-07 | 1993-07-23 | Fujitsu Ltd | 半導体パッケージ |
JP2828055B2 (ja) * | 1996-08-19 | 1998-11-25 | 日本電気株式会社 | フリップチップの製造方法 |
JP3703969B2 (ja) * | 1998-06-22 | 2005-10-05 | 松下電器産業株式会社 | 電子回路装置及びその製造方法 |
JP2001308215A (ja) * | 2000-04-24 | 2001-11-02 | Ngk Spark Plug Co Ltd | 半導体装置 |
JP2003229521A (ja) * | 2002-02-01 | 2003-08-15 | Hitachi Ltd | 半導体モジュール及びその製造方法 |
-
2006
- 2006-03-23 JP JP2006080578A patent/JP4910439B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2007258430A (ja) | 2007-10-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4910439B2 (ja) | 半導体装置 | |
JP4764159B2 (ja) | 半導体装置 | |
TWI613774B (zh) | 功率覆蓋結構及其製造方法 | |
KR100698526B1 (ko) | 방열층을 갖는 배선기판 및 그를 이용한 반도체 패키지 | |
US9214403B2 (en) | Stacked semiconductor package | |
JP5573645B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
US6657311B1 (en) | Heat dissipating flip-chip ball grid array | |
US9922902B2 (en) | Semiconductor device and semiconductor package | |
EP1796163B1 (en) | Semiconductor device and electronic control unit using the same | |
KR20080014004A (ko) | 인터포저 및 반도체 장치 | |
JPH0964099A (ja) | 半導体装置及びその実装構造 | |
KR20030021895A (ko) | 열 방출판이 부착된 플립칩 패키지 제조 방법 | |
US8598701B2 (en) | Semiconductor device | |
JP2012191002A (ja) | 半導体装置 | |
TWI286832B (en) | Thermal enhance semiconductor package | |
JP5285204B2 (ja) | 半導体装置及び半導体装置製造用基板 | |
JP2000232186A (ja) | 半導体装置およびその製造方法 | |
JP2008243966A (ja) | 電子部品が実装されたプリント基板及びその製造方法 | |
JP4952365B2 (ja) | 両面実装回路基板に対する電子部品の実装構造、半導体装置、及び両面実装半導体装置の製造方法 | |
CN111213234B (zh) | 半导体组装件 | |
JP2005026373A (ja) | 放熱構造を備えた電子部品 | |
KR100952850B1 (ko) | 개선된 열 에너지 소산을 가진 인쇄 회로 기판 어셈블리 | |
JP4193702B2 (ja) | 半導体パッケージの実装構造 | |
JP2008166711A (ja) | 半導体装置およびその製造方法並びに半導体装置の実装構造 | |
JP2012199283A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20080729 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20081212 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20101012 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110927 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111122 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20111220 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120102 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4910439 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150127 Year of fee payment: 3 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |