CN103825580B - Anti-single particle upset and the setable Scan Architecture d type flip flop of single-ion transient state - Google Patents
Anti-single particle upset and the setable Scan Architecture d type flip flop of single-ion transient state Download PDFInfo
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- CN103825580B CN103825580B CN201310671682.4A CN201310671682A CN103825580B CN 103825580 B CN103825580 B CN 103825580B CN 201310671682 A CN201310671682 A CN 201310671682A CN 103825580 B CN103825580 B CN 103825580B
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Abstract
The invention discloses anti-single particle upset and the setable Scan Architecture d type flip flop of single-ion transient state, it is therefore an objective to solve setable Scan Architecture d type flip flop anti-single particle upset ability and the highest problem of anti-single particle transient state ability.The present invention is by buffer circuit, scan control buffer circuit, set buffer circuit, clock circuit, main latch, form from latch and output buffer.Main latch and from latch be redundancy reinforce latch.Main latch and from series of latches, and be all connected with clock circuit, set buffer circuit.Main latch is also connected with buffer circuit, scan control buffer circuit, is also connected with output buffer from latch.Separate main latch and the C being mutually redundant from latch2MOS circuit improves primary particle inversion resistant ability.Buffer circuits makes not make a mistake under long-term single event transient pulse, and duplication redundancy path further increases the ability of anti-single particle transient state.
Description
Technical field
The present invention relates to a kind of set structure and the D master-slave flip-flop of Scan Architecture, particularly to a kind of anti-list
Particle upset (Single Event Upset, SEU) and anti-single particle transient state (Single Event Transient,
SET) setable Scan Architecture d type flip flop.
Background technology
Cosmic space exists a large amount of high energy particle (proton, electronics, heavy ion etc.), in integrated circuit time
Sequence circuit is by after these high-energy particle bombardments, and its state kept is likely to occur upset, and this effect is referred to as
Single event upset effecf, the LET(linear energy transfer of single-particle bombardment integrated circuit) value is the highest, more holds
It is easily generated Single event upset effecf.Combinational circuit in integrated circuit is by, after these high-energy particle bombardments, having
May produce transient electrical pulses, this effect is referred to as single-ion transient state effect, the LET of single-particle bombardment integrated circuit
Being worth the highest, the transient electrical pulses persistent period of generation is the longest, and electric pulse is the easiest to be gathered by sequence circuit.As
Really the state of sequence circuit makes a mistake upset, or the transient electrical pulses that produces of single-ion transient state effect by time
Sequence circuit error gathers, and integrated circuit operation instability all can be caused even to produce fatal mistake, and this is in boat
My god, military field is particularly acute.Therefore, integrated circuit is reinforced thus reduce Single event upset effecf
More and more important with single-ion transient state effect.
D type flip flop is to use one of most timing unit in integrated circuit, the upset of its anti-single particle and simple grain
The anti-single particle of whole integrated circuit is overturn by the ability of sub-transient state and the ability of single-ion transient state plays crucial work
With, d type flip flop is reinforced accordingly anti-single particle upset and the single-ion transient state energy that can make integrated circuit
Power is improved.
Traditional d type flip flop is D master-slave flip-flop, typically by main latch with from level series of latches structure
Become.Common lock storage is replaced with DICE(Dual Interlocked Storage Cell, dual interlocked storage cell)
Primary particle inversion resistant d type flip flop can be realized etc. redundancy ruggedized construction.Transform input and output on this basis
Port, it is possible to achieve anti-single particle upset simultaneously and single-ion transient state.M.J.Myjak et al. is at The47th
IEEE International Midwest Symposium the 47th IEEE electricity of on Circuits and Systems(
Road and the international conference of system Midwest) on " the Enhanced Fault-Tolerant CMOS Memory that delivers
Elements " (strengthening fault-tolerant cmos memory cell) (2004, the I-453～I-456 page) upper proposition
The DICE circuit of a kind of improvement, this circuit uses DICE circuit to carry out anti-single particle upset and reinforces, and handle
Bidirectional data line divide into two write data lines and two read data lines, by the duplication redundancy of data wire, makes
Travel to the single event transient pulse of DICE circuit by a certain data wire at any time and be difficult to cause whole
The upset of individual circuit state, thus realize the reinforcing for single-ion transient state.But the duplication redundancy of data wire
There is positive feedback loop, latch information upset can be produced under the single event transient pulse of longer duration,
Anti-single particle transient state ability is the highest.
D.G.Mavis etc. are in IEEE Reliability Physics Symposium(world Reliability Physics meeting)
On " the Soft error rate mitigation techniques for modern microcircuits " that deliver (reduce existing
Technology for microcircuit soft error rate) (2002 page 216 page-225) propose time sampling D touch
Send out device circuit.This circuit introduces delay and voting circuit in the feedback loop of latch data, thus possesses
Certain anti-single particle upset and single-ion transient state ability.But voting circuit itself does not possess anti-single particle transient state
Ability, under single event transient pulse can output error data, anti-single particle transient state ability is the highest.
The Chinese patent of Application No. 200910046337.5 discloses a kind of anti-single particle upset and single-particle wink
The d type flip flop of state pulse.This invention is a kind of d type flip flop being similar to that time sampling structure, including
Two variable connectors, two delay circuits, two protection gate circuits and three phase inverters, it is achieved that D triggers
The anti-single particle upset of device and the reinforcing of single-ion transient state.This patent has the ability of anti-single particle transient state, but
Outfan Q due to the 3rd reverser connects the input VIN0 of second variable connector, defines positive and negative
It is fed back to road, latch information upset, anti-single particle can be produced under the single event transient pulse of longer duration
Transient state ability is the highest.
Common D master-slave flip-flop is unfavorable for detecting circuit at test phase so that test job becomes
The most loaded down with trivial details, complicated.Scan Architecture is added on common D master-slave flip-flop architecture basics, can be effective
Ground simplifies circuit test work, i.e. can control the defeated of D master-slave flip-flop by scanning signal at test phase
Enter, and then control circuit state.
Some integrated circuit needs to control the state of d type flip flop in integrated circuit, forces d type flip flop output low
Level and the data wherein stored are set to logical one.At Scan Architecture d type flip flop original structure base
Increase setting circuit and set signal input part on plinth, it is possible to achieve the set structure of d type flip flop, and pass through
Set signal controls the set function of d type flip flop.But the most setable anti-list of Scan Architecture d type flip flop
Particle upset and anti-single particle transient state ability are the highest, are unfavorable for the ic core in fields such as Aeronautics and Astronautics
Sheet uses.
The Chinese patent of Application No. 201110323794.1 discloses a kind of primary particle inversion resistant setable
Scan Architecture d type flip flop, as it is shown in figure 1, this invention by clock circuit, main latch, from latch,
Scan control buffer circuit, output buffer form, can under the single-particle of higher LET value bombards just
Often work and do not produce single-particle inversion.Owing to this invention does not use in clock circuit, before main latch
Buffer circuit, so not possessing the ability of anti-single particle transient state, and main latch, is provided without from latch
Duplication redundancy, when the LET value of single-particle bombardment is higher, some node upset on circuit then can cause
Whole circuit overturns.
Summary of the invention
The technical problem to be solved in the present invention is, for the current setable anti-list of Scan Architecture d type flip flop
Particle upset ability and the highest problem of anti-single particle transient state, propose a kind of anti-single particle upset and single-particle wink
The setable Scan Architecture d type flip flop of state.
Concretism of the present invention is: carries out duplication redundancy reinforcing to main latch with from latch, can resist list
Particle overturns；In clock circuit, add buffer circuit in setting circuit and before main latch, list can be resisted
Particle transient state；Cut off the positive feedback loop that may be caused from latch, Ke Yi by single event transient pulse
Do not overturn under the single event transient pulse of longer duration.
The setable Scan Architecture d type flip flop of anti-single particle of the present invention upset and single-ion transient state is by buffering electricity
Road, scan control buffer circuit, set buffer circuit, clock circuit, main latch, from latch,
One output buffer, the second output buffer composition.Main latch and from latch be redundancy reinforce
Latch.Main latch and from latch tandem, and all with clock circuit, set buffer circuit even
Connect.Main latch is also connected with buffer circuit, scan control buffer circuit, also exports with first from latch
Buffer circuit, the second output buffer are connected.
The setable Scan Architecture d type flip flop of anti-single particle of the present invention upset and anti-single particle transient state has five
Input and two outfans.Five inputs are clock signal input terminal CK, data signal input respectively
D, scan control signal input SE, scan data input SI and set signal input part SN；Output
End is Q and QN.
Clock circuit has an input and four outfans, and input is CK, outfan is c1, c2, cn1,
cn2.Clock circuit is made up of 12 PMOS and 14 NMOS.The grid of the 53rd PMOS
Pole Pg53 connects CK, drain electrode Pd53 and connects the drain electrode Nd53 of the 53rd NMOS tube；54th
The grid Pg54 of PMOS connects the drain electrode Pd53 of the 53rd PMOS, drain electrode Pd54 and connects the 5th
The drain electrode Nd54 of 14 NMOS tube, source electrode Ps54 connect power vd D；55th PMOS
Grid Pg55 connects the drain electrode Pd54 of the 54th PMOS, drain electrode Pd55 and connects the 55th NMOS
The drain electrode Nd55 of pipe, source electrode Ps55 connect power vd D；The grid Pg56 of the 56th PMOS is even
Meet the drain electrode Pd55 of the 55th PMOS, drain electrode Pd56 and connect the drain electrode of the 56th NMOS tube
Nd56, source electrode Ps56 connect power vd D；The grid Pg57 of the 57th PMOS connects CK, leakage
Pole Pd57 connects the source electrode Ps58, source electrode Ps57 of the 58th PMOS and connects VDD；58th
The grid Pg58 of PMOS connects the drain electrode Pd56 of the 56th PMOS, drain electrode Pd58 and connects the 5th
The drain electrode Nd57 of 17 NMOS tube, and as an outfan cn1, the source electrode Ps58 company of clock circuit
Meet Pd57；The grid Pg59 of the 59th PMOS connects CK, drain electrode Pd59 and connects the 60th PMOS
The source electrode Ps60 of pipe, source electrode Ps59 connect VDD；The grid Pg60 of the 60th PMOS connects the 50th
The drain electrode Pd56 of six PMOS, drain electrode Pd60 connect the drain electrode Nd59 of the 59th NMOS tube and make
An outfan cn2, source electrode Ps60 for clock circuit connect Pd59；The grid of the 61st PMOS
Pg61 connects the drain electrode of the 58th PMOS as an outfan c1 of clock circuit, drain electrode Pd61
Pd58, and connect outfan cn1, source electrode Ps61 connects VDD；The grid Pg62 of the 62nd PMOS
Connecting the grid Ng62 of the 62nd NMOS tube and as an outfan c2 of clock circuit, drain Pd62
Connect the drain electrode Nd62 of the 62nd NMOS tube and as an outfan cn2 of clock circuit, source electrode
Ps62 connects VDD；The grid Pg63 of the 63rd PMOS connects outfan cn1, and drain electrode Pd63 is even
Meet outfan c1, source electrode Ps63 and connect VDD；The grid Pg64 of the 64th PMOS connects outfan
Cn2, drain electrode Pd64 connect outfan c2, source electrode Ps64 and connect VDD；The grid of the 53rd NMOS tube
Pole Ng53 connects CK, drain electrode Nd53 and connects the drain electrode Pd53 of the 53rd PMOS；54th
The grid Ng54 of NMOS tube connects the drain electrode Nd53 of the 53rd NMOS tube, drain electrode Nd54 and connects the
The drain electrode Pd54 of 54 PMOS, source electrode Ns54 connect VSS；The grid of the 55th NMOS tube
Ng55 connects the drain electrode Nd54 of the 54th NMOS tube, drain electrode Nd55 and connects the 55th PMOS
Drain electrode Pd55, source electrode Ns55 connect VSS；The grid Ng56 of the 56th NMOS tube connects the 5th
The drain electrode Nd55 of 15 NMOS tube, drain electrode Nd56 connect the drain electrode Pd56 of the 56th PMOS,
Source electrode Ns56 connects VSS；The grid Ng57 of the 57th NMOS tube connects the 56th NMOS tube
Drain electrode Nd56, source electrode Ns57 connect the 58th NMOS tube drain electrode Nd58, drain electrode connect cn1；
The grid Ng58 of the 58th NMOS tube connects CK, drain electrode Nd58 and connects the 57th NMOS tube
Source electrode Nd57, source electrode Ns58 connect VSS；The grid Ng59 of the 59th NMOS tube connects the 50th
The drain electrode Nd56 of six NMOS tube, source electrode Ns59 connect the drain electrode Nd60 of the 60th NMOS tube, drain electrode
Connect cn2；The grid Ng60 of the 60th NMOS tube connects CK, drain electrode Nd60 and connects the 59th NMOS
The source electrode Nd59 of pipe, source electrode Ns60 connect VSS；The grid Ng61 of the 61st NMOS tube connects defeated
Going out and hold c1, drain electrode Nd61 connects outfan cn2, source electrode Ns61 and connects the drain electrode of the 65th NMOS tube
Nd65；The grid Ng62 of the 62nd NMOS tube connects outfan c2, drain electrode Nd62 and connects outfan
Cn2, source electrode Ns62 connect the drain electrode Nd66 of the 66th NMOS tube；The grid of the 63rd NMOS tube
Pole Ng63 connects outfan cn1, drain electrode Nd63 and connects outfan c1, source electrode Ns63 and connect VSS；The
The grid Ng64 of 64 NMOS tube connects outfan cn2, drain electrode Nd64 and connects outfan c2, source electrode
Ns64 connects VSS；The drain electrode Nd65 of the 65th NMOS tube connects the source of the 61st NMOS tube
Pole Ns61, grid Ng65 connect outfan c1, source electrode Ns65 and connect VSS；66th NMOS tube
Drain electrode Nd66 connect the 62nd NMOS tube source electrode Ns62, grid Ng66 connect outfan c1,
Source electrode Ns66 connects VSS.
Buffer circuit has an input and an outfan, and input is D, and outfan is D1.Buffering electricity
Routeing eight PMOS and eight NMOS tube compositions, in buffer circuit, the substrate of all PMOS connects
Power vd D, the Substrate ground VSS of all NMOS tube.The grid Pg1 of the first PMOS connects defeated
Entering D and the grid Ng1 with the first NMOS tube connects, drain electrode Pd1 connects the drain electrode of the first NMOS tube
Ng1, source electrode Ps1 connect VDD；The grid Pg2 of the second PMOS connects the drain electrode of the first PMOS
Pd1, drain electrode Pd2 connect the drain electrode Nd2, source electrode Ps2 of the second NMOS tube and connect VDD；3rd PMOS
The grid Pg3 of pipe connects the drain electrode Pd2 of the second PMOS, drain electrode Pd3 and connects the leakage of the 3rd NMOS tube
Pole Nd3, source electrode Ps3 connect VDD；The grid Pg4 of the 4th PMOS connects the leakage of the 3rd PMOS
Pole Pd3, drain electrode Pd4 connect the drain electrode Nd4, source electrode Ps4 of the 4th NMOS tube and connect VDD；5th PMOS
The grid Pg5 of pipe connects the drain electrode Pd4 of the 4th PMOS, drain electrode Pd5 and connects the leakage of the 5th NMOS tube
Pole Nd5, source electrode Ps5 connect VDD；The grid Pg6 of the 6th PMOS connects the leakage of the 5th PMOS
Pole Pd5, drain electrode Pd6 connect the drain electrode Nd6, source electrode Ps6 of the 6th NMOS tube and connect VDD；7th PMOS
The grid Pg7 of pipe connects the drain electrode Pd6 of the 6th PMOS, drain electrode Pd7 and connects the leakage of the 7th NMOS tube
Pole Nd7, source electrode Ps7 connect VDD；The grid Pg8 of the 8th PMOS connects the leakage of the 7th PMOS
Pole Pd7, drain electrode Pd8 connect the drain electrode Nd8 of the 8th NMOS tube and as the outfan D1 of buffer,
Source electrode Ps8 connects VDD；The grid Ng1 of the first NMOS tube connects Pg1, drain electrode Nd1 and connects Pd1,
Source electrode Ns1 connects VSS;The grid Ng2 of the second NMOS tube connects the drain electrode Nd1 of the first NMOS tube,
Drain electrode Nd2 connects Pd2, source electrode Ns2 and connects VSS；The grid Ng3 of the 3rd NMOS tube connects second
The drain electrode Nd2 of NMOS tube, drain electrode Nd3 connect Pd3, source electrode Ns3 and connect VSS；4th NMOS tube
Grid Ng4 connect the 3rd NMOS tube drain electrode Nd3, drain electrode Nd4 connect Pd4, source electrode Ns4 connect
VSS；The grid Ng5 of the 5th NMOS tube connects the drain electrode Nd4 of the 4th NMOS tube, and drain electrode Nd5 is even
Meet Pd5, source electrode Ns5 and connect VSS；The grid Ng6 of the 6th NMOS tube connects the 5th NMOS tube
Drain electrode Nd5, drain electrode Nd6 connect Pd6, source electrode Ns6 and connect VSS；The grid Ng7 of the 7th NMOS tube
Connect the drain electrode Nd6 of the 6th NMOS tube, drain electrode Nd7 to connect Pd7, source electrode Ns7 and connect VSS；8th
The grid Ng8 of NMOS tube connects the drain electrode Nd7 of the 7th NMOS tube, drain electrode Nd8 and connects Pd8, source electrode
Ns8 connects VSS.
Scan control buffer circuit has an input and an outfan, and input is SE, and outfan is
SEN.Scan control buffer circuit is made up of the 39th PMOS and the 39th NMOS tube.3rd
The substrate of 19 PMOS and source electrode Ps39 are all connected with power vd D, the substrate of the 39th NMOS tube
Ground connection VSS equal with source electrode Ns39.The grid Pg39 of the 39th PMOS connects SE, and drain Pd39
Connect the drain electrode Nd39 of the 39th NMOS tube, and as the outfan SEN of scan control circuit；The
The grid Ng39 of 39 NMOS tube connects SE, drain electrode Nd39 and connects Pd39.
Set buffer circuit has an input and two outfans, and input is SN, and outfan is SN01,
SN02.Set buffer circuit is made up of ten NMOS tube and ten PMOS, institute in set buffer circuit
The substrate having PMOS connects power vd D, the Substrate ground VSS of all NMOS tube.41st
The grid Pg41 of PMOS connects SN, drain electrode Pd41 and connects the drain electrode Nd41 of the 41st NMOS tube,
Source electrode Ps41 connects power vd D；The grid Pg42 of the 42nd PMOS connects the 41st PMOS
The drain electrode Pd41 of pipe, drain electrode Pd42 connect the drain electrode Nd42, source electrode Ps42 of the 42nd NMOS tube even
Meet power vd D；The grid Pg43 of the 43rd PMOS connects the drain electrode of the 42nd PMOS
Pd42, drain electrode Pd43 connect the drain electrode Nd43, source electrode Ps43 of the 43rd NMOS tube and connect power vd D；
The grid Pg44 of the 44th PMOS connects the drain electrode Pd43 of the 43rd PMOS, and drain Pd44
Connect the drain electrode Nd44 of the 44th NMOS tube, source electrode Ps44 and connect power vd D；45th PMOS
The grid Pg45 of pipe connects SN, drain electrode Pd45 and connects the source electrode Ps46 of the 46th PMOS, source electrode
Ps45 connects VDD；The grid Pg46 of the 46th PMOS connects the drain electrode of the 44th PMOS
Pd44, drain electrode Pd46 connect the drain electrode Nd45 of the 45th NMOS tube；The grid of the 47th PMOS
Pole Pg47 connects SN, drain electrode Pd47 and connects the source electrode Ps48, source electrode Ps47 of the 48th PMOS even
Meet VDD；The grid Pg48 of the 48th PMOS connects the drain electrode Pd44 of the 44th PMOS,
Drain electrode Pd48 connects the drain electrode Nd47, source electrode Ps48 of the 47th NMOS tube and connects the 47th PMOS
The drain electrode Pd47 of pipe；The grid Pg49 of the 49th PMOS connects the drain electrode of the 46th PMOS
Pd46, source electrode Ps49 connect power vd D, drain electrode Pd49 and connect the drain electrode Nd49 of the 49th NMOS tube
And as an outfan SN01 of set buffer circuit；The grid Pg50 of the 50th PMOS connects the
The drain electrode Pd48 of 48 PMOS, source electrode Ps50 connect power vd D, drain electrode Pd50 and connect the 5th
The drain electrode Nd50 of ten NMOS tube another outfan SN02 as set buffer circuit；41st
The grid Ng41 of NMOS tube connects SN, drain electrode Nd41 and connects the drain electrode Pd41 of the 41st PMOS,
Source electrode Ns41 connects VSS；The grid Ng42 of the 42nd NMOS tube connects the 41st NMOS tube
Drain electrode Nd41, drain electrode Nd42 connect the 42nd PMOS drain electrode Pd42, source electrode Ns42 connect
VSS；The grid Ng43 of the 43rd NMOS tube connects the drain electrode Nd42 of the 42nd NMOS tube, leakage
Pole Nd43 connects the drain electrode Pd43, source electrode Ns43 of the 43rd PMOS and connects VSS；44th
The grid Ng44 of NMOS tube connects the drain electrode Nd43 of the 43rd NMOS tube, drain electrode Nd44 and connects the
The drain electrode Pd44 of 44 PMOS, source electrode Ns44 connect VSS；The grid of the 45th NMOS tube
Ng45 connects the drain electrode Nd44, source electrode Ns45 of the 44th NMOS tube and connects the 46th NMOS tube
Drain electrode Nd46, drain electrode Nd45 connect the 49th NMOS tube grid Ng49；46th NMOS
The grid Ng46 of pipe connects SN, drain electrode Nd46 and connects the source electrode Nd45 of the 45th NMOS tube, source electrode
Ns46 connects VSS；The grid Ng47 of the 47th NMOS tube connects the leakage of the 44th NMOS tube
Pole Nd44, source electrode Ns47 connect the drain electrode Nd48 of the 48th NMOS tube, drain electrode Nd47 and connect the 5th
Ten NMOS tube grid Ng50；The grid Ng48 of the 48th NMOS tube connects SN, and drain Nd48
Connect the source electrode Nd47 of the 47th NMOS tube, source electrode Ns48 and connect VSS.49th NMOS
The grid Ng49 of pipe connects the drain electrode Nd45, source electrode Ns49 of the 45th NMOS tube and connects ground VSS,
Drain electrode Nd49 connects the drain electrode Pd49 of the 49th PMOS and connects outfan SN01；50th
The grid Ng50 of NMOS tube connects the 47th NMOS tube drain electrode Nd47, and drain electrode Nd50 connects the 5th
The drain electrode Nd50 of ten PMOS also connects outfan SN02, and source electrode Ns50 connects VSS.
Main latch has 11 inputs and two outfans, and input is D, D1, SI, SE, SEN,
SN01, SN02, c1, c2, cn1, cn2；Outfan is m1, m1r.Main latch is by 18 PMOS
Pipe and 18 NMOS tube compositions, in main latch, the substrate of all PMOS connects power vd D,
The Substrate ground VSS of all NMOS tube.The grid Pg9 of the 9th PMOS connects SI, and drain Pd9
Connect the source electrode Ps10 of the tenth PMOS, source electrode Ps9 and connect power vd D；The grid of the tenth PMOS
Pole Pg10 connects SEN, drain electrode Pd10 and connects the source electrode Ps13, source electrode Ps10 of the 13rd PMOS even
Meet Pd9；The grid Pg11 of the 11st PMOS connects SE, drain electrode Pd11 and connects the 12nd PMOS
Source electrode Ps12, source electrode Ps11 connect power vd D；The grid Pg12 of the 12nd PMOS connects D,
Drain electrode Pd12 connects Ps13, source electrode Ps12 and connects Pd11；The grid Pg8 of the 13rd PMOS connects
C1, drain electrode Pd13 connect the drain electrode Nd9, source electrode Ps13 of the 9th NMOS tube and connect Pd10；14th
The grid Pg14 of PMOS connects SI, drain electrode Pd14 and connects the source electrode Ps15 of the 15th PMOS, source
Pole Ps14 connects power vd D；The grid Pg15 of the 15th PMOS connects SEN, and drain electrode Pd15 is even
Meet the source electrode Ps18 of the 18th PMOS, source electrode Ps15 and connect Pd14；The grid of the 16th PMOS
Pg16 connects SE, drain electrode Pd16 and connects the source electrode Ps17, source electrode Ps16 of the 17th PMOS and connect electricity
Source VDD；The grid Pg17 of the 17th PMOS connects D1, drain electrode Pd17 and connects the 18th PMOS
The source electrode Ps18 of pipe, source electrode Ps17 connect Pd16；The grid Pg18 of the 18th PMOS connects c2,
Drain electrode Pd18 connects the drain electrode Nd14, source electrode Ps18 of the 14th NMOS tube and connects Pd15；19th PMOS
The grid Pg19 of pipe connects the drain electrode Pd13 of the 13rd PMOS, drain electrode Pd19 and connects the 19th NMOS
The drain electrode Nd19 of pipe, and as an outfan m1, the source electrode Ps19 connection power vd D of main latch；
The grid Pg20 of the 20th PMOS connects SN01, drain electrode Pd20 and connects the leakage of the 19th NMOS tube
Pole Nd19, and connect outfan m1, source electrode Ps20 connects power vd D；21st PMOS
Grid Pg21 connects the drain electrode Pd18 of the 18th PMOS, drain electrode Pd21 and connects the 21st NMOS
The drain electrode Nd21 of pipe, and as an outfan m1r, the source electrode Ps21 connection power vd D of main latch；
The grid Pg22 of the 22nd PMOS connects SN02, drain electrode Pd22 and connects the 21st NMOS tube
Drain electrode Nd21, and connect outfan m1r, source electrode Ps22 connects power vd D；23rd PMOS
The grid Pg23 of pipe connects Pd22, drain electrode Pd23 and connects the source electrode Ps24 of the 24th PMOS, source electrode
Ps23 connects power vd D；The grid Pg24 of the 24th PMOS connects cn1, drain electrode Pd24 and connects
The drain electrode Nd23 of the 23rd NMOS tube, source electrode Ps24 connect Pd23；The grid of the 25th PMOS
Pole Pg25 connects Pd20, drain electrode Pd25 and connects the source electrode Ps26, source electrode Ps25 of the 26th PMOS
Connect power vd D；The grid Pg26 of the 26th PMOS connects cn2, drain electrode Pd26 and connects second
The drain electrode Nd25 of 15 NMOS tube is also connected with Pd18, and source electrode Ps26 connects Pd25；9th NMOS
The grid Ng9 of pipe connects cn1, drain electrode Nd9 and connects Pd13, source electrode Ns9 and connect the tenth NMOS tube
Drain electrode Nd10；The grid Ng10 of the tenth NMOS tube connects SE, drain electrode Nd10 and connects Ns9, source electrode
Ns10 connects the drain electrode Nd11 of the 11st NMOS tube；The grid Ng11 of the 11st NMOS tube connects SI,
Drain electrode Nd11 connects Ns10, source electrode Ns11 ground connection VSS；The grid Ng12 of the 12nd NMOS tube connects
D, drain electrode Nd12 connect Ns9, source electrode Ns12 and connect the drain electrode Nd13 of the 13rd NMOS tube；13rd
The grid Ng13 of NMOS tube connects SEN, drain electrode Nd13 and connects Ns12, source electrode Ns13 ground connection VSS；
The grid Ng14 of the 14th NMOS tube connects cn2, drain electrode Nd14 and connects Pd18, source electrode Ns14 and connect
The drain electrode Nd15 of the 15th NMOS tube；The grid Ng15 of the 15th NMOS tube connects SE, and drain Nd15
Connect Ns14, source electrode Ns15 and connect the drain electrode Nd16 of the 16th NMOS tube；16th NMOS tube
Grid Ng16 connects SI, drain electrode Nd16 and connects Ns15, source electrode Ns16 ground connection VSS；17th NMOS
The grid Ng17 of pipe connects D1, drain electrode Nd17 and connects Ns14, source electrode Ns17 and connect the 18th NMOS
The drain electrode Nd18 of pipe；The grid Ng18 of the 18th NMOS tube connects SEN, drain electrode Nd18 and connects Ns17,
Source electrode Ns18 ground connection VSS；The grid Ng19 of the 19th NMOS tube connects Pd18, drain electrode Nd19 and connects
Pd20, source electrode Ns19 meet the 20th NMOS tube drain electrode Nd20；The grid Ng20 of the 20th NMOS tube
Connect SN02, drain electrode Nd20 and connect Ns19, source electrode Ns20 ground connection VSS；21st NMOS tube
Grid Ng21 connects Pd18, and drain electrode Nd21 connection Pd22, source electrode Ns21 connect the 22nd NMOS tube
Drain electrode Nd22；The grid Ng22 of the 22nd NMOS tube connects SN01, drain electrode Nd22 and connects Ns21,
Source electrode Ns22 ground connection VSS；The grid Ng23 of the 23rd NMOS tube connects c1, drain electrode Nd23 and connects
Pd24, source electrode Ns23 connect the drain electrode Nd24 of the 24th NMOS tube；24th NMOS tube
Grid Ng24 connects Pd20, drain electrode Nd24 and connects Ns23, source electrode Ns24 ground connection VSS；25th
The grid Ng25 of NMOS tube connects c2, drain electrode Nd25 and connects Pd26, source electrode Ns25 and connect the 26th
The drain electrode Nd26 of NMOS tube；The grid Ng26 of the 26th NMOS tube connects Pd22, and drain Nd26
Connect Ns25, source electrode Ns26 ground connection VSS.9th PMOS, the tenth PMOS, the 11st PMOS
Manage and in the tenth NMOS tube, the 11st NMOS tube, the 13rd NMOS tube composition main latch
Scan Architecture.Set structure in 20th PMOS and the 20th NMOS tube composition main latch.
Having eight inputs and two outfans from latch, input is SN01, SN02, c1, c2, cn1,
Cn2, m1, m1r；Outfan is s1, s1r.From latch by 12 PMOS and 12 NMOS
Pipe forms, and from latch, the substrate of all PMOS connects power vd D, the lining of all NMOS tube
End ground connection VSS.The grid Pg27 of the 27th PMOS connects m1r, drain electrode Pd27 and connects the 20th
The source electrode Ps28 of eight PMOS, source electrode Ps27 connect power vd D；The grid of the 28th PMOS
Pg28 connects cn1, drain electrode Pd28 and connects the drain electrode Nd27, source electrode Ps28 of the 27th NMOS tube and connect
Pd27；The grid Pg29 of the 29th PMOS connects m1, drain electrode Pd29 and connects the 30th PMOS
The source electrode Ps30 of pipe, source electrode Ps29 connect power vd D；The grid Pg30 of the 30th PMOS connects
Cn2, drain electrode Pd30 connect the drain electrode Nd29, source electrode Ps30 of the 29th NMOS tube and connect Pd29；The
The grid Pg31 of 31 PMOS connects the drain electrode Pd28 of the 28th PMOS, and drain Pd31
Connect the drain electrode Nd31 of the 31st NMOS tube and as from latch outfan s1, source electrode Ps31
Connect power vd D；The grid Pg32 of the 32nd PMOS connects SN01, drain electrode Pd32 and connects the
The drain electrode Nd31 of 31 NMOS tube, and connect outfan s1, source electrode Ps32 connects power vd D；The
The grid Pg33 of 33 PMOS connects the drain electrode Pd30 of the 30th PMOS, drain electrode Pd33 and connects
The drain electrode Nd33 of the 33rd NMOS tube, and as from latch outfan s1r, source electrode Ps33
Connect power vd D；The grid Pg34 of the 34th PMOS connects SN02, drain electrode Pd34 and connects the
The drain electrode Nd33 of 33 NMOS tube, and connect outfan s1r, source electrode Ps34 connects power vd D；
The grid Pg35 of the 35th PMOS connects Pd34, drain electrode Pd35 and connects the 36th PMOS
Source electrode Ps36, source electrode Ps35 connect power vd D；The grid Pg36 of the 36th PMOS connects cn1,
Drain electrode Pd36 connects the drain electrode Nd35, source electrode Ps36 of the 35th NMOS tube and connects Pd35；30th
The grid Pg37 of seven PMOS connects Pd32, drain electrode Pd37 and connects the source electrode of the 38th PMOS
Ps38, source electrode Ps37 connect power vd D；The grid Pg38 of the 38th PMOS connects cn2, leakage
Pole Pd38 connects the drain electrode Nd37, source electrode Ps38 of the 37th NMOS tube and connects Pd37；27th
The grid Ng27 of NMOS tube connects c, drain electrode Nd27 and connects Pd28, source electrode Ns27 and connect the 28th
The drain electrode Nd28 of NMOS tube；The grid Ng28 of the 28th NMOS tube connects m1, and drain Nd28
Connect Ns27, source electrode Ns28 ground connection VSS；The grid Ng29 of the 29th NMOS tube connects c2, leakage
Pole Nd29 connects Pd30, source electrode Ns29 and connects the drain electrode Nd30 of the 30th NMOS tube；30th NMOS
The grid Ng30 of pipe connects m1r, drain electrode Nd30 and connects Ns29, source electrode Ns30 ground connection VSS；30th
The grid Ng31 of one NMOS tube connects Pd30, drain electrode Nd31 and connects Pd32, source electrode Ns31 and connect the
The drain electrode Nd32 of 32 NMOS tube；The grid Ng32 of the 32nd NMOS tube connects SN02, leakage
Pole Nd32 connects Ns31, source electrode Ns32 ground connection VSS；The grid Ng33 of the 33rd NMOS tube connects
Pd28, drain electrode Nd33 connect Pd34, source electrode Ns33 and meet the drain electrode Nd34 of the 34th NMOS tube；The
The grid Ng34 of 34 NMOS tube connects SN01, and drain electrode Nd34 connection Ns33, source electrode Ns34 connect
Ground VSS；The grid Ng35 of the 35th NMOS tube connects c1, drain electrode Nd35 and connects Pd36, source electrode
Ns35 connects the drain electrode Nd36 of the 36th NMOS tube；The grid Ng36 of the 36th NMOS tube is even
Meet Pd32, drain electrode Nd36 and connect Ns35, source electrode Ns36 ground connection VSS；The grid of the 37th NMOS tube
Pole Ng37 connects c2, drain electrode Nd37 and connects Pd38, source electrode Ns37 and connect the 38th NMOS tube
Drain electrode Nd38；The grid Ng38 of the 38th NMOS tube connects Pd34, drain electrode Nd38 and connects Ns37,
Source electrode Ns38 ground connection VSS.32nd PMOS and the 32nd NMOS tube form from latch
In set structure.
First output buffer has two inputs and an outfan, and input connects s1 and s1r, output
End is Q.Output buffer is made up of two PMOS and two NMOS tube.Output buffer institute
The substrate having PMOS connects power vd D, the Substrate ground VSS of all NMOS tube.51st
The grid Pg51 of PMOS meets input s1r, drain electrode Pd51 and connects the drain electrode of the 51st NMOS tube
Nd51, source electrode Ps51 meet power vd D；The grid Pg52 of the 52nd PMOS meets Pd51, drain electrode
Pd52 connects the drain electrode Nd52 of the 52nd NMOS tube, and as the output Q of output buffer；Source
Pole Ps52 meets power vd D；The grid Ng51 of the 51st NMOS tube meets input s1, and drain Nd51
Connect Pd51, source electrode Ns51 ground connection VSS；The grid Ng52 of the 52nd NMOS tube meets Nd51, leakage
Pole Nd52 connects Pd52, source electrode Ns52 ground connection VSS.
Second output buffer has two inputs and an outfan, and input connects s1 and s1r, output
End is QN.Output buffer is made up of a PMOS and a NMOS tube.The lining of PMOS
The end, connects power vd D, the Substrate ground VSS of NMOS tube.The grid Pg40 of the 40th PMOS
Meet input s1, drain electrode Pd40 and connect the drain electrode Nd40 of the 40th NMOS tube, and as buffer circuit
Outfan QN, source electrode Ps40 meet power vd D；The grid Ng40 of the 40th NMOS tube meets input s1r,
Drain electrode Nd40 connects Pd40, and connects outfan QN, source electrode Ns40 ground connection VSS.
Anti-single particle of the present invention upset and the setable Scan Architecture d type flip flop work process of single-ion transient state
As follows:
The setable Scan Architecture d type flip flop of anti-single particle of the present invention upset and single-ion transient state is being in scanning
The time marquis of state can also pass through SM set mode, i.e. scanning mode and SM set mode can exist simultaneously.The present invention
The Scan Architecture d type flip flop of single event upset resistant settable can carry out set, set function at any time
Controlled by the i.e. set signal input part of SN.
When SN be low level, SE be any level time, anti-single particle of the present invention upset and single-ion transient state
Setable Scan Architecture d type flip flop is in SM set mode, i.e. main latch and all being locked by force from latch
Depositing logical one, outfan Q and QN of output buffer is respectively high level and low level.
When SN be high level, SE be low level time, anti-single particle of the present invention upset and single-ion transient state setable
Scan Architecture d type flip flop is in normal operating conditions, i.e. clock circuit receives CK, after buffering CK
Produce cn1, cn2 anti-phase with CK and c1, c2 with CK homophase respectively, and cn1, cn2 and c1,
C2 is passed to main latch and from latch.Buffer circuits receives D, output and D after being postponed by D
The D1 of homophase, is between low period at CK, and cn1, cn2 are high level, and c1, c2 are low level, main
Latch open, receive D and D1, and in D and D1 may with single event transient pulse filter
Remove, then by latch output and m1, m1r of D, D1 homophase, be in preservation state from latch,
Do not receive m1, m1r of main latch output, but preserve m1, m1r that a CK trailing edge samples；
Be between high period at CK, cn1, cn2 be low level, c1, c2 be high level, main latch is in guarantor
Deposit state, preserve D, D1 that previous CK rising edge samples and export and D, D1 homophase, from lock
Output m1, m1r of main latch is opened and received to storage, and m1, m1r are carried out buffered and exports
S1, s1r with m1, m1r homophase.Output buffer will receive the output from latch at any time
S1, s1r, buffer and export the QN anti-phase with s1, s1r and the Q with s1, s1r homophase to s1, s1r.
When SN be high level, SE be high level time, anti-single particle of the present invention upset and single-ion transient state can
Set sweep structure d type flip flop is in scanning mode, i.e. clock circuit receives CK, after buffering CK
Produce cn1, cn2 anti-phase with CK and c1, c2 with CK homophase respectively, and cn1, cn2 and c1,
C2 is passed to main latch and from latch.Being between low period at CK, cn1, cn2 are high level, c1,
C2 is low level, and main latch is opened, and exports and SI homophase after receiving SI and it being carried out buffered
M1, m1r, be in preservation state from latch, does not receive m1, m1r of main latch output but preserves
M1, m1r that a upper CK trailing edge samples；Being between high period at CK, cn1, cn2 are low electricity
Flat, c1, c2 are high level, and main latch is in preservation state, preserves previous CK rising edge and samples
SI and export and m1, m1r of SI homophase, open from latch and receive main latch output m1,
M1r, carries out buffered and exports s1, the s1r with m1, m1r homophase m1, m1r.At any time
Output buffer will receive output s1, the s1r from latch, s1, s1r are buffered and export with s1,
QN that s1r the is anti-phase and Q with s1, s1r homophase.
Scan control buffer circuit exports the SEN anti-phase with SE after input signal carries out buffered, and will
It sends into main latch, is scanned the control of behavior.
Set buffer circuit input signal is postponed after by the C of duplication redundancy2MOS structure filters SN
Middle may with single event transient pulse, and will output send into main with SN01 and SN02 of SN homophase
Latch and from latch, carries out the control of set behavior.
Use the present invention can reach techniques below effect:
The anti-simple grain of the Scan Architecture d type flip flop that anti-single particle of the present invention upset is setable with anti-single particle transient state
Son upset and anti-single particle transient state ability are better than tradition unguyed setable Scan Architecture d type flip flop, the time
Setable Scan Architecture d type flip flop is reinforced in sampling and tradition duplication redundancy reinforces setable Scan Architecture D
Trigger.The unguyed setable Scan Architecture d type flip flop structure of tradition is transformed, to master by the present invention
Latch and all carried out duplication redundancy reinforcing from latch, and for main latch and from latch C2
MOS circuit is improved, and i.e. separates the C being mutually redundant2Pull-up PMOS in MOS circuit and under
Draw NMOS tube, improve the primary particle inversion resistant ability of the present invention.In clock circuit and before main latch
Add buffer circuit, make the present invention not make a mistake under long-term single event transient pulse；Logical
Cross well-designed duplication redundancy path, cut off from latch may by single event transient pulse cause positive and negative
It is fed back to road, further increases the ability of anti-single particle transient state.Anti-single particle of the present invention upset and single-particle wink
The setable Scan Architecture d type flip flop of state is suitable for anti-single particle upset and anti-single particle transient state is reinforced integrated
The standard cell lib of circuit, is applied to the fields such as Aeronautics and Astronautics.
Accompanying drawing explanation
Fig. 1 is that the Scan Architecture D of the single event upset resistant settable of Application No. 201110323794.1 triggers
Device overall logic structural representation
Fig. 2 is that the Scan Architecture d type flip flop that anti-single particle of the present invention overturns and single-ion transient state is setable is overall
Logical structure schematic diagram.
Fig. 3 be anti-single particle of the present invention upset and single-ion transient state setable Scan Architecture d type flip flop in
Clock circuit structural representation.
Fig. 4 is slow in the Scan Architecture d type flip flop that anti-single particle of the present invention upset is setable with single-ion transient state
Rush electrical block diagram.
Fig. 5 is to sweep in the Scan Architecture d type flip flop that anti-single particle of the present invention upset is setable with single-ion transient state
Retouch control buffer circuit structure schematic diagram.
Fig. 6 is to put in the Scan Architecture d type flip flop that anti-single particle of the present invention upset is setable with single-ion transient state
Bit buffering electrical block diagram.
Fig. 7 is main in the Scan Architecture d type flip flop that anti-single particle of the present invention upset is setable with single-ion transient state
Latch structure schematic diagram.
Fig. 8 be in anti-single particle of the present invention upset and the setable Scan Architecture d type flip flop of single-ion transient state from
Latch structure schematic diagram.
Fig. 9 is in anti-single particle of the present invention upset and the setable Scan Architecture d type flip flop of single-ion transient state the
One output buffer structural representation.
Figure 10 is in anti-single particle of the present invention upset and the setable Scan Architecture d type flip flop of single-ion transient state the
Two output buffer structural representations.
Detailed description of the invention
Fig. 2 is the Scan Architecture d type flip flop logic that anti-single particle of the present invention upset is setable with single-ion transient state
Structural representation.The present invention by clock circuit (as shown in Figure 3), buffer circuit (as shown in Figure 4), sweep
Retouch control buffer circuit (as shown in Figure 5), set buffer circuit (as shown in Figure 6), main latch (as
Shown in Fig. 7), from latch (as shown in Figure 8), the first output buffer (as shown in Figure 9) and
Two buffer circuits (shown in Figure 10) form.Anti-single particle of the present invention upset and anti-single particle transient state are setable
Scan Architecture d type flip flop has five inputs and two outfans.Four inputs are that clock signal is defeated respectively
Enter to hold CK, data signal input D, scan control signal input SE, scan data input SI and
Set signal input part SN；Outfan is Q and QN respectively.Clock circuit receives CK, carries out CK
C1, c2 and cn1, cn2 is exported respectively after buffered.Buffer circuit receives D, and D is carried out buffered
Rear export D1 respectively.Scan control buffer circuit receives SE, exports respectively after SE is carried out buffered
SEN.Set buffer circuit receives SN, exports SN01, SN02 after SN carries out buffered.Main lock
Storage receives D, D1, SI, SE, SEN, c1, c2, cn1, cn2, SN01, SN02, main latch
D, D1 or SI are entered under SE, the control of SEN, c1, c2, cn1, cn2, SN01, SN02 by device
Row latches etc. export m1, m1r after processing.From latch receive m1, m1r and c1, c2, cn1, cn2,
SN01, SN02, from latch under the control of c1, c2, cn1, cn2, SN01, SN02 to m1,
M1r carries out exporting s1, s1r respectively after latch etc. processes.Output buffer receives s1, s1r, carries out it
Q and QN is exported after buffered.SN is high level, SE when being low level, and anti-single particle of the present invention overturns
The Scan Architecture d type flip flop setable with single-ion transient state is in normal operating conditions；SN is high level, SE
During for high level, at the Scan Architecture d type flip flop that anti-single particle of the present invention upset is setable with single-ion transient state
In scanning work state；When SN is low level, anti-single particle of the present invention upset and single-ion transient state are setable
Scan Architecture d type flip flop enters SM set mode.
As it is shown on figure 3, clock circuit has an input and four outfans, input is CK, outfan
For c1, c2, cn1, cn2.Clock circuit is made up of 12 PMOS and 14 NMOS.50th
The grid Pg53 of three PMOS connects CK, drain electrode Pd53 and connects the drain electrode of the 53rd NMOS tube
Nd53；The grid Pg54 of the 54th PMOS connects the drain electrode Pd53 of the 53rd PMOS, leakage
Pole Pd54 connects the drain electrode Nd54, source electrode Ps54 of the 54th NMOS tube and connects power vd D；5th
The grid Pg55 of 15 PMOS connects the drain electrode Pd54 of the 54th PMOS, drain electrode Pd55 and connects
The drain electrode Nd55 of the 55th NMOS tube, source electrode Ps55 connect power vd D；56th PMOS
The grid Pg56 of pipe connects the drain electrode Pd55 of the 55th PMOS, drain electrode Pd56 and connects the 56th
The drain electrode Nd56 of NMOS tube, source electrode Ps56 connect power vd D；The grid of the 57th PMOS
Pg57 connects CK, drain electrode Pd57 and connects the source electrode Ps58, source electrode Ps57 of the 58th PMOS and connect
VDD；The grid Pg58 of the 58th PMOS connects the drain electrode Pd56 of the 56th PMOS, leakage
Pole Pd58 connects the drain electrode Nd57 of the 57th NMOS tube, and as an outfan cn1 of clock circuit,
Source electrode Ps58 connects Pd57；The grid Pg59 of the 59th PMOS connects CK, drain electrode Pd59 and connects
The source electrode Ps60 of the 60th PMOS, source electrode Ps59 connect VDD；The grid Pg60 of the 60th PMOS
Connect the drain electrode Pd56 of the 56th PMOS, drain electrode Pd60 and connect the drain electrode of the 59th NMOS tube
Nd59 an outfan cn2, source electrode Ps60 as clock circuit connect Pd59；61st PMOS
The grid Pg61 of pipe connects the 58th PMOS as an outfan c1 of clock circuit, drain electrode Pd61
The drain electrode Pd58 of pipe, and connect outfan cn1, source electrode Ps61 connects VDD；62nd PMOS
Grid Pg62 connect the grid Ng62 of the 62nd NMOS tube and as an outfan of clock circuit
C2, drain electrode Pd62 connect the drain electrode Nd62 of the 62nd NMOS tube and as an output of clock circuit
End cn2, source electrode Ps62 connect VDD；The grid Pg63 of the 63rd PMOS connects outfan cn1,
Drain electrode Pd63 connects outfan c1, source electrode Ps63 and connects VDD；The grid Pg64 of the 64th PMOS
Connect outfan cn2, drain electrode Pd64 to connect outfan c2, source electrode Ps64 and connect VDD；53rd NMOS
The grid Ng53 of pipe connects CK, drain electrode Nd53 and connects the drain electrode Pd53 of the 53rd PMOS；5th
The grid Ng54 of 14 NMOS tube connects the drain electrode Nd53 of the 53rd NMOS tube, and drain electrode Nd54 is even
Meet the drain electrode Pd54 of the 54th PMOS, source electrode Ns54 and connect VSS；55th NMOS tube
Grid Ng55 connects the drain electrode Nd54 of the 54th NMOS tube, drain electrode Nd55 and connects the 55th PMOS
The drain electrode Pd55 of pipe, source electrode Ns55 connect VSS；The grid Ng56 of the 56th NMOS tube connects the
The drain electrode Nd55 of 55 NMOS tube, drain electrode Nd56 connect the drain electrode Pd56 of the 56th PMOS,
Source electrode Ns56 connects VSS；The grid Ng57 of the 57th NMOS tube connects the 56th NMOS tube
Drain electrode Nd56, source electrode Ns57 connect the 58th NMOS tube drain electrode Nd58, drain electrode connect cn1；
The grid Ng58 of the 58th NMOS tube connects CK, drain electrode Nd58 and connects the 57th NMOS tube
Source electrode Nd57, source electrode Ns58 connect VSS；The grid Ng59 of the 59th NMOS tube connects the 50th
The drain electrode Nd56 of six NMOS tube, source electrode Ns59 connect the drain electrode Nd60 of the 60th NMOS tube, drain electrode
Connect cn2；The grid Ng60 of the 60th NMOS tube connects CK, drain electrode Nd60 and connects the 59th NMOS
The source electrode Nd59 of pipe, source electrode Ns60 connect VSS；The grid Ng61 of the 61st NMOS tube connects defeated
Going out and hold c1, drain electrode Nd61 connects outfan cn2, source electrode Ns61 and connects the drain electrode of the 65th NMOS tube
Nd65；The grid Ng62 of the 62nd NMOS tube connects outfan c2, drain electrode Nd62 and connects outfan
Cn2, source electrode Ns62 connect the drain electrode Nd66 of the 66th NMOS tube；The grid of the 63rd NMOS tube
Pole Ng63 connects outfan cn1, drain electrode Nd63 and connects outfan c1, source electrode Ns63 and connect VSS；The
The grid Ng64 of 64 NMOS tube connects outfan cn2, drain electrode Nd64 and connects outfan c2, source electrode
Ns64 connects VSS；The drain electrode Nd65 of the 65th NMOS tube connects the source of the 61st NMOS tube
Pole Ns61, grid Ng65 connect outfan c1, source electrode Ns65 and connect VSS；66th NMOS tube
Drain electrode Nd66 connect the 62nd NMOS tube source electrode Ns62, grid Ng66 connect outfan c1,
Source electrode Ns66 connects VSS.
As shown in Figure 4, buffer circuit has an input and an outfan, and input is D, outfan
For D1.Buffer circuit is made up of eight PMOS and eight NMOS tube, all PMOS in buffer circuit
The substrate of pipe connects power vd D, the Substrate ground VSS of all NMOS tube.The grid of the first PMOS
Pole Pg1 connects input D and the grid Ng1 with the first NMOS tube connects, and drain electrode Pd1 connects a NMOS
The drain electrode Ng1 of pipe, source electrode Ps1 connect VDD；The grid Pg2 of the second PMOS connects a PMOS
The drain electrode Pd1 of pipe, drain electrode Pd2 connect the drain electrode Nd2, source electrode Ps2 of the second NMOS tube and connect VDD；
The grid Pg3 of the 3rd PMOS connects the drain electrode Pd2 of the second PMOS, drain electrode Pd3 and connects the 3rd
The drain electrode Nd3 of NMOS tube, source electrode Ps3 connect VDD；The grid Pg4 of the 4th PMOS connects the 3rd
The drain electrode Pd3 of PMOS, drain electrode Pd4 connect the drain electrode Nd4, source electrode Ps4 of the 4th NMOS tube and connect
VDD；The grid Pg5 of the 5th PMOS connects the drain electrode Pd4 of the 4th PMOS, drain electrode Pd5 and connects
The drain electrode Nd5 of the 5th NMOS tube, source electrode Ps5 connect VDD；The grid Pg6 of the 6th PMOS is even
Meet the drain electrode Pd5 of the 5th PMOS, drain electrode Pd6 and connect the drain electrode Nd6, source electrode Ps6 of the 6th NMOS tube
Connect VDD；The grid Pg7 of the 7th PMOS connects the drain electrode Pd6 of the 6th PMOS, and drain Pd7
Connect the drain electrode Nd7 of the 7th NMOS tube, source electrode Ps7 and connect VDD；The grid Pg8 of the 8th PMOS
Connect the drain electrode Pd7 of the 7th PMOS, drain electrode Pd8 and connect drain electrode Nd8 the conduct of the 8th NMOS tube
The outfan D1 of buffer, source electrode Ps8 connect VDD；The grid Ng1 of the first NMOS tube connects Pg1,
Drain electrode Nd1 connects Pd1, source electrode Ns1 and connects VSS;The grid Ng2 of the second NMOS tube connects a NMOS
The drain electrode Nd1 of pipe, drain electrode Nd2 connect Pd2, source electrode Ns2 and connect VSS；The grid of the 3rd NMOS tube
Ng3 connects the drain electrode Nd2 of the second NMOS tube, drain electrode Nd3 and connects Pd3, source electrode Ns3 and connect VSS；
The grid Ng4 of the 4th NMOS tube connects the drain electrode Nd3 of the 3rd NMOS tube, drain electrode Nd4 and connects Pd4,
Source electrode Ns4 connects VSS；The grid Ng5 of the 5th NMOS tube connects the drain electrode Nd4 of the 4th NMOS tube,
Drain electrode Nd5 connects Pd5, source electrode Ns5 and connects VSS；The grid Ng6 of the 6th NMOS tube connects the 5th
The drain electrode Nd5 of NMOS tube, drain electrode Nd6 connect Pd6, source electrode Ns6 and connect VSS；7th NMOS tube
Grid Ng7 connect the 6th NMOS tube drain electrode Nd6, drain electrode Nd7 connect Pd7, source electrode Ns7 connect
VSS；The grid Ng8 of the 8th NMOS tube connects the drain electrode Nd7 of the 7th NMOS tube, and drain electrode Nd8 is even
Meet Pd8, source electrode Ns8 and connect VSS.
As it is shown in figure 5, scan control buffer circuit has an input and an outfan, input is SE,
Outfan is SEN.Scan control buffer circuit is by the 39th PMOS and the 39th NMOS tube group
Become.Substrate and the source electrode Ps39 of the 39th PMOS are all connected with power vd D, the 39th NMOS
The substrate of pipe and source electrode Ns39 equal ground connection VSS.The grid Pg39 of the 39th PMOS connects SE, leakage
Pole Pd39 connects the drain electrode Nd39 of the 39th NMOS tube, and as the outfan of scan control circuit
SEN；The grid Ng39 of the 39th NMOS tube connects SE, drain electrode Nd39 and connects Pd39.
As shown in Figure 6, set buffer circuit has an input and two outfans, and input is SN, defeated
Going out end is SN01, SN02.Set buffer circuit is made up of ten NMOS tube and ten PMOS, puts
In bit buffering circuit, the substrate of all PMOS connects power vd D, the Substrate ground of all NMOS tube
VSS.The grid Pg41 of the 41st PMOS connects SN, drain electrode Pd41 and connects the 41st NMOS
The drain electrode Nd41 of pipe, source electrode Ps41 connect power vd D；The grid Pg42 of the 42nd PMOS is even
Meet the drain electrode Pd41 of the 41st PMOS, drain electrode Pd42 and connect the drain electrode of the 42nd NMOS tube
Nd42, source electrode Ps42 connect power vd D；The grid Pg43 of the 43rd PMOS connects the 42nd
The drain electrode Pd42 of PMOS, drain electrode Pd43 connect the drain electrode Nd43 of the 43rd NMOS tube, source electrode
Ps43 connects power vd D；The grid Pg44 of the 44th PMOS connects the 43rd PMOS
Drain electrode Pd43, drain electrode Pd44 connect the drain electrode Nd44, source electrode Ps44 of the 44th NMOS tube and connect electricity
Source VDD；The grid Pg45 of the 45th PMOS connects SN, drain electrode Pd45 and connects the 46th PMOS
The source electrode Ps46 of pipe, source electrode Ps45 connect VDD；The grid Pg46 of the 46th PMOS connects the 4th
The drain electrode Pd44 of 14 PMOS, drain electrode Pd46 connect the drain electrode Nd45 of the 45th NMOS tube；
The grid Pg47 of the 47th PMOS connects SN, drain electrode Pd47 and connects the 48th PMOS
Source electrode Ps48, source electrode Ps47 connect VDD；The grid Pg48 of the 48th PMOS connects the 44th
The drain electrode Pd44 of PMOS, drain electrode Pd48 connect the drain electrode Nd47 of the 47th NMOS tube, source electrode
Ps48 connects the drain electrode Pd47 of the 47th PMOS；The grid Pg49 of the 49th PMOS connects
The drain electrode Pd46 of the 46th PMOS, source electrode Ps49 connect power vd D, and drain electrode Pd49 connects the
The drain electrode Nd49 of 49 NMOS tube an outfan SN01 as set buffer circuit；50th
The grid Pg50 of PMOS connects the drain electrode Pd48, source electrode Ps50 of the 48th PMOS and connects power supply
VDD, drain electrode Pd50 connect the drain electrode Nd50 of the 50th NMOS tube and as another of set buffer circuit
Individual outfan SN02；The grid Ng41 of the 41st NMOS tube connects SN, drain electrode Nd41 and connects the 4th
The drain electrode Pd41 of 11 PMOS, source electrode Ns41 connect VSS；The grid of the 42nd NMOS tube
Ng42 connects the drain electrode Nd41 of the 41st NMOS tube, drain electrode Nd42 and connects the 42nd PMOS
Drain electrode Pd42, source electrode Ns42 connect VSS；The grid Ng43 of the 43rd NMOS tube connects the 4th
The drain electrode Nd42 of 12 NMOS tube, drain electrode Nd43 connect the drain electrode Pd43 of the 43rd PMOS,
Source electrode Ns43 connects VSS；The grid Ng44 of the 44th NMOS tube connects the 43rd NMOS tube
Drain electrode Nd43, drain electrode Nd44 connect the 44th PMOS drain electrode Pd44, source electrode Ns44 connect
VSS；The grid Ng45 of the 45th NMOS tube connects the drain electrode Nd44 of the 44th NMOS tube, source
Pole Ns45 connects the drain electrode Nd46 of the 46th NMOS tube, drain electrode Nd45 and connects the 49th NMOS
Tube grid Ng49；The grid Ng46 of the 46th NMOS tube connects SN, drain electrode Nd46 and connects the 40th
The source electrode Nd45 of five NMOS tube, source electrode Ns46 connect VSS；The grid Ng47 of the 47th NMOS tube
Connect the drain electrode Nd44 of the 44th NMOS tube, source electrode Ns47 and connect the drain electrode of the 48th NMOS tube
Nd48, drain electrode Nd47 connect the 50th NMOS tube grid Ng50；The grid of the 48th NMOS tube
Ng48 connects SN, drain electrode Nd48 and connects the source electrode Nd47, source electrode Ns48 of the 47th NMOS tube even
Meet VSS.The grid Ng49 of the 49th NMOS tube connects the drain electrode Nd45 of the 45th NMOS tube,
Source electrode Ns49 connects ground VSS, drain electrode Nd49 and connects the drain electrode Pd49 of the 49th PMOS and connect
Outfan SN01；The grid Ng50 of the 50th NMOS tube connects the 47th NMOS tube drain electrode Nd47,
Drain electrode Nd50 connects the drain electrode Nd50 of the 50th PMOS and connects outfan SN02, source electrode Ns50
Connect VSS.
As it is shown in fig. 7, main latch has 11 inputs and two outfans, input is D, D1,
SI, SE, SEN, SN01, SN02, c1, c2, cn1, cn2；Outfan is m1, m1r.Main latch
Device is made up of 18 PMOS and 18 NMOS tube, the substrate of all PMOS in main latch
Connect power vd D, the Substrate ground VSS of all NMOS tube.The grid Pg9 of the 9th PMOS is even
Meet SI, drain electrode Pd9 to connect the source electrode Ps10, source electrode Ps9 of the tenth PMOS and connect power vd D；The
The grid Pg10 of ten PMOS connects SEN, drain electrode Pd10 and connects the source electrode Ps13 of the 13rd PMOS,
Source electrode Ps10 connects Pd9；The grid Pg11 of the 11st PMOS connects SE, drain electrode Pd11 and connects the
The source electrode Ps12 of 12 PMOS, source electrode Ps11 connect power vd D；The grid of the 12nd PMOS
Pg12 connects D, drain electrode Pd12 and connects Ps13, source electrode Ps12 and connect Pd11；13rd PMOS
Grid Pg8 connects c1, drain electrode Pd13 and connects the drain electrode Nd9, source electrode Ps13 of the 9th NMOS tube and connect
Pd10；The grid Pg14 of the 14th PMOS connects SI, drain electrode Pd14 and connects the 15th PMOS
Source electrode Ps15, source electrode Ps14 connect power vd D；The grid Pg15 of the 15th PMOS connects SEN,
Drain electrode Pd15 connects the source electrode Ps18, source electrode Ps15 of the 18th PMOS and connects Pd14；16th PMOS
The grid Pg16 of pipe connects SE, drain electrode Pd16 and connects the source electrode Ps17, source electrode Ps16 of the 17th PMOS
Connect power vd D；The grid Pg17 of the 17th PMOS connects D1, drain electrode Pd17 and connects the 18th
The source electrode Ps18 of PMOS, source electrode Ps17 connect Pd16；The grid Pg18 of the 18th PMOS connects
C2, drain electrode Pd18 connect the drain electrode Nd14, source electrode Ps18 of the 14th NMOS tube and connect Pd15；Tenth
The grid Pg19 of nine PMOS connects the drain electrode Pd13 of the 13rd PMOS, drain electrode Pd19 and connects the tenth
The drain electrode Nd19 of nine NMOS tube, and the outfan m1, source electrode Ps19 as main latch connect electricity
Source VDD；The grid Pg20 of the 20th PMOS connects SN01, drain electrode Pd20 and connects the 19th NMOS
The drain electrode Nd19 of pipe, and connect outfan m1, source electrode Ps20 connects power vd D；21st PMOS
The grid Pg21 of pipe connects the drain electrode Pd18 of the 18th PMOS, drain electrode Pd21 and connects the 21st NMOS
The drain electrode Nd21 of pipe, and as an outfan m1r, the source electrode Ps21 connection power vd D of main latch；
The grid Pg22 of the 22nd PMOS connects SN02, drain electrode Pd22 and connects the 21st NMOS tube
Drain electrode Nd21, and connect outfan m1r, source electrode Ps22 connects power vd D；23rd PMOS
The grid Pg23 of pipe connects Pd22, drain electrode Pd23 and connects the source electrode Ps24 of the 24th PMOS, source electrode
Ps23 connects power vd D；The grid Pg24 of the 24th PMOS connects cn1, drain electrode Pd24 and connects
The drain electrode Nd23 of the 23rd NMOS tube, source electrode Ps24 connect Pd23；The grid of the 25th PMOS
Pole Pg25 connects Pd20, drain electrode Pd25 and connects the source electrode Ps26, source electrode Ps25 of the 26th PMOS
Connect power vd D；The grid Pg26 of the 26th PMOS connects cn2, drain electrode Pd26 and connects second
The drain electrode Nd25 of 15 NMOS tube is also connected with Pd18, and source electrode Ps26 connects Pd25；9th NMOS
The grid Ng9 of pipe connects cn1, drain electrode Nd9 and connects Pd13, source electrode Ns9 and connect the tenth NMOS tube
Drain electrode Nd10；The grid Ng10 of the tenth NMOS tube connects SE, drain electrode Nd10 and connects Ns9, source electrode
Ns10 connects the drain electrode Nd11 of the 11st NMOS tube；The grid Ng11 of the 11st NMOS tube connects SI,
Drain electrode Nd11 connects Ns10, source electrode Ns11 ground connection VSS；The grid Ng12 of the 12nd NMOS tube connects
D, drain electrode Nd12 connect Ns9, source electrode Ns12 and connect the drain electrode Nd13 of the 13rd NMOS tube；13rd
The grid Ng13 of NMOS tube connects SEN, drain electrode Nd13 and connects Ns12, source electrode Ns13 ground connection VSS；
The grid Ng14 of the 14th NMOS tube connects cn2, drain electrode Nd14 and connects Pd18, source electrode Ns14 and connect
The drain electrode Nd15 of the 15th NMOS tube；The grid Ng15 of the 15th NMOS tube connects SE, and drain Nd15
Connect Ns14, source electrode Ns15 and connect the drain electrode Nd16 of the 16th NMOS tube；16th NMOS tube
Grid Ng16 connects SI, drain electrode Nd16 and connects Ns15, source electrode Ns16 ground connection VSS；17th NMOS
The grid Ng17 of pipe connects D1, drain electrode Nd17 and connects Ns14, source electrode Ns17 and connect the 18th NMOS
The drain electrode Nd18 of pipe；The grid Ng18 of the 18th NMOS tube connects SEN, drain electrode Nd18 and connects Ns17,
Source electrode Ns18 ground connection VSS；The grid Ng19 of the 19th NMOS tube connects Pd18, drain electrode Nd19 and connects
Pd20, source electrode Ns19 meet the 20th NMOS tube drain electrode Nd20；The grid Ng20 of the 20th NMOS tube
Connect SN02, drain electrode Nd20 and connect Ns19, source electrode Ns20 ground connection VSS；21st NMOS tube
Grid Ng21 connects Pd18, and drain electrode Nd21 connection Pd22, source electrode Ns21 connect the 22nd NMOS tube
Drain electrode Nd22；The grid Ng22 of the 22nd NMOS tube connects SN01, drain electrode Nd22 and connects Ns21,
Source electrode Ns22 ground connection VSS；The grid Ng23 of the 23rd NMOS tube connects c1, drain electrode Nd23 and connects
Pd24, source electrode Ns23 connect the drain electrode Nd24 of the 24th NMOS tube；24th NMOS tube
Grid Ng24 connects Pd20, drain electrode Nd24 and connects Ns23, source electrode Ns24 ground connection VSS；25th
The grid Ng25 of NMOS tube connects c2, drain electrode Nd25 and connects Pd26, source electrode Ns25 and connect the 26th
The drain electrode Nd26 of NMOS tube；The grid Ng26 of the 26th NMOS tube connects Pd22, and drain Nd26
Connect Ns25, source electrode Ns26 ground connection VSS.9th PMOS, the tenth PMOS, the 11st PMOS
Manage and in the tenth NMOS tube, the 11st NMOS tube, the 13rd NMOS tube composition main latch
Scan Architecture.Set structure in 20th PMOS and the 20th NMOS tube composition main latch.
As shown in Figure 8, having eight inputs and two outfans from latch, input is SN01, SN02,
C1, c2, cn1, cn2, m1, m1r；Outfan is s1, s1r.From latch by 12 PMOS
With 12 NMOS tube compositions, from latch, the substrate of all PMOS connects power vd D, institute
There is the Substrate ground VSS of NMOS tube.The grid Pg27 of the 27th PMOS connects m1r, drain electrode
Pd27 connects the source electrode Ps28, source electrode Ps27 of the 28th PMOS and connects power vd D；28th
The grid Pg28 of PMOS connects cn1, drain electrode Pd28 and connects the drain electrode Nd27 of the 27th NMOS tube,
Source electrode Ps28 connects Pd27；The grid Pg29 of the 29th PMOS connects m1, drain electrode Pd29 and connects
The source electrode Ps30 of the 30th PMOS, source electrode Ps29 connect power vd D；The grid of the 30th PMOS
Pole Pg30 connects cn2, drain electrode Pd30 and connects the drain electrode Nd29, source electrode Ps30 of the 29th NMOS tube
Connect Pd29；The grid Pg31 of the 31st PMOS connects the drain electrode Pd28 of the 28th PMOS,
Drain electrode Pd31 connects the drain electrode Nd31 of the 31st NMOS tube and as from latch outfan
S1, source electrode Ps31 connect power vd D；The grid Pg32 of the 32nd PMOS connects SN01, leakage
Pole Pd32 connects the drain electrode Nd31 of the 31st NMOS tube, and connects outfan s1, and source electrode Ps32 is even
Meet power vd D；The grid Pg33 of the 33rd PMOS connects the drain electrode Pd30 of the 30th PMOS,
Drain electrode Pd33 connects the drain electrode Nd33 of the 33rd NMOS tube, and as from latch outfan
S1r, source electrode Ps33 connect power vd D；The grid Pg34 of the 34th PMOS connects SN02, leakage
Pole Pd34 connects the drain electrode Nd33 of the 33rd NMOS tube, and connects outfan s1r, and source electrode Ps34 is even
Meet power vd D；The grid Pg35 of the 35th PMOS connects Pd34, drain electrode Pd35 and connects the 3rd
The source electrode Ps36 of 16 PMOS, source electrode Ps35 connect power vd D；The grid of the 36th PMOS
Pole Pg36 connects cn1, drain electrode Pd36 and connects the drain electrode Nd35, source electrode Ps36 of the 35th NMOS tube
Connect Pd35；The grid Pg37 of the 37th PMOS connects Pd32, drain electrode Pd37 and connects the 30th
The source electrode Ps38 of eight PMOS, source electrode Ps37 connect power vd D；The grid of the 38th PMOS
Pg38 connects cn2, drain electrode Pd38 and connects the drain electrode Nd37, source electrode Ps38 of the 37th NMOS tube and connect
Pd37；The grid Ng27 of the 27th NMOS tube connects c, drain electrode Nd27 and connects Pd28, source electrode Ns27
Connect the drain electrode Nd28 of the 28th NMOS tube；The grid Ng28 of the 28th NMOS tube connects m1,
Drain electrode Nd28 connects Ns27, source electrode Ns28 ground connection VSS；The grid Ng29 of the 29th NMOS tube
Connect c2, drain electrode Nd29 to connect Pd30, source electrode Ns29 and connect the drain electrode Nd30 of the 30th NMOS tube；
The grid Ng30 of the 30th NMOS tube connects m1r, drain electrode Nd30 and connects Ns29, source electrode Ns30 ground connection
VSS；The grid Ng31 of the 31st NMOS tube connects Pd30, drain electrode Nd31 and connects Pd32, source electrode
Ns31 connects the drain electrode Nd32 of the 32nd NMOS tube；The grid Ng32 of the 32nd NMOS tube is even
Meet SN02, drain electrode Nd32 and connect Ns31, source electrode Ns32 ground connection VSS；The grid of the 33rd NMOS tube
Pole Ng33 connects Pd28, and drain electrode Nd33 connection Pd34, source electrode Ns33 connect the 34th NMOS tube
Drain electrode Nd34；The grid Ng34 of the 34th NMOS tube connects SN01, drain electrode Nd34 and connects Ns33,
Source electrode Ns34 ground connection VSS；The grid Ng35 of the 35th NMOS tube connects c1, drain electrode Nd35 and connects
Pd36, source electrode Ns35 connect the drain electrode Nd36 of the 36th NMOS tube；36th NMOS tube
Grid Ng36 connects Pd32, drain electrode Nd36 and connects Ns35, source electrode Ns36 ground connection VSS；37th
The grid Ng37 of NMOS tube connects c2, drain electrode Nd37 and connects Pd38, source electrode Ns37 and connect the 38th
The drain electrode Nd38 of NMOS tube；The grid Ng38 of the 38th NMOS tube connects Pd34, and drain Nd38
Connect Ns37, source electrode Ns38 ground connection VSS.32nd PMOS and the 32nd NMOS tube group
Become the set structure from latch.
As it is shown in figure 9, the first output buffer has two inputs and an outfan, input connects
S1 and s1r, outfan is Q.Output buffer is made up of two PMOS and two NMOS tube.
The substrate of all PMOS of output buffer connects power vd D, the Substrate ground of all NMOS tube
VSS.The grid Pg51 of the 51st PMOS meets input s1r, drain electrode Pd51 and connects the 51st
The drain electrode Nd51 of NMOS tube, source electrode Ps51 meet power vd D；The grid Pg52 of the 52nd PMOS
Meet Pd51, drain electrode Pd52 and connect the drain electrode Nd52 of the 52nd NMOS tube, and as output buffer
Output Q；Source electrode Ps52 meets power vd D；The grid Ng51 of the 51st NMOS tube connects input
S1, drain electrode Nd51 connect Pd51, source electrode Ns51 ground connection VSS；The grid Ng52 of the 52nd NMOS tube
Meet Nd51, drain electrode Nd52 and connect Pd52, source electrode Ns52 ground connection VSS.
As shown in Figure 10, the second output buffer has two inputs and an outfan, and input connects
S1 and s1r, outfan is QN.Output buffer is made up of a PMOS and a NMOS tube.
The substrate of PMOS connects power vd D, the Substrate ground VSS of NMOS tube.40th PMOS
Grid Pg40 meet input s1, drain electrode Pd40 connects the drain electrode Nd40 of the 40th NMOS tube, and makees
For the outfan QN of buffer circuit, source electrode Ps40 meets power vd D；The grid Ng40 of the 40th NMOS tube
Meet input s1r, drain electrode Nd40 to connect Pd40, and connect outfan QN, source electrode Ns40 ground connection VSS；
Beijing Institute of Atomic Energy's H-13 tandem accelerator can produce LET value and be respectively
2.88MeV·cm2/mg、8.62MeV·cm2/mg、12.6MeV·cm2/ mg and 17.0MeV cm2/mg
Four kinds of ground heavy ion irradiation test environments.By unguyed for the tradition being in normal operating conditions setable
Scan Architecture d type flip flop, the setable Scan Architecture d type flip flop of tradition duplication redundancy reinforcing, time sampling
Setable Scan Architecture d type flip flop, the Chinese patent of Application No. 201110323794.1 reinforced propose
Primary particle inversion resistant setable Scan Architecture d type flip flop and anti-single particle of the present invention overturn and single-ion transient state
Setable Scan Architecture d type flip flop connect respectively identical 1000 grade reverser chain outfan and with
The clock frequency work of 40MHz, the input of 1000 grades of reverser chains connects low level.Foregoing circuit is put
The LET value produced in Beijing Institute of Atomic Energy's H-13 tandem accelerator is respectively 2.88MeV cm2/mg、
8.62MeV·cm2/mg、12.6MeV·cm2/ mg and 21.3MeV cm2The ground heavy ion irradiation of/mg
In test environment, during adding up the heavy ion irradiation of each LET, each setable Scan Architecture d type flip flop occurs
The number of times of mistake output.The total fluence of heavy ion irradiation of every kind of LET is 107ion/cm2.Table 1 is for using north
The tradition that the ground heavy particle irradiation test that capital Atomic Energy Research Institute H-13 tandem accelerator is carried out obtains is unguyed
Setable Scan Architecture d type flip flop, tradition duplication redundancy reinforce setable Scan Architecture d type flip flop,
Setable Scan Architecture d type flip flop, the China of Application No. 201110323794.1 that time sampling is reinforced are special
Primary particle inversion resistant setable Scan Architecture d type flip flop and anti-single particle of the present invention that profit proposes overturn and single
The setable Scan Architecture d type flip flop of particle transient state is respectively 2.88MeV cm in LET value2/mg、
8.62MeV·cm2/mg、12.6MeV·cm2/ mg and 21.3MeV cm2The ground heavy ion of/mg
Make a mistake in irradiation process the number of times exported.The total fluence of heavy ion irradiation of every kind of LET is 107ion/cm2。
From the statistics of table 1 it can be seen that the anti-single particle upset of the present invention and single-ion transient state ability are better than tradition not
Reinforce setable Scan Architecture d type flip flop, time sampling reinforce setable Scan Architecture d type flip flop,
The primary particle inversion resistant setable Scan Architecture D that the Chinese patent of Application No. 201110323794.1 proposes
The setable Scan Architecture d type flip flop that trigger and tradition duplication redundancy are reinforced, is suitable for anti-single particle and turns over
Turn and the standard cell lib of single-ion transient state reinforcing integrated circuit, be applied to the fields such as Aeronautics and Astronautics.
Table 1
Claims (1)
1. anti-single particle upset and the setable Scan Architecture d type flip flop of single-ion transient state, including time
Clock circuit, scan control buffer circuit, main latch, from latch, output buffer, its feature
It is that the setable Scan Architecture d type flip flop of anti-single particle upset and single-ion transient state also includes buffering
Circuit, set buffer circuit, output buffer has 2；Main latch and be redundancy from latch
The latch reinforced；Main latch and from latch tandem, and all with clock circuit, set buffering
Circuit connects；Main latch is also connected with buffer circuit, scan control buffer circuit, from latch also with
First output buffer, the second output buffer are connected；There are five inputs and two outfans；
Five inputs are clock signal input terminal CK, data signal input D, scan control signal respectively
Input SE, scan data input SI and set signal input part SN；Outfan is Q and QN；
Described clock circuit clock circuit has an input and four outfans, and input is CK, defeated
Going out end is c1, c2, cn1, cn2；Clock circuit is made up of 12 PMOS and 14 NMOS；
The grid Pg53 of the 53rd PMOS connects CK, drain electrode Pd53 and connects the 53rd NMOS
The drain electrode Nd53 of pipe；The grid Pg54 of the 54th PMOS connects the 53rd PMOS
Drain electrode Pd53, drain electrode Pd54 connect the drain electrode Nd54, source electrode Ps54 of the 54th NMOS tube and connect
Power vd D；The grid Pg55 of the 55th PMOS connects the drain electrode of the 54th PMOS
Pd54, drain electrode Pd55 connect the drain electrode Nd55, source electrode Ps55 of the 55th NMOS tube and connect power supply
VDD；The grid Pg56 of the 56th PMOS connects the drain electrode Pd55 of the 55th PMOS,
Drain electrode Pd56 connects the drain electrode Nd56, source electrode Ps56 of the 56th NMOS tube and connects power vd D；
The grid Pg57 of the 57th PMOS connects CK, drain electrode Pd57 and connects the 58th PMOS
Source electrode Ps58, source electrode Ps57 connect VDD；The grid Pg58 of the 58th PMOS connects the
The drain electrode Pd56 of 56 PMOS, drain electrode Pd58 connect the drain electrode of the 57th NMOS tube
Nd57, and the outfan cn1, source electrode Ps58 as clock circuit connect Pd57；59th
The grid Pg59 of PMOS connects CK, drain electrode Pd59 and connects the source electrode Ps60 of the 60th PMOS,
Source electrode Ps59 connects VDD；The grid Pg60 of the 60th PMOS connects the 56th PMOS
Drain electrode Pd56, drain electrode Pd60 connect the 59th NMOS tube drain electrode Nd59 and as clock electricity
One outfan cn2, source electrode Ps60 on road connect Pd59；The grid Pg61 of the 61st PMOS
The drain electrode of the 58th PMOS is connected as an outfan c1 of clock circuit, drain electrode Pd61
Pd58, and connect outfan cn1, source electrode Ps61 connects VDD；The grid of the 62nd PMOS
Pg62 connects the grid Ng62 of the 62nd NMOS tube and as an outfan c2 of clock circuit,
Drain electrode Pd62 connects the drain electrode Nd62 of the 62nd NMOS tube and as an output of clock circuit
End cn2, source electrode Ps62 connect VDD；The grid Pg63 of the 63rd PMOS connects outfan
Cn1, drain electrode Pd63 connect outfan c1, source electrode Ps63 and connect VDD；64th PMOS
Grid Pg64 connects outfan cn2, drain electrode Pd64 and connects outfan c2, source electrode Ps64 and connect VDD；
The grid Ng53 of the 53rd NMOS tube connects CK, drain electrode Nd53 and connects the 53rd PMOS
The drain electrode Pd53 of pipe；The grid Ng54 of the 54th NMOS tube connects the 53rd NMOS tube
Drain electrode Nd53, drain electrode Nd54 connect the drain electrode Pd54, source electrode Ns54 of the 54th PMOS even
Meet VSS；The grid Ng55 of the 55th NMOS tube connects the drain electrode of the 54th NMOS tube
Nd54, drain electrode Nd55 connect the drain electrode Pd55, source electrode Ns55 of the 55th PMOS and connect VSS；
The grid Ng56 of the 56th NMOS tube connects the drain electrode Nd55 of the 55th NMOS tube, drain electrode
Nd56 connects the drain electrode Pd56, source electrode Ns56 of the 56th PMOS and connects VSS；57th
The grid Ng57 of NMOS tube connects the drain electrode Nd56, source electrode Ns57 of the 56th NMOS tube even
Meeting the drain electrode Nd58 of the 58th NMOS tube, drain electrode connects cn1；The grid of the 58th NMOS tube
Pole Ng58 connects CK, drain electrode Nd58 and connects the source electrode Nd57 of the 57th NMOS tube, source electrode
Ns58 connects VSS；The grid Ng59 of the 59th NMOS tube connects the 56th NMOS tube
Drain electrode Nd56, source electrode Ns59 connect the drain electrode Nd60 of the 60th NMOS tube, and drain electrode connects cn2；
The grid Ng60 of the 60th NMOS tube connects CK, drain electrode Nd60 and connects the 59th NMOS tube
Source electrode Nd59, source electrode Ns60 connect VSS；The grid Ng61 of the 61st NMOS tube connects defeated
Going out and hold c1, drain electrode Nd61 connects outfan cn2, source electrode Ns61 and connects the 65th NMOS tube
Drain electrode Nd65；The grid Ng62 of the 62nd NMOS tube connects outfan c2, and drain electrode Nd62 is even
Meet outfan cn2, source electrode Ns62 and connect the drain electrode Nd66 of the 66th NMOS tube；63rd
The grid Ng63 of NMOS tube connects outfan cn1, drain electrode Nd63 and connects outfan c1, source electrode Ns63
Connect VSS；The grid Ng64 of the 64th NMOS tube connects outfan cn2, and drain electrode Nd64 is even
Meet outfan c2, source electrode Ns64 and connect VSS；The drain electrode Nd65 of the 65th NMOS tube connects the
The source electrode Ns61 of 61 NMOS tube, grid Ng65 connect outfan c1, source electrode Ns65 and connect
VSS；The drain electrode Nd66 of the 66th NMOS tube connects the source electrode Ns62 of the 62nd NMOS tube,
Grid Ng66 connects outfan c1, source electrode Ns66 and connects VSS；
Described buffer circuit has an input and an outfan, and input is D, and outfan is D1；
Buffer circuit is made up of eight PMOS and eight NMOS tube, all PMOS in buffer circuit
Substrate connect power vd D, the Substrate ground VSS of all NMOS tube；The grid of the first PMOS
Pole Pg1 connects input D and the grid Ng1 with the first NMOS tube connects, and drain electrode Pd1 connects first
The drain electrode Ng1 of NMOS tube, source electrode Ps1 connect VDD；The grid Pg2 of the second PMOS connects
The drain electrode Pd1 of the first PMOS, drain electrode Pd2 connect the drain electrode Nd2 of the second NMOS tube, source electrode
Ps2 connects VDD；The grid Pg3 of the 3rd PMOS connects the drain electrode Pd2 of the second PMOS,
Drain electrode Pd3 connects the drain electrode Nd3, source electrode Ps3 of the 3rd NMOS tube and connects VDD；4th PMOS
The grid Pg4 of pipe connects the drain electrode Pd3 of the 3rd PMOS, drain electrode Pd4 and connects the 4th NMOS tube
Drain electrode Nd4, source electrode Ps4 connect VDD；The grid Pg5 of the 5th PMOS connects the 4th PMOS
The drain electrode Pd4 of pipe, drain electrode Pd5 connect the drain electrode Nd5, source electrode Ps5 of the 5th NMOS tube and connect VDD；
The grid Pg6 of the 6th PMOS connects the drain electrode Pd5 of the 5th PMOS, drain electrode Pd6 and connects the
The drain electrode Nd6 of six NMOS tube, source electrode Ps6 connect VDD；The grid Pg7 of the 7th PMOS is even
Meet the drain electrode Pd6 of the 6th PMOS, drain electrode Pd7 and connect the drain electrode Nd7 of the 7th NMOS tube, source
Pole Ps7 connects VDD；The grid Pg8 of the 8th PMOS connects the drain electrode Pd7 of the 7th PMOS,
Drain electrode Pd8 connects the drain electrode Nd8 of the 8th NMOS tube and as the outfan D1 of buffer, source electrode
Ps8 connects VDD；The grid Ng1 of the first NMOS tube connects Pg1, drain electrode Nd1 and connects Pd1,
Source electrode Ns1 connects VSS；The grid Ng2 of the second NMOS tube connects the drain electrode Nd1 of the first NMOS tube,
Drain electrode Nd2 connects Pd2, source electrode Ns2 and connects VSS；The grid Ng3 of the 3rd NMOS tube connects the
The drain electrode Nd2 of two NMOS tube, drain electrode Nd3 connect Pd3, source electrode Ns3 and connect VSS；4th NMOS
The grid Ng4 of pipe connects the drain electrode Nd3 of the 3rd NMOS tube, drain electrode Nd4 and connects Pd4, source electrode Ns4
Connect VSS；The grid Ng5 of the 5th NMOS tube connects the drain electrode Nd4 of the 4th NMOS tube, drain electrode
Nd5 connects Pd5, source electrode Ns5 and connects VSS；The grid Ng6 of the 6th NMOS tube connects the 5th NMOS
The drain electrode Nd5 of pipe, drain electrode Nd6 connect Pd6, source electrode Ns6 and connect VSS；7th NMOS tube
Grid Ng7 connects the drain electrode Nd6 of the 6th NMOS tube, drain electrode Nd7 and connects Pd7, source electrode Ns7 even
Meet VSS；The grid Ng8 of the 8th NMOS tube connects the drain electrode Nd7 of the 7th NMOS tube, drain electrode
Nd8 connects Pd8, source electrode Ns8 and connects VSS；
Described scan control buffer circuit has an input and an outfan, and input is SE, defeated
Going out end is SEN；Scan control buffer circuit is by the 39th PMOS and the 39th NMOS tube
Composition；Substrate and the source electrode Ps39 of the 39th PMOS are all connected with power vd D, and the 39th
The substrate of NMOS tube and source electrode Ns39 equal ground connection VSS；The grid Pg39 of the 39th PMOS
Connect SE, drain electrode Pd39 and connect the drain electrode Nd39 of the 39th NMOS tube, and as scan control
The outfan SEN of circuit；The grid Ng39 of the 39th NMOS tube connects SE, and drain Nd39
Connect Pd39；
Described set buffer circuit has an input and two outfans, and input is SN, outfan
It is SN01, SN02；Set buffer circuit is made up of ten NMOS tube and ten PMOS, puts
In bit buffering circuit, the substrate of all PMOS connects power vd D, and the substrate of all NMOS tube connects
Ground VSS；The grid Pg41 of the 41st PMOS connects SN, drain electrode Pd41 and connects the 41st
The drain electrode Nd41 of NMOS tube, source electrode Ps41 connect power vd D；The grid of the 42nd PMOS
Pole Pg42 connects the drain electrode Pd41 of the 41st PMOS, drain electrode Pd42 and connects the 42nd NMOS
The drain electrode Nd42 of pipe, source electrode Ps42 connect power vd D；The grid Pg43 of the 43rd PMOS
Connect the drain electrode Pd42 of the 42nd PMOS, drain electrode Pd43 and connect the 43rd NMOS tube
Drain electrode Nd43, source electrode Ps43 connect power vd D；The grid Pg44 of the 44th PMOS connects
The drain electrode Pd43 of the 43rd PMOS, drain electrode Pd44 connect the drain electrode of the 44th NMOS tube
Nd44, source electrode Ps44 connect power vd D；The grid Pg45 of the 45th PMOS connects SN,
Drain electrode Pd45 connects the source electrode Ps46, source electrode Ps45 of the 46th PMOS and connects VDD；4th
The grid Pg46 of 16 PMOS connects the drain electrode Pd44 of the 44th PMOS, and drain Pd46
Connect the drain electrode Nd45 of the 45th NMOS tube；The grid Pg47 of the 47th PMOS connects
SN, drain electrode Pd47 connect the source electrode Ps48, source electrode Ps47 of the 48th PMOS and connect VDD；
The grid Pg48 of the 48th PMOS connects the drain electrode Pd44 of the 44th PMOS, drain electrode
Pd48 connects the drain electrode Nd47, source electrode Ps48 of the 47th NMOS tube and connects the 47th PMOS
The drain electrode Pd47 of pipe；The grid Pg49 of the 49th PMOS connects the 46th PMOS
Drain electrode Pd46, source electrode Ps49 connect power vd D, drain electrode Pd49 and connect the 49th NMOS tube
Drain electrode Nd49 an outfan SN01 as set buffer circuit；The grid of the 50th PMOS
Pole Pg50 connects the drain electrode Pd48, source electrode Ps50 of the 48th PMOS and connects power vd D, leakage
Pole Pd50 connects the drain electrode Nd50 of the 50th NMOS tube and another as set buffer circuit is defeated
Go out to hold SN02；The grid Ng41 of the 41st NMOS tube connects SN, drain electrode Nd41 and connects the 4th
The drain electrode Pd41 of 11 PMOS, source electrode Ns41 connect VSS；The grid of the 42nd NMOS tube
Pole Ng42 connects the drain electrode Nd41 of the 41st NMOS tube, drain electrode Nd42 and connects the 42nd PMOS
The drain electrode Pd42 of pipe, source electrode Ns42 connect VSS；The grid Ng43 of the 43rd NMOS tube connects
The drain electrode Nd42 of the 42nd NMOS tube, drain electrode Nd43 connect the drain electrode of the 43rd PMOS
Pd43, source electrode Ns43 connect VSS；The grid Ng44 of the 44th NMOS tube connects the 43rd
The drain electrode Nd43 of NMOS tube, drain electrode Nd44 connect the drain electrode Pd44 of the 44th PMOS, source
Pole Ns44 connects VSS；The grid Ng45 of the 45th NMOS tube connects the 44th NMOS tube
Drain electrode Nd44, source electrode Ns45 connect the 46th NMOS tube drain electrode Nd46, drain Nd45
Connect the 49th NMOS tube grid Ng49；The grid Ng46 of the 46th NMOS tube connects SN,
Drain electrode Nd46 connects the source electrode Nd45, source electrode Ns46 of the 45th NMOS tube and connects VSS；4th
The grid Ng47 of 17 NMOS tube connects the drain electrode Nd44, source electrode Ns47 of the 44th NMOS tube
Connect the drain electrode Nd48 of the 48th NMOS tube, drain electrode Nd47 and connect the 50th NMOS tube grid
Ng50；The grid Ng48 of the 48th NMOS tube connects SN, drain electrode Nd48 and connects the 47th
The source electrode Nd47 of NMOS tube, source electrode Ns48 connect VSS；The grid Ng49 of the 49th NMOS tube
Connecting the drain electrode Nd45 of the 45th NMOS tube, source electrode Ns49 and connect ground VSS, drain Nd49
Connect the drain electrode Pd49 of the 49th PMOS and connect outfan SN01；50th NMOS tube
Grid Ng50 connect the 47th NMOS tube drain electrode Nd47, drain electrode Nd50 connect the 50th PMOS
The drain electrode Nd50 of pipe also connects outfan SN02, and source electrode Ns50 connects VSS；
Described main latch has 11 inputs and two outfans, and input is D, D1, SI, SE,
SEN, SN01, SN02, c1, c2, cn1, cn2；Outfan is m1, m1r；Main latch by
18 PMOS and 18 NMOS tube compositions, the substrate of all PMOS in main latch
Connect power vd D, the Substrate ground VSS of all NMOS tube；The grid Pg9 of the 9th PMOS
Connect SI, drain electrode Pd9 to connect the source electrode Ps10, source electrode Ps9 of the tenth PMOS and connect power vd D；
The grid Pg10 of the tenth PMOS connects SEN, drain electrode Pd10 and connects the source of the 13rd PMOS
Pole Ps13, source electrode Ps10 connect Pd9；The grid Pg11 of the 11st PMOS connects SE, drain electrode
Pd11 connects the source electrode Ps12, source electrode Ps11 of the 12nd PMOS and connects power vd D；12nd
The grid Pg12 of PMOS connects D, drain electrode Pd12 and connects Ps13, source electrode Ps12 and connect Pd11；
The grid Pg8 of the 13rd PMOS connects c1, drain electrode Pd13 and connects the drain electrode of the 9th NMOS tube
Nd9, source electrode Ps13 connect Pd10；The grid Pg14 of the 14th PMOS connects SI, and drain Pd14
Connect the source electrode Ps15 of the 15th PMOS, source electrode Ps14 and connect power vd D；15th PMOS
The grid Pg15 of pipe connects SEN, drain electrode Pd15 and connects the source electrode Ps18 of the 18th PMOS, source
Pole Ps15 connects Pd14；The grid Pg16 of the 16th PMOS connects SE, drain electrode Pd16 and connects
The source electrode Ps17 of the 17th PMOS, source electrode Ps16 connect power vd D；17th PMOS
Grid Pg17 connect D1, drain electrode Pd17 connect the 18th PMOS source electrode Ps18, source electrode
Ps17 connects Pd16；The grid Pg18 of the 18th PMOS connects c2, drain electrode Pd18 and connects the tenth
The drain electrode Nd14 of four NMOS tube, source electrode Ps18 connect Pd15；The grid Pg19 of the 19th PMOS
Connect the drain electrode Pd13 of the 13rd PMOS, drain electrode Pd19 and connect the drain electrode of the 19th NMOS tube
Nd19, and as an outfan m1, the source electrode Ps19 connection power vd D of main latch；Second
The grid Pg20 of ten PMOS connects SN01, drain electrode Pd20 and connects the drain electrode of the 19th NMOS tube
Nd19, and connect outfan m1, source electrode Ps20 connects power vd D；21st PMOS
Grid Pg21 connects the drain electrode Pd18 of the 18th PMOS, drain electrode Pd21 and connects the 21st NMOS
The drain electrode Nd21 of pipe, and the outfan m1r, source electrode Ps21 as main latch connect power supply
VDD；The grid Pg22 of the 22nd PMOS connects SN02, drain electrode Pd22 and connects the 21st
The drain electrode Nd21 of NMOS tube, and connect outfan m1r, source electrode Ps22 connects power vd D；The
The grid Pg23 of 23 PMOS connects Pd22, drain electrode Pd23 and connects the 24th PMOS
Source electrode Ps24, source electrode Ps23 connect power vd D；The grid Pg24 of the 24th PMOS is even
Meet cn1, drain electrode Pd24 to connect the drain electrode Nd23, source electrode Ps24 of the 23rd NMOS tube and connect Pd23；
The grid Pg25 of the 25th PMOS connects Pd20, drain electrode Pd25 and connects the 26th PMOS
The source electrode Ps26 of pipe, source electrode Ps25 connect power vd D；The grid Pg26 of the 26th PMOS
Connect cn2, drain electrode Pd26 connect the drain electrode Nd25 of the 25th NMOS tube and be connected with Pd18,
Source electrode Ps26 connects Pd25；The grid Ng9 of the 9th NMOS tube connects cn1, drain electrode Nd9 and connects
Pd13, source electrode Ns9 connect the drain electrode Nd10 of the tenth NMOS tube；The grid Ng10 of the tenth NMOS tube
Connect SE, drain electrode Nd10 to connect Ns9, source electrode Ns10 and connect the drain electrode Nd11 of the 11st NMOS tube；
The grid Ng11 of the 11st NMOS tube connects SI, and drain electrode Nd11 connection Ns10, source electrode Ns11 connect
Ground VSS；The grid Ng12 of the 12nd NMOS tube connects D, drain electrode Nd12 and connects Ns9, source electrode
Ns12 connects the drain electrode Nd13 of the 13rd NMOS tube；The grid Ng13 of the 13rd NMOS tube is even
Meet SEN, drain electrode Nd13 and connect Ns12, source electrode Ns13 ground connection VSS；14th NMOS tube
Grid Ng14 connects cn2, drain electrode Nd14 and connects Pd18, source electrode Ns14 and connect the 15th NMOS
The drain electrode Nd15 of pipe；The grid Ng15 of the 15th NMOS tube connects SE, drain electrode Nd15 and connects Ns14,
Source electrode Ns15 connects the drain electrode Nd16 of the 16th NMOS tube；The grid Ng16 of the 16th NMOS tube
Connect SI, drain electrode Nd16 and connect Ns15, source electrode Ns16 ground connection VSS；17th NMOS tube
Grid Ng17 connects D1, drain electrode Nd17 and connects Ns14, source electrode Ns17 and connect the 18th NMOS
The drain electrode Nd18 of pipe；The grid Ng18 of the 18th NMOS tube connects SEN, drain electrode Nd18 and connects
Ns17, source electrode Ns18 ground connection VSS；The grid Ng19 of the 19th NMOS tube connects Pd18, drain electrode
Nd19 connects Pd20, source electrode Ns19 and meets the 20th NMOS tube drain electrode Nd20；20th NMOS
The grid Ng20 of pipe connects SN02, drain electrode Nd20 and connects Ns19, source electrode Ns20 ground connection VSS；The
The grid Ng21 of 21 NMOS tube connects Pd18, drain electrode Nd21 and connects Pd22, source electrode Ns21
Meet the drain electrode Nd22 of the 22nd NMOS tube；The grid Ng22 of the 22nd NMOS tube connects
SN01, drain electrode Nd22 connect Ns21, source electrode Ns22 ground connection VSS；23rd NMOS tube
Grid Ng23 connects c1, drain electrode Nd23 and connects Pd24, source electrode Ns23 and connect the 24th NMOS
The drain electrode Nd24 of pipe；The grid Ng24 of the 24th NMOS tube connects Pd20, and drain electrode Nd24 is even
Meet Ns23, source electrode Ns24 ground connection VSS；The grid Ng25 of the 25th NMOS tube connects c2,
Drain electrode Nd25 connects Pd26, source electrode Ns25 and connects the drain electrode Nd26 of the 26th NMOS tube；The
The grid Ng26 of 26 NMOS tube connects Pd22, drain electrode Nd26 and connects Ns25, source electrode Ns26
Ground connection VSS；9th PMOS, the tenth PMOS, the 11st PMOS and the tenth NMOS
Scan Architecture in pipe, the 11st NMOS tube, the 13rd NMOS tube composition main latch；Second
Set structure in ten PMOS and the 20th NMOS tube composition main latch；
Described have eight inputs and two outfans from latch, and input is SN01, SN02, c1,
C2, cn1, cn2, m1, m1r；Outfan is s1, s1r；From latch by 12 PMOS
With 12 NMOS tube compositions, from latch, the substrate of all PMOS connects power vd D,
The Substrate ground VSS of all NMOS tube；The grid Pg27 of the 27th PMOS connects m1r,
Drain electrode Pd27 connects the source electrode Ps28, source electrode Ps27 of the 28th PMOS and connects power vd D；
The grid Pg28 of the 28th PMOS connects cn1, drain electrode Pd28 and connects the 27th NMOS
The drain electrode Nd27 of pipe, source electrode Ps28 connect Pd27；The grid Pg29 of the 29th PMOS connects
M1, drain electrode Pd29 connect the source electrode Ps30, source electrode Ps29 of the 30th PMOS and connect power vd D；
The grid Pg30 of the 30th PMOS connects cn2, drain electrode Pd30 and connects the 29th NMOS tube
Drain electrode Nd29, source electrode Ps30 connect Pd29；The grid Pg31 of the 31st PMOS connects the
The drain electrode Pd28 of 28 PMOS, drain electrode Pd31 connect the drain electrode Nd31 of the 31st NMOS tube
And connect power vd D as from latch outfan s1, source electrode Ps31；32nd PMOS
The grid Pg32 of pipe connects SN01, drain electrode Pd32 and connects the drain electrode Nd31 of the 31st NMOS tube,
And connect outfan s1, source electrode Ps32 connection power vd D；The grid Pg33 of the 33rd PMOS
Connect the drain electrode Pd30 of the 30th PMOS, drain electrode Pd33 and connect the leakage of the 33rd NMOS tube
Pole Nd33, and connect power vd D as from latch outfan s1r, source electrode Ps33；The
The grid Pg34 of 34 PMOS connects SN02, drain electrode Pd34 and connects the 33rd NMOS
The drain electrode Nd33 of pipe, and connect outfan s1r, source electrode Ps34 connects power vd D；35th PMOS
The grid Pg35 of pipe connects Pd34, drain electrode Pd35 and connects the source electrode Ps36 of the 36th PMOS,
Source electrode Ps35 connects power vd D；The grid Pg36 of the 36th PMOS connects cn1, drain electrode
Pd36 connects the drain electrode Nd35, source electrode Ps36 of the 35th NMOS tube and connects Pd35；37th
The grid Pg37 of PMOS connects Pd32, drain electrode Pd37 and connects the source electrode of the 38th PMOS
Ps38, source electrode Ps37 connect power vd D；The grid Pg38 of the 38th PMOS connects cn2,
Drain electrode Pd38 connects the drain electrode Nd37, source electrode Ps38 of the 37th NMOS tube and connects Pd37；Second
The grid Ng27 of 17 NMOS tube connects c, drain electrode Nd27 and connects Pd28, source electrode Ns27 and connect
The drain electrode Nd28 of the 28th NMOS tube；The grid Ng28 of the 28th NMOS tube connects m1,
Drain electrode Nd28 connects Ns27, source electrode Ns28 ground connection VSS；The grid Ng29 of the 29th NMOS tube
Connect c2, drain electrode Nd29 to connect Pd30, source electrode Ns29 and connect the drain electrode Nd30 of the 30th NMOS tube；
The grid Ng30 of the 30th NMOS tube connects m1r, drain electrode Nd30 and connects Ns29, source electrode Ns30
Ground connection VSS；The grid Ng31 of the 31st NMOS tube connects Pd30, drain electrode Nd31 and connects Pd32,
Source electrode Ns31 connects the drain electrode Nd32 of the 32nd NMOS tube；The grid of the 32nd NMOS tube
Ng32 connects SN02, drain electrode Nd32 and connects Ns31, source electrode Ns32 ground connection VSS；33rd NMOS
The grid Ng33 of pipe connects Pd28, and drain electrode Nd33 connection Pd34, source electrode Ns33 meet the 34th NMOS
The drain electrode Nd34 of pipe；The grid Ng34 of the 34th NMOS tube connects SN01, and drain electrode Nd34 is even
Meet Ns33, source electrode Ns34 ground connection VSS；The grid Ng35 of the 35th NMOS tube connects c1,
Drain electrode Nd35 connects Pd36, source electrode Ns35 and connects the drain electrode Nd36 of the 36th NMOS tube；The
The grid Ng36 of 36 NMOS tube connects Pd32, drain electrode Nd36 and connects Ns35, source electrode Ns36
Ground connection VSS；The grid Ng37 of the 37th NMOS tube connects c2, drain electrode Nd37 and connects Pd38,
Source electrode Ns37 connects the drain electrode Nd38 of the 38th NMOS tube；The grid of the 38th NMOS tube
Ng38 connects Pd34, drain electrode Nd38 and connects Ns37, source electrode Ns38 ground connection VSS；32nd PMOS
Pipe and the 32nd NMOS tube composition set structure from latch；
Described first output buffer has two inputs and an outfan, input connect s1 and
S1r, outfan is Q；Output buffer is made up of two PMOS and two NMOS tube；Defeated
The substrate going out all PMOS of buffer circuit connects power vd D, the Substrate ground of all NMOS tube
VSS；The grid Pg51 of the 51st PMOS meets input s1r, drain electrode Pd51 and connects the 50th
The drain electrode Nd51 of one NMOS tube, source electrode Ps51 meet power vd D；The grid of the 52nd PMOS
Pole Pg52 meets Pd51, drain electrode Pd52 and connects the drain electrode Nd52 of the 52nd NMOS tube, and as defeated
Go out the output Q of buffer circuit；Source electrode Ps52 meets power vd D；The grid of the 51st NMOS tube
Ng51 meets input s1, drain electrode Nd51 and connects Pd51, source electrode Ns51 ground connection VSS；52nd
The grid Ng52 of NMOS tube meets Nd51, drain electrode Nd52 and connects Pd52, source electrode Ns52 ground connection VSS；
Described second output buffer has two inputs and an outfan, input connect s1 and
S1r, outfan is QN；Output buffer is made up of a PMOS and a NMOS tube；
The substrate of PMOS connects power vd D, the Substrate ground VSS of NMOS tube；40th PMOS
The grid Pg40 of pipe meets input s1, drain electrode Pd40 and connects the drain electrode Nd40 of the 40th NMOS tube,
And as the outfan QN of buffer circuit, source electrode Ps40 meets power vd D；40th NMOS tube
Grid Ng40 meets input s1r, drain electrode Nd40 and connects Pd40, and connect outfan QN, source electrode
Ns40 ground connection VSS.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101447786B (en) * | 2008-12-29 | 2010-11-10 | 北京时代民芯科技有限公司 | Buffer cell circuit for resisting single-particle transient state |
| CN102394602A (en) * | 2011-10-21 | 2012-03-28 | 中国人民解放军国防科学技术大学 | Single event upset-resisting scanning structure D trigger capable of setting and resetting |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101447786B (en) * | 2008-12-29 | 2010-11-10 | 北京时代民芯科技有限公司 | Buffer cell circuit for resisting single-particle transient state |
| CN102394602A (en) * | 2011-10-21 | 2012-03-28 | 中国人民解放军国防科学技术大学 | Single event upset-resisting scanning structure D trigger capable of setting and resetting |
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| 标准单元抗单粒子瞬态效应版图加固技术与验证方法研究;刘真;《中国优秀硕士学位论文全文数据库》;20120731;第40页至第42页 * |
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