CN106505976B - A kind of primary particle inversion resistant d type flip flop - Google Patents
A kind of primary particle inversion resistant d type flip flop Download PDFInfo
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- CN106505976B CN106505976B CN201710020099.5A CN201710020099A CN106505976B CN 106505976 B CN106505976 B CN 106505976B CN 201710020099 A CN201710020099 A CN 201710020099A CN 106505976 B CN106505976 B CN 106505976B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
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Abstract
The present invention is suitable for d type flip flop technical field, provides a kind of primary particle inversion resistant d type flip flop.The d type flip flop include: clock signal input circuit, main latch buffer circuit, from latch buffer circuit, main latch and from latch, main latch and from latch be duplication redundancy reinforce latch.Compared to the prior art, the present invention improves the anti-single particle overturning ability of d type flip flop, carries out duplication redundancy reinforcing to main latch and from latch, that is, be separated into the C being mutually redundant by increasing buffer circuit in main latch and before latch2Pull-up PMOS tube and pull-down NMOS pipe in MOS circuit, avoid from the feedback loop as caused by single event transient pulse in latch, to main latch and the C from latch circuit2MOS circuit improves, and control of the clock signal to circuit is realized by cmos transmission gate, further improves the anti-single particle overturning ability of d type flip flop.
Description
Technical field
The invention belongs to d type flip flop technical field more particularly to a kind of primary particle inversion resistant d type flip flops.
Background technique
There are a large amount of high energy particles (proton, electronics, heavy ion etc.) in cosmic space, sequence circuit in integrated circuit by
To after these high-energy particle bombardments, the state kept is likely to occur overturning, this effect is known as Single event upset effecf, simple grain
LET (linear energy transfer) value of son bombardment integrated circuit is higher, is more easy to produce Single event upset effecf.In integrated circuit
After combinational circuit is by these high-energy particle bombardments, it is possible to produce transient electrical pulses, this effect are known as single-ion transient state effect,
The LET value that single-particle bombards integrated circuit is higher, and the transient electrical pulses duration of generation is longer, and electric pulse is easier by timing
Circuit acquisition.The transient electrical pulses quilt that if mistake overturning occurs for the state of sequence circuit or single-ion transient state effect generates
The acquisition of sequence circuit mistake can all cause integrated circuit operation unstable or even generate fatal mistake, this is in space flight, military neck
Domain is particularly acute.Therefore, integrated circuit is carried out reinforcing to reduce Single event upset effecf and single-ion transient state effect is more next
It is more important.
D type flip flop is one of most commonly used timing unit structure in integrated circuit, is determined to the resistance of single-particle inversion
The ability of entire integrated circuit anti-single particle is determined.In some integrated circuits, need d type flip flop state be it is controllable, than
D type flip flop input low level can such as be forced.Increase signal input part and circuit in the structure basis of existing d type flip flop,
The structure of d type flip flop may be implemented, can control the function of d type flip flop by signal, but it is this can d type flip flop anti-single particle turn over
Turn that ability is poor, is not suitable for the IC chip applied to high reliability.
Summary of the invention
The embodiment of the invention provides a kind of primary particle inversion resistant d type flip flops, it is intended to solve d type flip flop in the prior art
Anti-single particle overturns the not high problem of ability.
The embodiment of the invention provides a kind of primary particle inversion resistant d type flip flop, the d type flip flop includes:
Clock signal input circuit, main latch buffer circuit, from latch buffer circuit, main latch and from latch
Device, the main latch and it is described from latch be duplication redundancy reinforce latch；
There are two input terminal and two output ends for the d type flip flop, and two input terminals are respectively clock signal input
CLK and data signal input D is held, two output ends are respectively the first output end Q and second output terminal QN；
The clock signal input circuit respectively with the clock signal input terminal CLK, the main latch and it is described from
Latch connection；
The main latch buffer circuit is connect with the data signal input D, the main latch respectively；
It is described from latch buffer circuit respectively with the main latch, described connect from latch；
It is described also to be connect from latch with the first output end Q and the second output terminal QN.
From the embodiments of the present invention it is found that compared to the prior art, the present invention passes through in main latch and from latch
Preceding increase buffer circuit, improves the anti-single particle overturning ability of d type flip flop, and it is superfluous to carry out bimodulus to main latch and from latch
Remaining reinforcing is separated into the C being mutually redundant2Pull-up PMOS tube and pull-down NMOS pipe in MOS circuit, avoid from latch
The feedback loop as caused by single event transient pulse, to main latch and the C from latch circuit2MOS circuit is changed
Into, control of the clock signal to circuit is realized by cmos transmission gate, further improve d type flip flop anti-single particle overturning
Ability.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those skilled in the art without any creative labor, can be with root
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is the electrical block diagram of the C cell circuit in the prior art based on DICE structure；
Fig. 2 is the structural schematic diagram for the primary particle inversion resistant d type flip flop that first embodiment of the invention provides；
Fig. 3 is clock signal input circuit in the primary particle inversion resistant d type flip flop of first embodiment of the invention offer
Electrical block diagram；
Fig. 4 is main latch buffer circuit in the primary particle inversion resistant d type flip flop of first embodiment of the invention offer
Electrical block diagram；
Fig. 5 is the circuit structure of main latch in the primary particle inversion resistant d type flip flop of first embodiment of the invention offer
Schematic diagram；
Fig. 6 is in the primary particle inversion resistant d type flip flop of first embodiment of the invention offer from latch buffer circuit
Electrical block diagram；
Fig. 7 is the circuit structure in the primary particle inversion resistant d type flip flop of first embodiment of the invention offer from latch
Schematic diagram.
Specific embodiment
To enable goal of the invention, the feature, advantage of the embodiment of the present invention more obvious and understandable, below in conjunction with
Attached drawing in the embodiment of the present invention, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that is retouched
The embodiment stated is only a part of the embodiment of the present invention, and not all embodiments.Based on the embodiments of the present invention, this field
Technical staff's every other embodiment obtained without making creative work belongs to the model that the present invention protects
It encloses.
Referring to Fig. 1, Fig. 1 is the electrical block diagram of the C cell circuit based on DICE structure, DICE structure should be based on
C cell circuit include:
First signal input part IN1, second signal input terminal IN2, signal output end OUT, P-channel metal-oxide-semiconductor MP1, P-channel
Metal-oxide-semiconductor MP2, N-channel MOS pipe MN1, N-channel MOS pipe MN2.The substrate of MP1 and MP2 meets power vd D (not shown), MN1
With the Substrate ground (not shown) of MN2.
Wherein, the grid of MP1 meets the first signal input part IN1, and source electrode meets power vd D, and drain electrode connects the source electrode of MP2；MP2's
Grid meets second signal input terminal IN2, and drain electrode meets signal output end OUT；The grid of MN1 connects the first signal input part IN1, source electrode
The drain electrode of MN2 is connect, drain electrode meets signal output end OUT；The grid of MN2 connects second signal input terminal IN2, source electrode ground connection.
It (is all 0 when the first signal input part IN1 of C cell circuit is identical with the logical value of second signal input terminal IN2
Or all for 1), signal output end OUT provides the logic opposite with the first signal input part IN1 and second signal input terminal IN2
Value, C cell circuit shows as phase inverter at this time；When the logical value of the first signal input part IN1 and second signal input terminal IN2 not
Simultaneously (one for 0 and another is 1), signal output end OUT enters hold mode, the logical value before providing under state.Cause
This, the logic that C cell can be used to masked nodes is overturn, and avoids the first signal input part IN1's or second signal input terminal IN2
The overturning of transient state logic influences output end OUT.
Referring to Fig. 2, Fig. 2 is the structural representation for the primary particle inversion resistant d type flip flop that first embodiment of the invention provides
Figure, the d type flip flop include:
Clock signal input circuit 1, main latch buffer circuit 2, from latch buffer circuit 3, main latch 4 and from lock
Storage 5, main latch 4 and from latch 5 be duplication redundancy reinforce latch.
The d type flip flop there are two input terminal and two output ends, two input terminals be respectively clock signal input terminal CLK and
Data signal input D, two output ends are respectively the first output end Q and second output terminal QN.Wherein, clock signal input terminal
The clock signal of CLK input is CLK0, and the data-signal of data signal input D input is D0.
Clock signal input circuit is connect with clock signal input terminal CLK, main latch and from latch respectively；Main latch
Device buffer circuit is connect with data signal input D, main latch respectively；From latch buffer circuit respectively with main latch,
It is connected from latch；It is also connect from latch with the first output end Q and second output terminal QN.
Referring to Fig. 3, clock signal in the primary particle inversion resistant d type flip flop that Fig. 3 provides for first embodiment of the invention
The electrical block diagram of input circuit, the clock signal input circuit include:
One input terminal and an output end, an input terminal is clock signal input terminal CLK, and an output end is
CLK1。
The clock signal input circuit is made of the first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube.
First PMOS tube, the second PMOS tube substrate connect power vd D (not shown), the first NMOS tube, the 2nd NMOS
The Substrate ground (not shown) of pipe.
Grid Pg1 connection the clock signal input terminal CLK, source electrode Ps1 of first PMOS tube meet power vd D, and drain Pd1 connection
The source electrode Ps2 of second PMOS tube；The grid Pg2 connection clock signal input terminal CLK of second PMOS tube, drain Pd2 connection CLK1；
The grid Ng1 connection clock signal input terminal CLK of first NMOS tube, the drain electrode Nd2 of source electrode Ns1 the second NMOS tube of connection, drain electrode
Nd1 connection CLK1；Grid Ng2 connection clock signal input terminal CLK, source electrode the Ns2 ground connection of second NMOS tube.
Wherein, the first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube form the circuit of a C cell.
The characteristic of the circuit is, when the logical value of the first PMOS tube, the input signal of the second PMOS tube grid is identical, alternatively, when the
When one NMOS tube, the logical value of the input signal of the second NMOS tube grid are identical, output end output and input signal logical value phase
Anti- output signal；And when the first PMOS tube, the logical value of the input signal of the second PMOS tube grid are different, alternatively, when first
When NMOS tube, the logical value difference of the input signal of the second NMOS tube grid, the logical value of output signal is by the shape before holding
State does not change.This C cell structure can guarantee the input of the output signal CLK01 and input terminal CLK of output end CLK1
The logic state of signal CLK0 by single particle effect always on the contrary, and do not influenced.
Referring to Fig. 4, main latch in the primary particle inversion resistant d type flip flop that Fig. 4 provides for first embodiment of the invention
The electrical block diagram of buffer circuit, the main latch buffer circuit include:
One input terminal and two output ends, an input terminal is data signal input D, and two output ends are respectively D1
And D2.
Main latch buffer circuit is by third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the 7th
PMOS tube, the 8th PMOS tube, the 9th PMOS tube, the tenth PMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th
NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube, the tenth NMOS tube composition.
Third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the 7th PMOS tube, the 8th PMOS tube,
Nine PMOS tube, the tenth PMOS tube substrate connect power vd D (not shown), third NMOS tube, the 4th NMOS tube, the 5th NMOS
Pipe, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube, the tenth NMOS tube Substrate ground (do not show in figure
Out).
Grid Pg3 connection the data signal input D, source electrode Ps3 of third PMOS tube meet power vd D, and drain electrode Pd3 connects respectively
Connect the grid Pg4 of the 4th PMOS tube, the drain electrode Nd3 of third NMOS tube, the 4th NMOS tube grid Ng4；The grid of third NMOS tube
Pole Ng3 connection data signal input D, source electrode Ns3 ground connection；The source electrode Ps4 of 4th PMOS tube connects power vd D, drain electrode Pd4 difference
Connect the grid Pg5 of the 5th PMOS tube, the drain electrode Nd4 of the 4th NMOS tube, the 5th NMOS tube grid Ng5；4th NMOS tube source
Pole Ns4 ground connection；The source electrode Ps5 of 5th PMOS tube meets power vd D, and drain electrode Pd5 is separately connected the grid Pg6 of the 6th PMOS tube, the
Five NMOS tubes drain electrode Nd5, the 6th NMOS tube grid Ng6；5th NMOS tube source electrode Ns5 ground connection；The source electrode of 6th PMOS tube
Ps6 meets power vd D, and drain electrode Pd6 is separately connected the drain electrode Nd6 and D1 of the 6th NMOS tube；The source electrode Ns6 of 6th NMOS tube is grounded.
Grid Pg7 the connection data signal input D, source electrode Ps7 of 7th PMOS tube meet power vd D, and drain electrode Pd7 connects respectively
Connect the grid Pg8 of the 8th PMOS tube, the drain electrode Nd7 of the 7th NMOS tube, the tenth NMOS tube grid Ng10；The grid of 7th NMOS tube
Pole Ng7 be separately connected the 8th PMOS tube drain electrode Pd8, the grid Pg9 of the 9th PMOS tube, the 8th NMOS tube drain electrode Nd8, source electrode
Ns7 ground connection；The source electrode Ps8 of 8th PMOS tube meets power vd D；The grid Ng8 of 8th NMOS tube is separately connected the 9th PMOS tube
Drain Pd9, the grid Pg10 of the tenth PMOS tube, the 9th NMOS tube drain electrode Nd9, source electrode Ns8 ground connection；The source electrode of 9th PMOS tube
Ps9 meets power vd D；The grid Ng9 of 9th NMOS tube is separately connected the drain electrode of the drain electrode Pd10, the tenth NMOS tube of the tenth PMOS tube
Nd10, data signal input D and D2, source electrode Ns9 ground connection；The source electrode Ps10 of tenth PMOS tube meets power vd D；Tenth NMOS tube
Source electrode Ns10 ground connection.
The 7th PMOS tube, the 8th PMOS tube, the 9th PMOS tube, the tenth PMOS tube in the main latch buffer circuit and
The DICE unit that seven NMOS tubes, the 8th NMOS tube, the 9th NMOS tube, the tenth NMOS tube form reversely constitutes feedback loop, forms 4
The cascade of interlocking phase inverter, there is 4 storage nodes with phase inverter connected back-to-back in this cellular construction: n0, n1,
N2, n3 can store two pairs of complementary data, and wherein n0 and n2, n1 and n3 are the identical nodes of logic state.With it is traditional mutual
Unlike lock circuit, the grid of the PMOS tube of every level-one and NMOS tube is respectively by previous stage and rear stage in the cellular construction
Output signal triggering.Therefore, the state of each storage node is controlled by the state of its adjacent storage node in the cellular construction,
And adjacent storage node is mutually independent.When the voltage of only one storage node in circuit changes, due to
By the feedback influence of other nodes, the storage state of each storage node will not change in DICE unit.The main latch
Third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube and third NMOS tube, the 4th NMOS in buffer circuit
Pipe, the 5th NMOS tube, the 6th NMOS tube separately constitute four phase inverters two-by-two, and constitute delay circuit.Therefore, data-signal is defeated
The logic state for the signal D01 for entering to hold the input signal D0 of D to obtain at output end D2 after DICE unit buffering should be with input
The logic state for the signal D0 that signal D0 is obtained at output end D1 after phase inverter is delayed is consistent, and has anti-single particle effect
The effect of answering.
Referring to Fig. 5, main latch in the primary particle inversion resistant d type flip flop that Fig. 5 provides for first embodiment of the invention
Electrical block diagram, which includes:
Ten input terminals and an output end, wherein four input terminals are connect with clock signal input terminal CLK respectively, and four
A input terminal is connect with CLK1 respectively, and an input terminal is connect with D1, and an input terminal is connect with D2；One output end is D3.
Main latch is by the 11st PMOS tube, the 12nd PMOS tube, the 13rd PMOS tube, the 14th PMOS tube, the 15th
PMOS tube, the 16th PMOS tube, the 17th PMOS tube, the 18th PMOS tube, the 19th PMOS tube, the 20th PMOS tube, second
11 PMOS tube, the 11st NMOS tube, the 12nd NMOS tube, the 13rd NMOS tube, the 14th NMOS tube, the 15th NMOS tube,
16th NMOS tube, the 17th NMOS tube, the 18th NMOS tube, the 19th NMOS tube, the 20th NMOS tube, the 21st NMOS
Pipe composition.
11st PMOS tube, the 12nd PMOS tube, the 13rd PMOS tube, the 14th PMOS tube, the 15th PMOS tube, the tenth
Six PMOS tube, the 17th PMOS tube, the 18th PMOS tube, the 19th PMOS tube, the 20th PMOS tube, the 21st PMOS tube
Substrate connects power vd D (not shown), the 11st NMOS tube, the 12nd NMOS tube, the 13rd NMOS tube, the 14th NMOS
Pipe, the 15th NMOS tube, the 16th NMOS tube, the 17th NMOS tube, the 18th NMOS tube, the 19th NMOS tube, the 20th
The Substrate ground (not shown) of NMOS tube, the 21st NMOS tube.
Grid Ng11 the connection CLK, source electrode Ns11 of 11st NMOS tube are separately connected the source electrode Ps11 of the 11st PMOS tube
And D1, drain electrode Nd11 are separately connected the drain electrode Pd11, the source electrode Ns14 of the 14th NMOS tube, the 14th PMOS of the 11st PMOS tube
The source electrode Ps14 of pipe, the grid Ng15 of the 15th NMOS tube, the grid Pg16 of the 16th PMOS tube, the 17th NMOS tube grid
The grid Pg18 of Ng17, the 18th PMOS tube；The grid Pg11 connection CLK1 of 11st PMOS tube；The grid of 12nd NMOS tube
Ng12 connection CLK, source electrode Ns12 are separately connected the source electrode Ps12 and D2 of the 12nd PMOS tube, and drain electrode Nd12 is separately connected the 12nd
Drain electrode Pd12, the source electrode Ns13 of the 13rd NMOS tube, the source electrode Ps13 of the 13rd PMOS tube, the 15th PMOS tube of PMOS tube
Grid Pg15, the grid Ng16 of the 16th NMOS tube, the grid Pg17 of the 17th PMOS tube, the 18th NMOS tube grid
Ng18；The grid Pg12 connection CLK1 of 12nd PMOS tube.
The grid Ng13 connection CLK1 of 13rd NMOS tube, drain electrode Nd13 are separately connected the drain electrode of the 13rd PMOS tube
Pd13, the 19th PMOS tube drain electrode Pd19, the 19th NMOS tube drain electrode Nd19；The grid Pg13 connection of 13rd PMOS tube
CLK；The grid Ng14 connection CLK1 of 14th NMOS tube, drain electrode Nd14 are separately connected the drain electrode Pd16 of the 14th PMOS tube, the
20 PMOS tube drain electrode Pd20, the 20th NMOS tube drain electrode Nd20；The grid Pg14 connection CLK of 14th PMOS tube.
The source electrode Ps15 of 15th PMOS tube meets power vd D, the source electrode Ps16 for the 16th PMOS tube of Pd15 connection that drains；The
The drain electrode Pd16 of 16 PMOS tube is separately connected the drain electrode Nd15 of the 15th NMOS tube, the grid Ng19 of the 19th NMOS tube, the
The grid Pg20 of 20 PMOS tube, the grid Pg21 of the 21st PMOS tube, the 21st NMOS tube grid Ng21；15th
The drain electrode Nd16 of the 16th NMOS tube of source electrode Ns15 connection of NMOS tube；The source electrode Ns16 of 16th NMOS tube is grounded；17th
The source electrode Ps17 of PMOS tube meets power vd D, the source electrode Ps18 for the 18th PMOS tube of Pd17 connection that drains；The leakage of 18th PMOS tube
Pole Pd18 be separately connected the 17th NMOS tube drain electrode Nd17, the grid Pg19 of the 19th PMOS tube, the 20th NMOS tube grid
Pole Ng20；The drain electrode Nd18 of the 18th NMOS tube of source electrode Ns17 connection of 17th NMOS tube；The source electrode of 18th NMOS tube
Ns18 ground connection.
The source electrode Ps19 of 19th PMOS tube meets power vd D；The source electrode Ns19 of 19th NMOS tube is grounded；20th PMOS
The source electrode Ps20 of pipe meets power vd D；The source electrode Ns20 of 20th NMOS tube is grounded；The source electrode Ps21 of 21st PMOS tube connects electricity
Source VDD, drain electrode Pd21 are separately connected the drain electrode Nd21 and D3 of the 21st NMOS tube；The source electrode Ns21 of 21st NMOS tube connects
Ground.
The main latch is made of the DICE structural circuit of dual redundant.11st PMOS tube and the 11st NMOS tube structure in figure
The second transmission gate, the 13rd PMOS tube and the 13rd are constituted at the first transmission gate, the 12nd PMOS tube and the 12nd NMOS tube
NMOS tube constitutes third transmission gate, the 14th PMOS tube and the 14th NMOS tube and constitutes the 4th transmission gate, this four transmission gates are equal
Controlled by clock signal, wherein the first, second transmission gate cut-off state and third, the 4th transmission gate to cut-off state opposite.
When the logical value of the signal CLK0 of the port CLK input is 1, the logical value of the signal CLK01 of the port CLK1 input
It is the 0, and first, second transmission gate conducting, third, the shutdown of the 4th transmission gate.The port D1 is separately connected by the first transmission gate
The grid Ng15 of the 15 NMOS tubes and grid Pg16 of the 16th PMOS tube, the port D2 is separately connected the tenth by the second transmission gate
The grid Pg15 of the five PMOS tube and grid Ng16 of the 16th NMOS tube.15th PMOS tube, the 16th PMOS tube, the 15th
NMOS tube, the 16th NMOS tube collectively form the C cell circuit based on DICE structure.Due to aforementioned to " anti-single particle
In the explanation of main latch buffer circuit in the d type flip flop of overturning ", D0 signal and the input of the port D2 of the input of the port D1 are described
The logic state of D01 signal be consistent, therefore the C cell circuit is equivalent to a phase inverter, and signal passes through a node in figure
Output is connected to the phase inverter that the 21st PMOS tube and the 21st NMOS tube are constituted, and passes through the defeated of the main latch
Outlet D3 output signal D02.Due to the presence of C cell circuit, the logic overturning that can be effectively prevented from input signal D0 and D01 is passed
Output end is cast to, at this point, the logic state of the output signal D02 of D3 output should be consistent with D0 and D01.
When the logical value of the signal CLK0 of the port CLK input is 0, the logical value of the signal CLK01 of the port CLK1 input
It is the shutdown of the 1, and first, second transmission gate, third, the 4th transmission gate conducting.At this point, the logic state of a, b node is by by the tenth
Five PMOS tube, the 16th PMOS tube, the 17th PMOS tube, the 18th PMOS tube, the 19th PMOS tube, the 20th PMOS tube,
15 NMOS tubes, the 16th NMOS tube, the 17th NMOS tube, the 18th NMOS tube, the 19th NMOS tube, the 20th NMOS tube structure
At feedback control loop latch, node a is identical as the logic state of node b, and node c is identical as the logic state of node d, node
The logic state of a and node c is on the contrary, the logic state of the output signal D02 of output end D3 remains unchanged.Transistor the 15th
PMOS tube, the 16th PMOS tube, the 15th NMOS tube, the 16th NMOS tube and the 17th PMOS tube, the 18th PMOS tube, the tenth
Seven NMOS tubes, respectively constitute two C cell circuits at the 18th NMOS tube, can be effectively prevented from what node in feedback control loop occurred
Logic overturning travels to output end, ensure that circuit has good anti-single particle ability.
Referring to Fig. 6, from latch in the primary particle inversion resistant d type flip flop that Fig. 6 provides for first embodiment of the invention
The electrical block diagram of buffer circuit, this include: from latch buffer circuit
One input terminal and two output ends, an input terminal connect D3, and two output ends are respectively D4 and D5.
From latch buffer circuit by the 22nd PMOS tube, the 23rd PMOS tube, the 24th PMOS tube, the 20th
Five PMOS tube, the 26th PMOS tube, the 27th PMOS tube, the 28th PMOS tube, the 29th PMOS tube, the 22nd
NMOS tube, the 23rd NMOS tube, the 24th NMOS tube, the 25th NMOS tube, the 26th NMOS tube, the 27th
NMOS tube, the 28th NMOS tube, the 29th NMOS tube composition.
22nd PMOS tube, the 23rd PMOS tube, the 24th PMOS tube, the 25th PMOS tube, the 26th
PMOS tube, the 27th PMOS tube, the 28th PMOS tube, the 29th PMOS tube substrate meet power vd D and (do not show in figure
Out), the 22nd NMOS tube, the 23rd NMOS tube, the 24th NMOS tube, the 25th NMOS, the 26th NMOS tube,
27th NMOS tube, the 28th NMOS tube, the Substrate ground (not shown) of the 29th NMOS.
Grid Pg22 the connection D3, source electrode Ps22 of 22nd PMOS tube meet power vd D, and drain electrode Pd22 is separately connected second
The grid Pg23 of 13 PMOS tube, the drain electrode Nd22 of the 22nd NMOS tube, the 23rd NMOS tube grid Ng23；20th
Grid Ng22 connection D3, source electrode the Ns22 ground connection of two NMOS tubes；The source electrode Ps23 of 23rd PMOS tube meets power vd D, drain electrode
Pd23 is separately connected the grid Pg24 of the 24th PMOS tube, the drain electrode Nd23 of the 23rd NMOS tube, the 24th NMOS tube
Grid Ng24；23rd NMOS tube source electrode Ns23 ground connection；The source electrode Ps24 of 24th PMOS tube meets power vd D, drain electrode
Pd24 is separately connected the grid Pg25 of the 25th PMOS tube, the drain electrode Nd24 of the 24th NMOS tube, the 25th NMOS tube
Grid Ng25；24th NMOS tube source electrode Ns24 ground connection；The source electrode Ps25 of 25th PMOS tube meets power vd D, drain electrode
Pd25 is separately connected the drain electrode Nd25 and D4 of the 25th NMOS tube；The source electrode Ns25 of 25th NMOS tube is grounded.
Grid Pg26 the connection D3, source electrode Ps26 of 26th PMOS tube meet power vd D, and drain electrode Pd26 is separately connected second
The grid Pg27 of 17 PMOS tube, the drain electrode Nd6 of the 26th NMOS tube, the 29th NMOS tube grid Ng29；20th
The grid Ng26 of six NMOS tubes be separately connected the 27th PMOS tube drain electrode Pd27, the 28th PMOS tube grid Pg28,
The drain electrode Nd27 of 27th NMOS tube, source electrode Ns26 ground connection；The source electrode Ps27 of 27th PMOS tube meets power vd D；Second
The grid Ng27 of 17 NMOS tubes is separately connected the grid of the drain electrode Pd28 of the 28th PMOS tube, the 29th PMOS tube
The drain electrode Nd28 of Pg29, the 28th NMOS tube, source electrode Ns27 ground connection；The source electrode Ps28 of 28th PMOS tube meets power vd D；
The grid Ng28 of 28th NMOS tube is separately connected the drain electrode of the drain electrode Pd29, the 29th NMOS tube of the 29th PMOS tube
Nd29, D3 and D5, source electrode Ns28 ground connection；The source electrode Ps29 of 29th PMOS tube meets power vd D；The source of 29th NMOS tube
Pole Ns29 ground connection.
This is essentially identical from latch buffer circuit and the working principle of aforementioned main latch buffer circuit, no longer superfluous herein
It states.
Referring to Fig. 7, from latch in the primary particle inversion resistant d type flip flop that Fig. 7 provides for first embodiment of the invention
Electrical block diagram, from latch should include:
Ten input terminals and two output ends, wherein four input terminals are connect with clock signal input terminal CLK respectively, and four
A input terminal is connect with CLK1 respectively, and an input terminal is connect with D4, and an input terminal is connect with D5；Two output ends are respectively
First output end Q and second output terminal QN.
From latch by the 30th PMOS tube, the 31st PMOS tube, the 32nd PMOS tube, the 33rd PMOS tube,
34th PMOS tube, the 35th PMOS tube, the 36th PMOS tube, the 37th PMOS tube, the 38th PMOS tube,
39 PMOS tube, the 40th PMOS tube, the 30th NMOS tube, the 31st NMOS tube, the 32nd NMOS tube, the 33rd
NMOS tube, the 34th NMOS tube, the 35th NMOS tube, the 36th NMOS tube, the 37th NMOS tube, the 38th
NMOS tube, the 39th NMOS tube, the 40th NMOS tube composition.
30th PMOS tube, the 31st PMOS tube, the 32nd PMOS tube, the 33rd PMOS tube, the 34th
PMOS tube, the 35th PMOS tube, the 36th PMOS tube, the 37th PMOS tube, the 38th PMOS tube, the 39th
PMOS tube, the 40th PMOS tube substrate connect power vd D (not shown), the 30th NMOS tube, the 31st NMOS tube,
32 NMOS tubes, the 33rd NMOS tube, the 34th NMOS tube, the 35th NMOS tube, the 36th NMOS tube, third
17 NMOS tubes, the 38th NMOS tube, the 39th NMOS tube, the Substrate ground (not shown) of the 40th NMOS tube.
Grid Ng30 the connection CLK1, source electrode Ns30 of 30th NMOS tube are separately connected the source electrode Ps30 of the 30th PMOS tube
And D4, drain electrode Nd30 are separately connected the drain electrode Pd30 of the 30th PMOS tube, the source electrode Ns33 of the 33rd NMOS tube, the 33rd
The source electrode Ps33 of PMOS tube, the grid Ng34 of the 34th NMOS tube, the grid Pg35 of the 35th PMOS tube, the 36th
The grid Pg37 of the grid Ng36 of NMOS tube, the 37th PMOS tube；The grid Pg30 connection CLK of 30th PMOS tube；Third
Grid Ng31 the connection CLK1, source electrode Ns31 of 11 NMOS tubes are separately connected the source electrode Ps31 and D5 of the 31st PMOS tube, leakage
Pole Nd31 is separately connected the drain electrode Pd31, the source electrode Ns32 of the 32nd NMOS tube, the 32nd PMOS of the 31st PMOS tube
The source electrode Ps32 of pipe, the grid Pg34 of the 34th PMOS tube, the grid Ng35 of the 35th NMOS tube, the 36th PMOS tube
Grid Pg36, the 37th NMOS tube grid Ng37；The grid Pg31 connection CLK of 31st PMOS tube.
The grid Ng32 connection CLK of 32nd NMOS tube, drain electrode Nd32 are separately connected the drain electrode of the 32nd PMOS tube
Pd32, the 38th PMOS tube drain electrode Pd38, the 38th NMOS tube drain electrode Nd38；The grid of 32nd PMOS tube
Pg32 connection CLK1；The grid Ng33 connection CLK of 33rd NMOS tube, drain electrode Nd33 are separately connected the 33rd PMOS tube
Drain Pd33, the 39th PMOS tube drain electrode Pd39, the 39th NMOS tube drain electrode Nd39；The grid of 33rd PMOS tube
Pole Pg33 connection CLK1.
The source electrode Ps34 of 34th PMOS tube meets power vd D, the source electrode for the 35th PMOS tube of Pd34 connection that drains
Ps35；The drain electrode Pd35 of 35th PMOS tube is separately connected the drain electrode Nd34 of the 34th NMOS tube, the 38th NMOS tube
Grid Ng38, the grid Pg39 of the 39th PMOS tube, the grid Pg40 of the 40th PMOS tube, the 40th NMOS tube grid
Ng40 and second output terminal QN；The drain electrode Nd35 of the 35th NMOS tube of source electrode Ns34 connection of 34th NMOS tube；Third
The source electrode Ns35 of 15 NMOS tubes is grounded.
The source electrode Ps36 of 36th PMOS tube meets power vd D, the source electrode for the 37th PMOS tube of Pd36 connection that drains
Ps37；The drain electrode Pd37 of 37th PMOS tube is separately connected the drain electrode Nd36 of the 36th NMOS tube, the 38th PMOS tube
Grid Pg38, the 39th NMOS tube grid Ng39；The 37th NMOS of source electrode Ns36 connection of 36th NMOS tube
The drain electrode Nd37 of pipe；The source electrode Ns37 of 37th NMOS tube is grounded.
The source electrode Ps38 of 38th PMOS tube meets power vd D；The source electrode Ns38 of 38th NMOS tube is grounded；30th
The source electrode Ps39 of nine PMOS tube meets power vd D；The source electrode Ns39 of 39th NMOS tube is grounded；The source electrode of 40th PMOS tube
Ps40 meets power vd D, and drain electrode Pd40 is separately connected the drain electrode Nd40 and the first output end Q of the 40th NMOS tube；40th NMOS
The source electrode Ns40 of pipe is grounded.
The working principle from latch and aforementioned main latch is essentially identical, and details are not described herein.
Primary particle inversion resistant d type flip flop provided in an embodiment of the present invention, compared to the prior art, the present invention passes through in master
Latch and increase buffer circuit before latch, improve the anti-single particle overturning ability of d type flip flop, to main latch and from
Latch carries out duplication redundancy reinforcing, that is, is separated into the C being mutually redundant2Pull-up PMOS tube and pull-down NMOS pipe in MOS circuit,
It avoids from the feedback loop as caused by single event transient pulse in latch, to main latch and from latch circuit
C2MOS circuit improves, and control of the clock signal to circuit is realized by cmos transmission gate, further improves D triggering
The anti-single particle of device overturns ability.
It should be noted that for the various method embodiments described above, describing for simplicity, therefore, it is stated as a series of
Combination of actions, but those skilled in the art should understand that, the present invention is not limited by the sequence of acts described because
According to the present invention, certain steps can use other sequences or carry out simultaneously.Secondly, those skilled in the art should also know
It knows, the embodiments described in the specification are all preferred embodiments, and related actions and modules might not all be this hair
Necessary to bright.
In the above-described embodiments, it all emphasizes particularly on different fields to the description of each embodiment, there is no the portion being described in detail in some embodiment
Point, it may refer to the associated description of other embodiments.
The above are the descriptions to primary particle inversion resistant d type flip flop provided by the present invention, for those skilled in the art
Member, thought according to an embodiment of the present invention, there will be changes in the specific implementation manner and application range, to sum up, this theory
Bright book content should not be construed as limiting the invention.
Claims (1)
1. a kind of primary particle inversion resistant d type flip flop, which is characterized in that the d type flip flop includes:
Clock signal input circuit, main latch buffer circuit, from latch buffer circuit, main latch and from latch, institute
State main latch and it is described from latch be duplication redundancy reinforce latch；
There are two input terminal and two output ends for the d type flip flop, and two input terminals are respectively clock signal input terminal CLK
With data signal input D, two output ends are respectively the first output end Q and second output terminal QN；
The clock signal input circuit respectively with the clock signal input terminal CLK, the main latch and described from latch
Device connection；
The main latch buffer circuit is connect with the data signal input D, the main latch respectively；
It is described from latch buffer circuit respectively with the main latch, described connect from latch；
It is described also to be connect from latch with the first output end Q and the second output terminal QN；
The clock signal input circuit has an input terminal and an output end, and an input terminal is the clock signal
Input terminal CLK, an output end are CLK1；
The clock signal input circuit is made of the first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube；
First PMOS tube, second PMOS tube substrate connect power vd D, first NMOS tube, the 2nd NMOS
The Substrate ground of pipe；
Grid Pg1 connection the clock signal input terminal CLK, source electrode Ps1 of first PMOS tube meet power vd D, and drain Pd1
Connect the source electrode Ps2 of second PMOS tube；The grid Pg2 connection clock signal input terminal CLK of second PMOS tube,
Drain Pd2 connection CLK1；The grid Ng1 connection clock signal input terminal CLK of first NMOS tube, source electrode Ns1 connection
The drain electrode Nd2 of second NMOS tube, drain Nd1 connection CLK1；The grid Ng2 connection of second NMOS tube clock letter
Number input terminal CLK, source electrode Ns2 ground connection；
The main latch buffer circuit has an input terminal and two output ends, and an input terminal is the data-signal
Input terminal D, two output ends are respectively D1 and D2；
The main latch buffer circuit is by third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the 7th
PMOS tube, the 8th PMOS tube, the 9th PMOS tube, the tenth PMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th
NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube, the tenth NMOS tube composition；
The third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the 7th PMOS
Pipe, the 8th PMOS tube, the 9th PMOS tube, the tenth PMOS tube substrate meet power vd D, the 3rd NMOS
Pipe, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS
The Substrate ground of pipe, the 9th NMOS tube, the tenth NMOS tube；
Grid Pg3 connection the data signal input D, source electrode Ps3 of the third PMOS tube meet power vd D, and drain electrode Pd3 divides
Not Lian Jie the grid Pg4 of the 4th PMOS tube, the drain electrode Nd3 of third NMOS tube, the 4th NMOS tube grid Ng4；The third
The grid Ng3 connection data signal input D, source electrode the Ns3 ground connection of NMOS tube；The source electrode Ps4 of 4th PMOS tube connects
Power vd D, drain electrode Pd4 be separately connected the grid Pg5 of the 5th PMOS tube, the 4th NMOS tube drain electrode Nd4, the 5th NMOS tube grid
Pole Ng5；The 4th NMOS tube source electrode Ns4 ground connection；The source electrode Ps5 of 5th PMOS tube connects power vd D, drain electrode Pd5 difference
Connect the grid Pg6 of the 6th PMOS tube, the drain electrode Nd5 of the 5th NMOS tube, the 6th NMOS tube grid Ng6；5th NMOS
Pipe source electrode Ns5 ground connection；The source electrode Ps6 of 6th PMOS tube meets power vd D, and drain electrode Pd6 is separately connected the leakage of the 6th NMOS tube
Pole Nd6 and D1；The source electrode Ns6 of 6th NMOS tube is grounded；
Grid Pg7 connection the data signal input D, source electrode Ps7 of 7th PMOS tube meet power vd D, and drain electrode Pd7 divides
Do not connect the grid Pg8 of the 8th PMOS tube, the drain electrode Nd7 of the 7th NMOS tube, the tenth NMOS tube grid
Ng10；The grid Ng7 of 7th NMOS tube is separately connected the drain electrode Pd8 of the 8th PMOS tube, the 9th PMOS tube
The drain electrode Nd8 of grid Pg9, the 8th NMOS tube, source electrode Ns7 ground connection；The source electrode Ps8 of 8th PMOS tube meets power vd D；
The grid Ng8 of 8th NMOS tube is separately connected the grid of the drain electrode Pd9 of the 9th PMOS tube, the tenth PMOS tube
The drain electrode Nd9 of Pg10, the 9th NMOS tube, source electrode Ns8 ground connection；The source electrode Ps9 of 9th PMOS tube meets power vd D；Institute
State the 9th NMOS tube grid Ng9 be separately connected the tenth PMOS tube drain electrode Pd10, the tenth NMOS tube drain electrode
Nd10, data signal input D and D2, source electrode Ns9 ground connection；The source electrode Ps10 of tenth PMOS tube meets power vd D；Described
The source electrode Ns10 of ten NMOS tubes is grounded；
The main latch has ten input terminals and an output end, wherein four input terminals are believed with the clock respectively
Number input terminal CLK connection, four input terminals are connect with CLK1 respectively, and an input terminal is connect with D1, described in one
Input terminal is connect with D2；One output end is D3；
The main latch is by the 11st PMOS tube, the 12nd PMOS tube, the 13rd PMOS tube, the 14th PMOS tube, the 15th
PMOS tube, the 16th PMOS tube, the 17th PMOS tube, the 18th PMOS tube, the 19th PMOS tube, the 20th PMOS tube, second
11 PMOS tube, the 11st NMOS tube, the 12nd NMOS tube, the 13rd NMOS tube, the 14th NMOS tube, the 15th NMOS tube,
16th NMOS tube, the 17th NMOS tube, the 18th NMOS tube, the 19th NMOS tube, the 20th NMOS tube, the 21st NMOS
Pipe composition；
It is 11st PMOS tube, the 12nd PMOS tube, the 13rd PMOS tube, the 14th PMOS tube, described
15th PMOS tube, the 16th PMOS tube, the 17th PMOS tube, the 18th PMOS tube, the described 19th
PMOS tube, the 20th PMOS tube, the 21st PMOS tube substrate connect power vd D, the 11st NMOS tube, institute
State the 12nd NMOS tube, the 13rd NMOS tube, the 14th NMOS tube, the 15th NMOS tube, the described 16th
NMOS tube, the 17th NMOS tube, the 18th NMOS tube, the 19th NMOS tube, the 20th NMOS tube, institute
State the Substrate ground of the 21st NMOS tube；
Grid Ng11 the connection CLK, source electrode Ns11 of 11st NMOS tube are separately connected the source electrode Ps11 of the 11st PMOS tube
And D1, drain electrode Nd11 are separately connected the drain electrode Pd11, the source electrode Ns14 of the 14th NMOS tube, institute of the 11st PMOS tube
State the source electrode Ps14 of the 14th PMOS tube, the grid Ng15 of the 15th NMOS tube, the 16th PMOS tube grid
Pg16, the grid Ng17 of the 17th NMOS tube, the 18th PMOS tube grid Pg18；11st PMOS tube
Grid Pg11 connection CLK1；Grid Ng12 the connection CLK, source electrode Ns12 of 12nd NMOS tube are separately connected the 12nd PMOS
The source electrode Ps12 and D2 of pipe, drain electrode Nd12 are separately connected the drain electrode Pd12 of the 12nd PMOS tube, the 13rd NMOS tube
Source electrode Ns13, the source electrode Ps13 of the 13rd PMOS tube, the grid Pg15 of the 15th PMOS tube, the described 16th
The grid Ng16 of NMOS tube, the grid Pg17 of the 17th PMOS tube, the 18th NMOS tube grid Ng18；Described
The grid Pg12 connection CLK1 of 12 PMOS tube；
The grid Ng13 connection CLK1 of 13rd NMOS tube, drain electrode Nd13 are separately connected the drain electrode of the 13rd PMOS tube
Pd13, the 19th PMOS tube drain electrode Pd19, the 19th NMOS tube drain electrode Nd19；13rd PMOS tube
Grid Pg13 connection CLK；The grid Ng14 connection CLK1 of 14th NMOS tube, drain electrode Nd14 are separately connected the described 14th
PMOS tube drain electrode Pd16, the 20th PMOS tube drain electrode Pd20, the 20th NMOS tube drain electrode Nd20；Described
The grid Pg14 connection CLK of 14 PMOS tube；
The source electrode Ps15 of 15th PMOS tube meets power vd D, and drain electrode Pd15 connects the source electrode of the 16th PMOS tube
Ps16；The drain electrode Pd16 of 16th PMOS tube is separately connected the drain electrode Nd15 of the 15th NMOS tube, the described 19th
The grid Ng19 of NMOS tube, the grid Pg20 of the 20th PMOS tube, the 21st PMOS tube grid Pg21, described
The grid Ng21 of 21st NMOS tube；The source electrode Ns15 of 15th NMOS tube connects the drain electrode of the 16th NMOS tube
Nd16；The source electrode Ns16 of 16th NMOS tube is grounded；The source electrode Ps17 of 17th PMOS tube meets power vd D, drain electrode
Pd17 connects the source electrode Ps18 of the 18th PMOS tube；The drain electrode Pd18 of 18th PMOS tube is separately connected the described tenth
Seven NMOS tubes drain electrode Nd17, the grid Pg19 of the 19th PMOS tube, the 20th NMOS tube grid Ng20；It is described
The source electrode Ns17 of 17th NMOS tube connects the drain electrode Nd18 of the 18th NMOS tube；The source electrode of 18th NMOS tube
Ns18 ground connection；
The source electrode Ps19 of 19th PMOS tube meets power vd D；The source electrode Ns19 of 19th NMOS tube is grounded；Described
The source electrode Ps20 of 20 PMOS tube meets power vd D；The source electrode Ns20 of 20th NMOS tube is grounded；21st PMOS
The source electrode Ps21 of pipe meets power vd D, and drain electrode Pd21 is separately connected the drain electrode Nd21 and D3 of the 21st NMOS tube；Described 20th
The source electrode Ns21 of one NMOS tube is grounded；
Described to have an input terminal and two output ends from latch buffer circuit, an input terminal connects D3, two institutes
Stating output end is respectively D4 and D5；
It is described from latch buffer circuit by the 22nd PMOS tube, the 23rd PMOS tube, the 24th PMOS tube, the 20th
Five PMOS tube, the 26th PMOS tube, the 27th PMOS tube, the 28th PMOS tube, the 29th PMOS tube, the 22nd
NMOS tube, the 23rd NMOS tube, the 24th NMOS tube, the 25th NMOS tube, the 26th NMOS tube, the 27th
NMOS tube, the 28th NMOS tube, the 29th NMOS tube composition；
22nd PMOS tube, the 23rd PMOS tube, the 24th PMOS tube, the 25th PMOS
Pipe, the 26th PMOS tube, the 27th PMOS tube, the 28th PMOS tube, the 29th PMOS
The substrate of pipe connects power vd D, the 22nd NMOS tube, the 23rd NMOS tube, the 24th NMOS tube, institute
State the 25th NMOS, the 26th NMOS tube, the 27th NMOS tube, the 28th NMOS tube, described
The Substrate ground of 29th NMOS；
Grid Pg22 the connection D3, source electrode Ps22 of 22nd PMOS tube meet power vd D, and drain electrode Pd22 is separately connected second
The grid Pg23 of 13 PMOS tube, the drain electrode Nd22 of the 22nd NMOS tube, the 23rd NMOS tube grid Ng23；Described
Grid Ng22 connection D3, source electrode the Ns22 ground connection of 22 NMOS tubes；The source electrode Ps23 of 23rd PMOS tube connects power supply
VDD, drain electrode Pd23 are separately connected the grid Pg24 of the 24th PMOS tube, the drain electrode Nd23 of the 23rd NMOS tube, the
The grid Ng24 of 24 NMOS tubes；The 23rd NMOS tube source electrode Ns23 ground connection；The source of 24th PMOS tube
Pole Ps24 meets power vd D, and drain electrode Pd24 is separately connected the drain electrode of the grid Pg25, the 24th NMOS tube of the 25th PMOS tube
The grid Ng25 of Nd24, the 25th NMOS tube；The 24th NMOS tube source electrode Ns24 ground connection；25th PMOS
The source electrode Ps25 of pipe meets power vd D, and drain electrode Pd25 is separately connected the drain electrode Nd25 and D4 of the 25th NMOS tube；Described 20th
The source electrode Ns25 of five NMOS tubes is grounded；
Grid Pg26 the connection D3, source electrode Ps26 of 26th PMOS tube meet power vd D, and drain electrode Pd26 is separately connected described
The grid Pg27 of 27th PMOS tube, the 26th NMOS tube drain electrode Nd6, the 29th NMOS tube grid
Ng29；The grid Ng26 of 26th NMOS tube is separately connected the drain electrode Pd27 of the 27th PMOS tube, described
The drain electrode Nd27 of the grid Pg28 of 28 PMOS tube, the 27th NMOS tube, source electrode Ns26 ground connection；Described 27th
The source electrode Ps27 of PMOS tube meets power vd D；The grid Ng27 of 27th NMOS tube is separately connected the described 28th
PMOS tube drain electrode Pd28, the grid Pg29 of the 29th PMOS tube, the 28th NMOS tube drain electrode Nd28, source
Pole Ns27 ground connection；The source electrode Ps28 of 28th PMOS tube meets power vd D；The grid Ng28 of 28th NMOS tube
It is separately connected the drain electrode Pd29 of the 29th PMOS tube, drain electrode Nd29, D3 and D5 of the 29th NMOS tube, source electrode
Ns28 ground connection；The source electrode Ps29 of 29th PMOS tube meets power vd D；The source electrode Ns29 of 29th NMOS tube connects
Ground；
It is described to have ten input terminals and two output ends from latch, wherein four input terminals are believed with the clock respectively
Number input terminal CLK connection, four input terminals are connect with CLK1 respectively, and an input terminal is connect with D4, described in one
Input terminal is connect with D5；Two output ends are respectively the first output end Q and the second output terminal QN；
It is described from latch by the 30th PMOS tube, the 31st PMOS tube, the 32nd PMOS tube, the 33rd PMOS tube,
34th PMOS tube, the 35th PMOS tube, the 36th PMOS tube, the 37th PMOS tube, the 38th PMOS tube,
39 PMOS tube, the 40th PMOS tube, the 30th NMOS tube, the 31st NMOS tube, the 32nd NMOS tube, the 33rd
NMOS tube, the 34th NMOS tube, the 35th NMOS tube, the 36th NMOS tube, the 37th NMOS tube, the 38th
NMOS tube, the 39th NMOS tube, the 40th NMOS tube composition；
30th PMOS tube, the 31st PMOS tube, the 32nd PMOS tube, the 33rd PMOS
Pipe, the 34th PMOS tube, the 35th PMOS tube, the 36th PMOS tube, the 37th PMOS
Pipe, the 38th PMOS tube, the 39th PMOS tube, the 40th PMOS tube substrate meet power vd D, it is described
30th NMOS tube, the 31st NMOS tube, the 32nd NMOS tube, the 33rd NMOS tube, described
34 NMOS tubes, the 35th NMOS tube, the 36th NMOS tube, the 37th NMOS tube, described
The Substrate ground of 38 NMOS tubes, the 39th NMOS tube, the 40th NMOS tube；
Grid Ng30 the connection CLK1, source electrode Ns30 of 30th NMOS tube are separately connected the source electrode Ps30 of the 30th PMOS tube
And D4, drain electrode Nd30 be separately connected the 30th PMOS tube drain electrode Pd30, the 33rd NMOS tube source electrode Ns33,
Source electrode Ps33, the grid Ng34 of the 34th NMOS tube, the 35th PMOS tube of 33rd PMOS tube
Grid Pg35, the grid Ng36 of the 36th NMOS tube, the 37th PMOS tube grid Pg37；The third
The grid Pg30 connection CLK of ten PMOS tube；The grid Ng31 connection CLK1 of 31st NMOS tube, source electrode Ns31 connect respectively
Meet the source electrode Ps31 and D5 of the 31st PMOS tube, drain electrode Nd31 be separately connected the 31st PMOS tube drain electrode Pd31,
Source electrode Ns32, the source electrode Ps32 of the 32nd PMOS tube, the 34th PMOS tube of 32nd NMOS tube
Grid Pg34, the 35th NMOS tube grid Ng35, the grid Pg36 of the 36th PMOS tube, the third
The grid Ng37 of 17 NMOS tubes；The grid Pg31 connection CLK of 31st PMOS tube；
The grid Ng32 connection CLK of 32nd NMOS tube, drain electrode Nd32 are separately connected the 32nd PMOS tube
Drain Pd32, the 38th PMOS tube drain electrode Pd38, the 38th NMOS tube drain electrode Nd38；Described 30th
The grid Pg32 connection CLK1 of two PMOS tube；The grid Ng33 connection CLK of 33rd NMOS tube, drain electrode Nd33 connect respectively
Meet the drain electrode Pd33, the drain electrode Pd39 of the 39th PMOS tube, the 39th NMOS of the 33rd PMOS tube
The drain electrode Nd39 of pipe；The grid Pg33 connection CLK1 of 33rd PMOS tube；
The source electrode Ps34 of 34th PMOS tube meets power vd D, and drain electrode Pd34 connects the source of the 35th PMOS tube
Pole Ps35；The drain electrode Pd35 of 35th PMOS tube is separately connected the drain electrode Nd34, described of the 34th NMOS tube
The grid Ng38 of 38th NMOS tube, the grid Pg39 of the 39th PMOS tube, the 40th PMOS tube grid
The grid Ng40 and the second output terminal QN of Pg40, the 40th NMOS tube；The source electrode of 34th NMOS tube
Ns34 connects the drain electrode Nd35 of the 35th NMOS tube；The source electrode Ns35 of 35th NMOS tube is grounded；
The source electrode Ps36 of 36th PMOS tube meets power vd D, and drain electrode Pd36 connects the source of the 37th PMOS tube
Pole Ps37；The drain electrode Pd37 of 37th PMOS tube is separately connected the drain electrode Nd36, described of the 36th NMOS tube
The grid Ng39 of the grid Pg38 of 38th PMOS tube, the 39th NMOS tube；The source of 36th NMOS tube
Pole Ns36 connects the drain electrode Nd37 of the 37th NMOS tube；The source electrode Ns37 of 37th NMOS tube is grounded；
The source electrode Ps38 of 38th PMOS tube meets power vd D；The source electrode Ns38 of 38th NMOS tube is grounded；Institute
The source electrode Ps39 for stating the 39th PMOS tube meets power vd D；The source electrode Ns39 of 39th NMOS tube is grounded；Described 4th
The source electrode Ps40 of ten PMOS tube meets power vd D, and drain electrode Pd40 is separately connected the drain electrode Nd40 and described first of the 40th NMOS tube
Output end Q；The source electrode Ns40 of 40th NMOS tube is grounded.
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| CN109687850B (en) * | 2018-12-19 | 2022-09-23 | 安徽大学 | Latch completely tolerating any three-node overturning |
| CN110289846A (en) * | 2019-06-27 | 2019-09-27 | 北京大学深圳研究生院 | A kind of trigger keeping function with data |
| CN110855270B (en) * | 2019-09-04 | 2022-09-23 | 合肥工业大学 | Cross-layer dual-mode redundancy sensitive amplifier type trigger with low overhead |
| CN110995234B (en) * | 2019-12-06 | 2023-04-28 | 上海复旦微电子集团股份有限公司 | Laminated structure for restraining single event transient |
| CN112234954B (en) * | 2020-09-24 | 2023-08-29 | 北京时代民芯科技有限公司 | Single event upset reinforcement trigger circuit structure of node feedback |
| CN114785323B (en) * | 2022-03-31 | 2023-12-19 | 北京时代民芯科技有限公司 | Single event upset resistant power-down data retention trigger circuit |
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| CN106505976A (en) | 2017-03-15 |
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