CN103825577B - Anti-single particle upset and reducible Scan Architecture d type flip flop of single-ion transient state - Google Patents

Anti-single particle upset and reducible Scan Architecture d type flip flop of single-ion transient state Download PDF

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CN103825577B
CN103825577B CN201310674896.7A CN201310674896A CN103825577B CN 103825577 B CN103825577 B CN 103825577B CN 201310674896 A CN201310674896 A CN 201310674896A CN 103825577 B CN103825577 B CN 103825577B
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connects
drain electrode
pmos
nmos tube
grid
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CN103825577A (en
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陈建军
杨茂森
沈广振
陈书明
孙永节
郭阳
梁斌
池雅庆
胡春媚
刘祥远
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National University of Defense Technology
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Abstract

The invention discloses anti-single particle upset and reducible Scan Architecture d type flip flop of single-ion transient state, it is therefore an objective to solve reducible Scan Architecture d type flip flop anti-single particle upset ability and the highest problem of anti-single particle transient state.The present invention is by buffer circuit, scan control buffer circuit, reset buffer circuit, clock circuit, main latch, form from latch and output buffer.Main latch and from latch be redundancy reinforce latch.Main latch and from series of latches, and be all connected with clock circuit, reset buffer circuit.Main latch is also connected with buffer circuit, scan control buffer circuit, is also connected with output buffer from latch.Separate main latch and the C being mutually redundant from latch2MOS circuit improves primary particle inversion resistant ability.Buffer circuits makes not make a mistake under long-term single event transient pulse, and duplication redundancy path further increases the ability of anti-single particle transient state.

Description

Anti-single particle upset and reducible Scan Architecture d type flip flop of single-ion transient state
Technical field
The present invention relates to the D master-slave flip-flop of a kind of resetting structure and Scan Architecture, particularly to a kind of anti-list Particle upset (Single Event Upset, SEU) and anti-single particle transient state (Single Event Transient, SET) reducible Scan Architecture d type flip flop.
Background technology
Cosmic space exists a large amount of high energy particle (proton, electronics, heavy ion etc.), in integrated circuit time Sequence circuit is by after these high-energy particle bombardments, and its state kept is likely to occur upset, and this effect is referred to as Single event upset effecf, the LET(linear energy transfer of single-particle bombardment integrated circuit) value is the highest, more holds It is easily generated Single event upset effecf.Combinational circuit in integrated circuit is by, after these high-energy particle bombardments, having May produce transient electrical pulses, this effect is referred to as single-ion transient state effect, the LET of single-particle bombardment integrated circuit Being worth the highest, the transient electrical pulses persistent period of generation is the longest, and electric pulse is the easiest to be gathered by sequence circuit.As Really the state of sequence circuit makes a mistake upset, or the transient electrical pulses that produces of single-ion transient state effect by time Sequence circuit error gathers, and integrated circuit operation instability all can be caused even to produce fatal mistake, and this is in boat My god, military field is particularly acute.Therefore, integrated circuit is reinforced thus reduce Single event upset effecf More and more important with single-ion transient state effect.
D type flip flop is to use one of most timing unit in integrated circuit, the upset of its anti-single particle and simple grain The anti-single particle of whole integrated circuit is overturn by the ability of sub-transient state and the ability of single-ion transient state plays crucial work With, d type flip flop is reinforced accordingly anti-single particle upset and the single-ion transient state energy that can make integrated circuit Power is improved.
Traditional d type flip flop is D master-slave flip-flop, typically by main latch with from level series of latches structure Become.Common lock storage is replaced with DICE(Dual Interlocked Storage Cell, dual interlocked storage cell) Primary particle inversion resistant d type flip flop can be realized etc. redundancy ruggedized construction.Transform input and output on this basis Port, it is possible to achieve anti-single particle upset simultaneously and single-ion transient state.M.J.Myjak et al. is at The 47th IEEE International Midwest Symposium the 47th IEEE electricity of on Circuits and Systems( Road and the international conference of system Midwest) on " the Enhanced Fault-Tolerant CMOS Memory that delivers Elements " (strengthening fault-tolerant cmos memory cell) (2004, the I-453～I-456 page) upper proposition The DICE circuit of a kind of improvement, this circuit uses DICE circuit to carry out anti-single particle upset and reinforces, and handle Bidirectional data line divide into two write data lines and two read data lines, by the duplication redundancy of data wire, makes Travel to the single event transient pulse of DICE circuit by a certain data wire at any time and be difficult to cause whole The upset of individual circuit state, thus realize the reinforcing for single-ion transient state.But the duplication redundancy of data wire There is positive feedback loop, latch information upset can be produced under the single event transient pulse of longer duration, Anti-single particle transient state ability is the highest.
D.G.Mavis etc. are in IEEE Reliability Physics Symposium(world Reliability Physics meeting) On " the Soft error rate mitigation techniques for modern microcircuits " that deliver (reduce existing Technology for microcircuit soft error rate) (2002 page 216 page-225) propose time sampling D touch Send out device circuit.This circuit introduces delay and voting circuit in the feedback loop of latch data, thus possesses Certain anti-single particle upset and single-ion transient state ability.But voting circuit itself does not possess anti-single particle transient state Ability, under single event transient pulse can output error data, anti-single particle transient state ability is the highest.
The Chinese patent of Application No. 200910046337.5 discloses a kind of anti-single particle upset and single-particle wink The d type flip flop of state.This invention is a kind of d type flip flop being similar to that time sampling structure, including two Variable connector, two delay circuits, two protection gate circuits and three phase inverters, it is achieved that d type flip flop Anti-single particle upset and the reinforcing of single-ion transient state.This patent has an ability of anti-single particle transient state, but due to The outfan Q of the 3rd reverser connects the input VIN0 of second variable connector, defines positive and negative being fed back to Road, can produce latch information upset, anti-single particle transient state under the single event transient pulse of longer duration Ability is the highest.
Common D master-slave flip-flop is unfavorable for detecting circuit at test phase so that test job becomes The most loaded down with trivial details, complicated.Scan Architecture is added on common D master-slave flip-flop architecture basics, can be effective Ground simplifies circuit test work, i.e. can control the defeated of D master-slave flip-flop by scanning signal at test phase Enter, and then control circuit state.
Some integrated circuit needs to control the state of d type flip flop in integrated circuit, forces d type flip flop output low Level and the data wherein stored are set to logical zero.At Scan Architecture d type flip flop original structure base Increase reset circuit and reset signal input on plinth, it is possible to achieve the resetting structure of d type flip flop, and pass through Reset signal controls the reset function of d type flip flop.But current reducible anti-list of Scan Architecture d type flip flop Particle upset and anti-single particle transient state ability are the highest, are unfavorable for the ic core in fields such as Aeronautics and Astronautics Sheet uses.
The Chinese patent of Application No. 201110323927.5 discloses a kind of primary particle inversion resistant reset and sweeps Retouch structure d type flip flop, as it is shown in figure 1, this invention by clock circuit, main latch, from latch, multiple Bit buffering circuit, scan control buffer circuit, output buffer form, can be at the list of higher LET value Normally work under particle bombardment and do not produce single-particle inversion.Owing to this invention is in clock circuit, main latch Do not use buffer circuit before device, so not possessing the ability of anti-single particle transient state, and main latch, from Latch is provided without duplication redundancy, when the LET value of single-particle bombardment is higher, and some node on circuit Upset then can cause whole circuit to overturn.
Summary of the invention
The technical problem to be solved in the present invention is, for current reducible anti-list of Scan Architecture d type flip flop Particle upset ability and the highest problem of anti-single particle transient state, propose a kind of anti-single particle upset and single-particle wink Reducible Scan Architecture d type flip flop of state.
Concretism of the present invention is: carries out duplication redundancy reinforcing to main latch with from latch, can resist list Particle overturns；In clock circuit, add buffer circuit in reset circuit and before main latch, list can be resisted Particle transient state；Cut off the positive feedback loop that may be caused from latch, Ke Yi by single event transient pulse Do not overturn under the anti-single particle transient state of longer duration.
Reducible Scan Architecture d type flip flop of anti-single particle of the present invention upset and single-ion transient state is by buffering electricity Road, scan control buffer circuit, reset buffer circuit, clock circuit, main latch, from latch and defeated Go out buffer circuit composition.Main latch and from latch be redundancy reinforce latch.Main latch and from Latch tandem, and be all connected with clock circuit, reset buffer circuit.Main latch is also electric with buffering Road, scan control buffer circuit are connected, and are also connected with output buffer from latch.
Reducible Scan Architecture d type flip flop of anti-single particle of the present invention upset and anti-single particle transient state has five Input and an outfan.Five inputs are clock signal input terminal CK, data signal input respectively D, scan control signal input SE, scan data input SI and reset signal input RN；Output End is Q.
Clock circuit has an input and four outfans, and input is CK, outfan is c1, c2, cn1, cn2.Clock circuit is made up of 12 PMOS and 14 NMOS, all PMOS in circuit Substrate connects power vd D, the Substrate ground VSS of all NMOS tube.The grid of the 51st PMOS Pole Pg51 connects CK, drain electrode Pd51 and connects the drain electrode Nd51 of the 51st NMOS tube；52nd The grid Pg52 of PMOS connects the drain electrode Pd51 of the 51st PMOS, drain electrode Pd52 and connects the 5th The drain electrode Nd52 of 12 NMOS tube, source electrode Ps52 connect power vd D；53rd PMOS Grid Pg53 connects the drain electrode Pd52 of the 52nd PMOS, drain electrode Pd53 and connects the 53rd NMOS The drain electrode Nd53 of pipe, source electrode Ps53 connect power vd D；The grid Pg54 of the 54th PMOS is even Meet the drain electrode Pd53 of the 53rd PMOS, drain electrode Pd54 and connect the drain electrode of the 54th NMOS tube Nd54, source electrode Ps54 connect power vd D；The grid Pg55 of the 55th PMOS connects CK, leakage Pole Pd55 connects the source electrode Ps56, source electrode Ps55 of the 56th PMOS and connects VDD；56th The grid Pg56 of PMOS connects the drain electrode Pd54 of the 54th PMOS, drain electrode Pd56 and connects the 5th The drain electrode Nd55 of 15 NMOS tube, and as an outfan cn1, the source electrode Ps56 company of clock circuit Meet Pd55；The grid Pg57 of the 57th PMOS connects CK, drain electrode Pd57 and connects the 58th PMOS The source electrode Ps58 of pipe, source electrode Ps57 connect VDD；The grid Pg58 of the 58th PMOS connects the 5th The drain electrode Pd54 of 14 PMOS, drain electrode Pd58 connect the drain electrode Nd57 of the 57th NMOS tube also An outfan cn2, source electrode Ps58 as clock circuit connect Pd57；The grid of the 59th PMOS Pole Pg59 connects the grid Ng59 of the 59th NMOS tube and as an outfan c1 of clock circuit, Drain electrode Pd59 connects the drain electrode Pd56 of the 56th PMOS, and connects outfan cn1, source electrode Ps59 Connect VDD；The grid Pg60 of the 60th PMOS connects the grid Ng60 of the 60th NMOS tube also The drain electrode Nd60 of the 60th NMOS tube is connected as an outfan c2 of clock circuit, drain electrode Pd60 VDD is connected with outfan cn2, source electrode Ps60；The grid Pg61 of the 61st PMOS connects output End cn1, drain electrode Pd61 connect outfan c1, source electrode Ps61 and connect VDD；62nd PMOS Grid Pg62 connects outfan cn2, drain electrode Pd62 and connects outfan c2, source electrode Ps62 and connect VDD；The The grid Ng51 of 51 NMOS tube connects CK, drain electrode Nd51 and connects the leakage of the 51st PMOS Pole Pd51；The grid Ng52 of the 52nd NMOS tube connects the drain electrode Nd51 of the 51st NMOS tube, Drain electrode Nd52 connects the drain electrode Pd52, source electrode Ns52 of the 52nd PMOS and connects VSS；50th The grid Ng53 of three NMOS tube connects the drain electrode Nd52 of the 52nd NMOS tube, drain electrode Nd53 and connects The drain electrode Pd53 of the 53rd PMOS, source electrode Ns53 connect VSS；The grid of the 54th NMOS tube Pole Ng54 connects the drain electrode Nd53 of the 53rd NMOS tube, drain electrode Nd54 and connects the 54th PMOS The drain electrode Pd54 of pipe, source electrode Ns54 connect VSS；The grid Ng55 of the 55th NMOS tube connects the The drain electrode Nd54 of 54 NMOS tube, source electrode Ns55 connect the drain electrode Nd56 of the 56th NMOS tube, Drain electrode connects cn1；The grid Ng56 of the 56th NMOS tube connects CK, drain electrode Nd56 and connects the 5th The source electrode Nd55 of 15 NMOS tube, source electrode Ns56 connect VSS；The grid of the 57th NMOS tube Ng57 connects the drain electrode Nd54, source electrode Ns57 of the 54th NMOS tube and connects the 58th NMOS tube Drain electrode Nd58, drain electrode connect cn2；The grid Ng58 of the 58th NMOS tube connects CK, drain electrode Nd58 connects the source electrode Nd57, source electrode Ns58 of the 57th NMOS tube and connects VSS；59th NMOS The grid Ng59 of pipe connects outfan c1, drain electrode Nd59 and connects outfan cn2, source electrode Ns59 and connect the The drain electrode Nd63 of 63 NMOS tube；The grid Ng60 of the 60th NMOS tube connects outfan c2, Drain electrode Nd60 connects outfan cn2, source electrode Ns60 and connects the drain electrode Nd64 of the 64th NMOS tube；The The grid Ng61 of 61 NMOS tube connects outfan cn1, drain electrode Nd61 and connects outfan c1, source electrode Ns61 connects VSS；The grid Ng62 of the 62nd NMOS tube connects outfan cn2, and drain Nd62 Connect outfan c2, source electrode Ns62 and connect VSS；The drain electrode Nd63 of the 63rd NMOS tube connects the The source electrode Ns59 of 59 NMOS tube, grid Ng63 connect outfan c1, source electrode Ns63 and connect VSS； The drain electrode Nd64 of the 64th NMOS tube connects the source electrode Ns60, grid Ng64 of the 60th NMOS tube Connect outfan c1, source electrode Ns64 and connect VSS.
Buffer circuit has an input and an outfan, and input is D, and outfan is D1.Buffering electricity Routeing eight PMOS and eight NMOS tube compositions, in buffer circuit, the substrate of all PMOS connects Power vd D, the Substrate ground VSS of all NMOS tube.The grid Pg1 of the first PMOS connects defeated Entering D and the grid Ng1 with the first NMOS tube connects, drain electrode Pd1 connects the drain electrode of the first NMOS tube Ng1, source electrode Ps1 connect VDD；The grid Pg2 of the second PMOS connects the drain electrode of the first PMOS Pd1, drain electrode Pd2 connect the drain electrode Nd2, source electrode Ps2 of the second NMOS tube and connect VDD；3rd PMOS The grid Pg3 of pipe connects the drain electrode Pd2 of the second PMOS, drain electrode Pd3 and connects the leakage of the 3rd NMOS tube Pole Nd3, source electrode Ps3 connect VDD；The grid Pg4 of the 4th PMOS connects the leakage of the 3rd PMOS Pole Pd3, drain electrode Pd4 connect the drain electrode Nd4, source electrode Ps4 of the 4th NMOS tube and connect VDD；5th PMOS The grid Pg5 of pipe connects the drain electrode Pd4 of the 4th PMOS, drain electrode Pd5 and connects the leakage of the 5th NMOS tube Pole Nd5, source electrode Ps5 connect VDD；The grid Pg6 of the 6th PMOS connects the leakage of the 5th PMOS Pole Pd5, drain electrode Pd6 connect the drain electrode Nd6, source electrode Ps6 of the 6th NMOS tube and connect VDD；7th PMOS The grid Pg7 of pipe connects the drain electrode Pd6 of the 6th PMOS, drain electrode Pd7 and connects the leakage of the 7th NMOS tube Pole Nd7, source electrode Ps7 connect VDD；The grid Pg8 of the 8th PMOS connects the leakage of the 7th PMOS Pole Pd7, drain electrode Pd8 connect the drain electrode Nd8 of the 8th NMOS tube and as the outfan D1 of buffer, Source electrode Ps8 connects VDD；The grid Ng1 of the first NMOS tube connects Pg1, drain electrode Nd1 and connects Pd1, Source electrode Ns1 connects VSS;The grid Ng2 of the second NMOS tube connects the drain electrode Nd1 of the first NMOS tube, Drain electrode Nd2 connects Pd2, source electrode Ns2 and connects VSS；The grid Ng3 of the 3rd NMOS tube connects second The drain electrode Nd2 of NMOS tube, drain electrode Nd3 connect Pd3, source electrode Ns3 and connect VSS；4th NMOS tube Grid Ng4 connect the 3rd NMOS tube drain electrode Nd3, drain electrode Nd4 connect Pd4, source electrode Ns4 connect VSS；The grid Ng5 of the 5th NMOS tube connects the drain electrode Nd4 of the 4th NMOS tube, and drain electrode Nd5 is even Meet Pd5, source electrode Ns5 and connect VSS；The grid Ng6 of the 6th NMOS tube connects the 5th NMOS tube Drain electrode Nd5, drain electrode Nd6 connect Pd6, source electrode Ns6 and connect VSS；The grid Ng7 of the 7th NMOS tube Connect the drain electrode Nd6 of the 6th NMOS tube, drain electrode Nd7 to connect Pd7, source electrode Ns7 and connect VSS；8th The grid Ng8 of NMOS tube connects the drain electrode Nd7 of the 7th NMOS tube, drain electrode Nd8 and connects Pd8, source electrode Ns8 connects VSS.
Scan control buffer circuit has an input and an outfan, and input is SE, and outfan is SEN.Scan control buffer circuit is made up of the 39th PMOS and the 39th NMOS tube.3rd The substrate of 19 PMOS and source electrode Ps39 are all connected with power vd D, the substrate of the 39th NMOS tube Ground connection VSS equal with source electrode Ns39.The grid Pg39 of the 39th PMOS connects SE, and drain Pd39 Connect the drain electrode Nd39 of the 39th NMOS tube, and as the outfan SEN of scan control circuit；The The grid Ng39 of 39 NMOS tube connects SE, drain electrode Nd39 and connects Pd39.
Reset buffer circuit has an input and two outfans, and input is RN, and outfan is R1, R2.Reset buffer circuit is made up of eight NMOS tube and eight PMOS, all in reset buffer circuit The substrate of PMOS connects power vd D, the Substrate ground VSS of all NMOS tube.41st PMOS The grid Pg41 of pipe connects RN, drain electrode Pd41 and connects the drain electrode Nd41 of the 41st NMOS tube, source electrode Ps41 connects power vd D；The grid Pg42 of the 42nd PMOS connects the 41st PMOS Drain electrode Pd41, drain electrode Pd42 connect the drain electrode Nd42, source electrode Ps42 of the 42nd NMOS tube and connect electricity Source VDD；The grid Pg43 of the 43rd PMOS connects the drain electrode Pd42 of the 42nd PMOS, Drain electrode Pd43 connects the drain electrode Nd43, source electrode Ps43 of the 43rd NMOS tube and connects power vd D；The The grid Pg44 of 44 PMOS connects the drain electrode Pd43 of the 43rd PMOS, and drain Pd44 Connect the drain electrode Nd44 of the 44th NMOS tube, source electrode Ps44 and connect power vd D；45th PMOS The grid Pg45 of pipe connects RN, drain electrode Pd45 and connects the source electrode Ps46 of the 46th PMOS, source electrode Ps45 connects VDD；The grid Pg46 of the 46th PMOS connects the drain electrode of the 44th PMOS Pd44, drain electrode Pd46 connect the drain electrode Nd45 of the 45th NMOS tube, and as reset buffer circuit One outfan R1, source electrode Ps46 connect Pd45；The grid Pg47 of the 47th PMOS connects RN, Drain electrode Pd47 connects the source electrode Ps48, source electrode Ps47 of the 48th PMOS and connects VDD；48th The grid Pg48 of PMOS connects the drain electrode Pd44 of the 44th PMOS, drain electrode Pd48 and connects the 4th The drain electrode Nd47 of 17 NMOS tube, and as an outfan R2, source electrode Ps48 of reset buffer circuit Connect Pd47；The grid Ng41 of the 41st NMOS tube connects RN, drain electrode Nd41 and connects the 41st The drain electrode Pd41 of PMOS, source electrode Ns41 connect VSS；The grid Ng42 of the 42nd NMOS tube Connect the drain electrode Nd41 of the 41st NMOS tube, drain electrode Nd42 and connect the drain electrode of the 42nd PMOS Pd42, source electrode Ns42 connect VSS；The grid Ng43 of the 43rd NMOS tube connects the 42nd NMOS The drain electrode Nd42 of pipe, drain electrode Nd43 connect the drain electrode Pd43, source electrode Ns43 of the 43rd PMOS even Meet VSS；The grid Ng44 of the 44th NMOS tube connects the drain electrode Nd43 of the 43rd NMOS tube, Drain electrode Nd44 connects the drain electrode Pd44, source electrode Ns44 of the 44th PMOS and connects VSS；40th The grid Ng45 of five NMOS tube connects the drain electrode Nd44, source electrode Ns45 of the 44th NMOS tube and connects The drain electrode Nd46 of the 46th NMOS tube, drain electrode Nd45 connect R1；The grid of the 46th NMOS tube Pole Ng46 connects RN, drain electrode Nd46 and connects the source electrode Nd45, source electrode Ns46 of the 45th NMOS tube Connect VSS；The grid Ng47 of the 47th NMOS tube connects the drain electrode Nd44 of the 44th NMOS tube, Source electrode Ns47 connects the drain electrode Nd48 of the 48th NMOS tube, drain electrode Nd47 and connects R2；48th The grid Ng48 of NMOS tube connects RN, drain electrode Nd48 and connects the source electrode Nd47 of the 47th NMOS tube, Source electrode Ns48 connects VSS.
Main latch has 11 inputs and two outfans, and input is D, D1, SI, SE, SEN, R1, R2, c1, c2, cn1, cn2；Outfan is m1, m1r.Main latch is by 18 PMOS With 18 NMOS tube compositions, in main latch, the substrate of all PMOS connects power vd D, institute There is the Substrate ground VSS of NMOS tube.The grid Pg9 of the 9th PMOS connects SI, and drain electrode Pd9 is even Meet the source electrode Ps10 of the tenth PMOS, source electrode Ps9 and connect power vd D；The grid of the tenth PMOS Pg10 connects SEN, drain electrode Pd10 and connects the source electrode Ps13, source electrode Ps10 of the 13rd PMOS and connect Pd9；The grid Pg11 of the 11st PMOS connects SE, drain electrode Pd11 and connects the 12nd PMOS Source electrode Ps12, source electrode Ps11 connect power vd D；The grid Pg12 of the 12nd PMOS connects D, leakage Pole Pd12 connects Ps13, source electrode Ps12 and connects Pd11；The grid Pg13 of the 13rd PMOS connects c1, Drain electrode Pd13 connects the drain electrode Nd9, source electrode Ps13 of the 9th NMOS tube and connects Pd10；14th PMOS The grid Pg14 of pipe connects SI, drain electrode Pd14 and connects the source electrode Ps15, source electrode Ps14 of the 15th PMOS Connect power vd D；The grid Pg15 of the 15th PMOS connects SEN, drain electrode Pd15 and connects the 18th The source electrode Ps18 of PMOS, source electrode Ps15 connect Pd14；The grid Pg16 of the 16th PMOS connects SE, drain electrode Pd16 connect the source electrode Ps17, source electrode Ps16 of the 17th PMOS and connect power vd D； The grid Pg17 of the 17th PMOS connects D1, drain electrode Pd17 and connects the source electrode of the 18th PMOS Ps18, source electrode Ps17 connect Pd16；The grid Pg18 of the 18th PMOS connects c2, and drain Pd18 Connect the drain electrode Nd14 of the 14th NMOS tube, source electrode Ps18 and connect Pd15；The grid of the 19th PMOS Pole Pg19 connects R1, drain electrode Pd19 and connects the source electrode Ps20, source electrode Ps19 of the 20th PMOS and connect Power vd D；The grid Pg20 of the 20th PMOS connects Pd13, drain electrode Pd20 and connects the 20th NMOS The drain electrode Nd20 of pipe, and as an outfan m1r, source electrode Ps20 connection the 19th PMOS of main latch The drain electrode Pd19 of pipe；The grid Pg21 of the 21st PMOS connects R2, drain electrode Pd21 and connects second The source electrode Ps22 of 12 PMOS, source electrode Ps21 connect power vd D；The grid of the 22nd PMOS Pole Pg22 connects Pd18, drain electrode Pd22 and connects the drain electrode Nd20 of the 22nd NMOS tube, and as main One outfan m1, source electrode Ps22 of latch connects the drain electrode Pd21 of the 21st PMOS；Second The grid Pg23 of 13 PMOS connects Pd22, drain electrode Pd23 and connects the source electrode of the 24th PMOS Ps24, source electrode Ps23 connect power vd D；The grid Pg24 of the 24th PMOS connects cn1, leakage Pole Pd24 connects the drain electrode Nd23, source electrode Ps24 of the 23rd NMOS tube and connects Pd23；25th The grid Pg25 of PMOS connects Pd20, drain electrode Pd25 and connects the source electrode Ps26 of the 26th PMOS, Source electrode Ps25 connects power vd D；The grid Pg26 of the 26th PMOS connects cn2, and drain Pd26 Connect drain electrode Nd25 and Pd18 of the 25th NMOS tube, source electrode Ps26 and connect Pd25；9th NMOS The grid Ng9 of pipe connects cn1, drain electrode Nd9 and connects Pd13, source electrode Ns9 and connect the tenth NMOS tube Drain electrode Nd10；The grid Ng10 of the tenth NMOS tube connects SE, drain electrode Nd10 and connects Ns9, source electrode Ns10 connects the drain electrode Nd11 of the 11st NMOS tube；The grid Ng11 of the 11st NMOS tube connects SI, Drain electrode Nd11 connects Ns10, source electrode Ns11 ground connection VSS；The grid Ng12 of the 12nd NMOS tube connects D, drain electrode Nd12 connect Ns9, source electrode Ns12 and connect the drain electrode Nd13 of the 13rd NMOS tube；13rd The grid Ng13 of NMOS tube connects SEN, drain electrode Nd13 and connects Ns12, source electrode Ns13 ground connection VSS； The grid Ng14 of the 14th NMOS tube connects cn2, drain electrode Nd14 and connects Pd18, source electrode Ns14 and connect The drain electrode Nd15 of the 15th NMOS tube；The grid Ng15 of the 15th NMOS tube connects SE, and drain Nd15 Connect Ns14, source electrode Ns15 and connect the drain electrode Nd16 of the 16th NMOS tube；16th NMOS tube Grid Ng16 connects SI, drain electrode Nd16 and connects Ns15, source electrode Ns16 ground connection VSS；17th NMOS The grid Ng17 of pipe connects D1, drain electrode Nd17 and connects Ns14, source electrode Ns17 and connect the 18th NMOS The drain electrode Nd18 of pipe；The grid Ng18 of the 18th NMOS tube connects SEN, drain electrode Nd18 and connects Ns17, Source electrode Ns18 ground connection VSS；The grid Ng19 of the 19th NMOS tube connects Pd18, drain electrode Nd19 and connects Pd20, source electrode Ns19 ground connection VSS；The grid Ng20 of the 20th NMOS tube connects R2, and drain Nd20 Connect Pd20, source electrode Ns20 ground connection VSS；The grid Ng21 of the 21st NMOS tube connects Pd13, Drain electrode Nd21 connects Pd22, source electrode Ns21 ground connection VSS；The grid Ng22 of the 22nd NMOS tube Connect R1, drain electrode Nd22 and connect Pd22, source electrode Ns22 ground connection VSS；The grid of the 23rd NMOS tube Pole Ng23 connects c1, drain electrode Nd23 and connects Pd24, source electrode Ns23 and connect the 24th NMOS tube Drain electrode Nd24；The grid Ng24 of the 24th NMOS tube connects Pd20, drain electrode Nd24 and connects Ns23, Source electrode Ns24 ground connection VSS；The grid Ng25 of the 25th NMOS tube connects c2, drain electrode Nd25 and connects Pd26, source electrode Ns25 connect the drain electrode Nd26 of the 26th NMOS tube；26th NMOS tube Grid Ng26 connects Pd22, drain electrode Nd26 and connects Ns25, source electrode Ns26 ground connection VSS.9th PMOS Pipe, the tenth PMOS, the 11st PMOS and the tenth NMOS tube, the 11st NMOS tube, Scan Architecture in 13rd NMOS tube composition main latch；19th PMOS and the 20th Resetting structure in NMOS tube composition main latch.
Having eight inputs and two outfans from latch, input is R1, R2, c1, c2, cn1, cn2, M1, m1r；Outfan is s1, s1r.From latch by 12 PMOS and 12 NMOS tube groups Becoming, from latch, the substrate of all PMOS connects power vd D, and the substrate of all NMOS tube connects Ground VSS.The grid Pg27 of the 27th PMOS connects m1r, drain electrode Pd27 and connects the 28th PMOS The source electrode Ps28 of pipe, source electrode Ps27 connect power vd D；The grid Pg28 of the 28th PMOS connects Cn1, drain electrode Pd28 connect the drain electrode Nd27, source electrode Ps28 of the 27th NMOS tube and connect Pd27；The The grid Pg29 of 29 PMOS connects m1, drain electrode Pd29 and connects the source electrode of the 30th PMOS Ps30, source electrode Ps29 connect power vd D；The grid Pg30 of the 30th PMOS connects cn2, drain electrode Pd30 connects the drain electrode Nd29, source electrode Ps30 of the 29th NMOS tube and connects Pd29；31st PMOS The grid Pg31 of pipe connects R1, drain electrode Pd31 and connects the source electrode Ps32 of the 32nd PMOS, source electrode Ps31 connects power vd D；The grid Pg32 of the 32nd PMOS connects Pd28, and drain electrode Pd32 is even Meet the drain electrode Nd32 of the 32nd NMOS tube, and as from latch outfan s1r, source electrode Ps32 Connect the drain electrode Pd31 of the 31st PMOS；The grid Pg33 of the 33rd PMOS connects R2, Drain electrode Pd33 connects the source electrode Ps34, source electrode Ps33 of the 34th PMOS and connects power vd D；3rd The grid Pg34 of 14 PMOS connects Pd30, drain electrode Pd34 and connects the leakage of the 34th NMOS tube Pole Nd34, and connect the 33rd PMOS as from latch outfan s1, source electrode Ps34 Drain electrode Pd33；The grid Pg35 of the 35th PMOS connects Pd34, drain electrode Pd35 and connects the 3rd The source electrode Ps36 of 16 PMOS, source electrode Ps35 connect power vd D；The grid of the 36th PMOS Pole Pg36 connects cn1, drain electrode Pd36 and connects drain electrode Nd35 and Pd28 of the 35th NMOS tube, source Pole Ps36 connects Pd35；The grid Pg37 of the 37th PMOS connects Pd32, drain electrode Pd37 and connects The source electrode Ps38 of the 38th PMOS, source electrode Ps37 connect power vd D；38th PMOS Grid Pg38 connect cn2, drain electrode Pd38 connect the 37th NMOS tube drain electrode Nd37 and Pd30, Source electrode Ps38 connects Pd37；The grid Ng27 of the 27th NMOS tube connects c, drain electrode Nd27 and connects Pd28, source electrode Ns27 connect the drain electrode Nd28 of the 28th NMOS tube；28th NMOS tube Grid Ng28 connects m1, drain electrode Nd28 and connects Ns27, source electrode Ns28 ground connection VSS；29th NMOS The grid Ng29 of pipe connects c2, drain electrode Nd29 and connects Pd30, source electrode Ns29 and connect the 30th NMOS The drain electrode Nd30 of pipe；The grid Ng30 of the 30th NMOS tube connects m1r, drain electrode Nd30 and connects Ns29, Source electrode Ns30 ground connection VSS；The grid Ng31 of the 31st NMOS tube connects Pd30, and drain Nd31 Connect Pd32, source electrode Ns31 ground connection VSS；The grid Ng32 of the 32nd NMOS tube connects R2, leakage Pole Nd32 connects Pd32, source electrode Ns32 ground connection VSS；The grid Ng33 of the 33rd NMOS tube connects Pd28, drain electrode Nd33 connect Pd34, source electrode Ns33 ground connection VSS；The grid of the 34th NMOS tube Ng34 connects R1, drain electrode Nd34 and connects Pd34, source electrode Ns34 ground connection VSS；35th NMOS The grid Ng35 of pipe connects c1, drain electrode Nd35 and connects Pd36, source electrode Ns35 and connect the 36th NMOS The drain electrode Nd36 of pipe；The grid Ng36 of the 36th NMOS tube connects Pd32, drain electrode Nd36 and connects Ns35, source electrode Ns36 ground connection VSS；The grid Ng37 of the 37th NMOS tube connects c2, and drain Nd37 Connect Pd38, source electrode Ns37 and connect the drain electrode Nd38 of the 38th NMOS tube；38th NMOS The grid Ng38 of pipe connects Pd34, drain electrode Nd38 and connects Ns37, source electrode Ns38 ground connection VSS；30th One PMOS and the 32nd NMOS tube composition resetting structure from latch.
Output buffer has two inputs and an outfan, and input connects s1 and s1r, and outfan is Q.Output buffer is made up of two PMOS and two NMOS tube.Output buffer owns The substrate of PMOS connects power vd D, the Substrate ground VSS of all NMOS tube.49th PMOS The grid Pg49 of pipe meets input s1r, drain electrode Pd49 and connects the drain electrode Nd49 of the 49th NMOS tube, Source electrode Ps49 meets power vd D；The grid Pg50 of the 50th PMOS meets Pd49, drain electrode Pd50 and connects The drain electrode Nd50 of the 50th NMOS tube, and as the output Q of output buffer；Source electrode Ps50 connects electricity Source VDD；The grid Ng49 of the 49th NMOS tube meets input s1, drain electrode Nd49 and connects Pd49, Source electrode Ns49 ground connection VSS；The grid Ng50 of the 50th NMOS tube meets Nd49, drain electrode Nd50 and connects Pd50, source electrode Ns50 ground connection VSS.
Reducible Scan Architecture d type flip flop of anti-single particle of the present invention upset and anti-single particle transient state is worked Journey is as follows:
Anti-single particle of the present invention overturn reducible Scan Architecture d type flip flop be in scanning mode time marquis also Reset state, i.e. scanning mode and reset state can be entered can exist simultaneously.Anti-single particle of the present invention overturns Reducible Scan Architecture d type flip flop can reset at any time, and reset function is i.e. resetted by RN Signal input part controls.
When RN be low level, SE be any level time, anti-single particle of the present invention upset reducible scanning knot Structure d type flip flop all enters reset state, i.e. main latch and from latch all by latching logic by force " 0 ", The outfan Q of output buffer is low level.
When RN be high level, SE be low level time, anti-single particle of the present invention overturns reducible Scan Architecture D type flip flop is in normal operating conditions.Buffer circuit receives D, produces the D1 with D homophase.Clock circuit Receive CK, after it is buffered, produce the cn1 anti-phase with CK by the inverter circuit of circuit intermediate formation And cn2, produce c1 and c2 with CK homophase by the inverter circuit of circuit end, and cn1, cn2, C1 and c2 is passed to main latch and from latch.Buffer circuits receives D, exports after being postponed by D With the D1 of D homophase, be between low period at CK, cn1 and cn2 be high level, c1 and c2 be low level, Main latch open, receive D and D1, and in D and D1 may with single event transient pulse carry out Filter, then by latch output and m1 and m1r of D, D1 homophase, be in preservation shape from latch State, does not receive m1, m1r of main latch output, but preserve m1 that a CK trailing edge samples, m1r；Be between high period at CK, cn1 and cn2 be low level, c1 and c2 be high level, main latch Be in preservation state, preserve D Yu D1 the m1 exporting homophase that previous CK rising edge samples and M1r, opens and receives output m1 and m1r of main latch, buffer m1 and m1r from latch And export s1 and s1r with m1 and m1r homophase.Output buffer will receive from latch at any time Output s1 and s1r of device, buffers and exports the Q with s1 and s1r homophase to s1 and s1r.
When RN be high level, SE be high level time, anti-single particle of the present invention upset and anti-single particle transient state Reducible Scan Architecture d type flip flop is in scanning mode.Clock circuit receives CK, after buffering it Cn1 and cn2 anti-phase with CK is produced, by circuit end by the inverter circuit of circuit intermediate formation Inverter circuit produces c1 and c2 with CK homophase, and cn1, cn2, c1 and c2 are passed to main latch Device and from latch.Be between low period at CK, cn1 and cn2 be high level, c1 and c2 be low level, Main latch is opened, and exports m1 and m1r of homophase, from latch after receiving SI and it being carried out buffered Device is in preservation state, does not receive m1, m1r of main latch output, but preserves a CK and decline Along m1, m1r of sampling；Being between high period at CK, cn1 and cn2 is that low level, c1 and c2 are High level, main latch is in preservation state, preserve SI that previous CK rising edge samples and export with M1 and m1r of phase, opens and receives output m1 and m1r of main latch, to m1 and m1r from latch Carry out buffering and exporting and s1 and s1r of m1 and m1r homophase.Output buffer will connect at any time Receive output s1 and s1r from latch, s1 and s1r buffers and export the Q with s1 and s1r homophase.
Scan control buffer circuit exports the SEN anti-phase with SE after input signal carries out buffered, and will It sends into main latch, is scanned the control of behavior.
Reset buffer circuit input signal is postponed after by the C of duplication redundancy2MOS structure filters can in RN Can with single event transient pulse, and by output with R1 and R2 of RN homophase send into main latch and From latch, carry out the control of reset behavior.
Use the present invention can reach techniques below effect:
The anti-list of reducible Scan Architecture d type flip flop of anti-single particle of the present invention upset and anti-single particle transient state Particle upset and anti-single particle transient state ability be better than the unguyed reducible Scan Architecture d type flip flop of tradition, Reducible Scan Architecture d type flip flop of time sampling reinforcing and reducible the sweeping of tradition duplication redundancy reinforcing Retouch structure d type flip flop.The unguyed reducible Scan Architecture d type flip flop structure of tradition is carried out by the present invention Transformation, to main latch with all carried out duplication redundancy reinforcing from latch, and for main latch with from lock C in storage2MOS circuit is improved, and i.e. separates the C being mutually redundant2Pull-up in MOS circuit PMOS and pull-down NMOS pipe, improve the primary particle inversion resistant ability of the present invention.In clock circuit, Add buffer circuit in reset circuit and before main latch, make the present invention in long-term single-particle wink Do not make a mistake under state pulse；By well-designed duplication redundancy path, cutting off may be by list from latch The positive feedback loop that particle transient pulse causes, further increases the ability of anti-single particle transient state.The present invention Reducible Scan Architecture d type flip flop of anti-single particle upset and single-ion transient state is suitable for anti-single particle and turns over Turn and the standard cell lib of anti-single particle transient state reinforcing integrated circuit, be applied to the fields such as Aeronautics and Astronautics.
Accompanying drawing explanation
Fig. 1 is that the primary particle inversion resistant Scan Architecture D that resets of Application No. 201110323927.5 triggers Device overall logic structural representation
Fig. 2 is that reducible Scan Architecture d type flip flop of anti-single particle of the present invention upset and single-ion transient state is total Body logical structure schematic diagram.
Fig. 3 is in reducible Scan Architecture d type flip flop of anti-single particle of the present invention upset and single-ion transient state Clock circuit structural representation.
Fig. 4 is in reducible Scan Architecture d type flip flop of anti-single particle of the present invention upset and single-ion transient state Buffer circuit structure schematic diagram.
Fig. 5 is in reducible Scan Architecture d type flip flop of anti-single particle of the present invention upset and single-ion transient state Scan control buffer circuit structure schematic diagram.
Fig. 6 is in reducible Scan Architecture d type flip flop of anti-single particle of the present invention upset and single-ion transient state Reset buffer circuit structure schematic diagram.
Fig. 7 is in reducible Scan Architecture d type flip flop of anti-single particle of the present invention upset and single-ion transient state Main latch structural representation.
Fig. 8 is in reducible Scan Architecture d type flip flop of anti-single particle of the present invention upset and single-ion transient state From latch structure schematic diagram.
Fig. 9 is in reducible Scan Architecture d type flip flop of anti-single particle of the present invention upset and single-ion transient state Output buffer structural representation.
Detailed description of the invention
Fig. 2 is that the Scan Architecture d type flip flop logical structure of anti-single particle of the present invention upset and single-ion transient state is shown It is intended to.The present invention is by clock circuit (as shown in Figure 3), buffer circuits (as shown in Figure 4), scanning control Buffer circuit processed (as shown in Figure 5), reset buffer circuit (as shown in Figure 6), main latch are (such as Fig. 7 Shown in), from latch (as shown in Figure 8), output buffer (as shown in Figure 9) composition.The present invention Reducible Scan Architecture d type flip flop of anti-single particle upset and anti-single particle transient state has five inputs and Individual outfan.Five inputs are clock signal input terminal CK, data signal input D, scanning control respectively Signal input part SE processed, scan data input SI and reset signal input RN；Outfan is Q.Time Clock circuit receives CK, exports c1, c2 and cn1, cn2 after CK is carried out buffered respectively.Buffering electricity Road receives D, exports D1 after D is carried out buffered respectively.Scan control buffer circuit receives SE, right SE exports SEN after carrying out buffered.Reset buffer circuit receives RN, after RN is carried out buffered Output R1 and R2.Main latch receives D, D1, SI, SE, SEN, R1, R2, c1, c2, cn1, cn2.When R1 and R2 is high level, main latch exports " 0 ", " 0 " after " 0 " carries out latch process； From latch c1, c2 and cn1, cn2 control " 0 ", " 0 " are carried out latch process after export respectively “0”、“0”；Output buffering road receives " 0 ", " 0 ", exports " 0 " after it is carried out buffered.Work as R1 With R2 be low level, SE be low level time, main latch c1, c2 and cn1, cn2 control under to D M1, m1r is exported after carrying out latch process with D1；From latch receive m1, m1r and c1, c2 and cn1, Cn2, from latch c1, c2 and cn1, cn2 control m1, m1r are carried out latch process after respectively Output s1, s1r；Output buffer receives s1, s1r, exports Q after it is carried out buffered.Work as R1 With R2 be low level, SE be high level time, main latch c1, c2 and cn1, cn2 control under right SI exports m1, m1r after carrying out latch process；From latch receive m1, m1r and c1, c2 and cn1, Cn2, from latch c1, c2 and cn1, cn2 control m1, m1r are carried out latch process after respectively Output s1, s1r；Output buffer receives s1, s1r, exports Q after it is carried out buffered.
As it is shown on figure 3, clock circuit has an input and four outfans, input is CK, outfan For c1, c2, cn1, cn2.Clock circuit is made up of, in circuit 12 PMOS and 14 NMOS The substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube.50th The grid Pg51 of one PMOS connects CK, drain electrode Pd51 and connects the drain electrode of the 51st NMOS tube Nd51；The grid Pg52 of the 52nd PMOS connects the drain electrode Pd51 of the 51st PMOS, leakage Pole Pd52 connects the drain electrode Nd52, source electrode Ps52 of the 52nd NMOS tube and connects power vd D；5th The grid Pg53 of 13 PMOS connects the drain electrode Pd52 of the 52nd PMOS, drain electrode Pd53 and connects The drain electrode Nd53 of the 53rd NMOS tube, source electrode Ps53 connect power vd D；54th PMOS The grid Pg54 of pipe connects the drain electrode Pd53 of the 53rd PMOS, drain electrode Pd54 and connects the 54th The drain electrode Nd54 of NMOS tube, source electrode Ps54 connect power vd D；The grid of the 55th PMOS Pg55 connects CK, drain electrode Pd55 and connects the source electrode Ps56, source electrode Ps55 of the 56th PMOS and connect VDD；The grid Pg56 of the 56th PMOS connects the drain electrode Pd54 of the 54th PMOS, leakage Pole Pd56 connects the drain electrode Nd55 of the 55th NMOS tube, and as an outfan cn1 of clock circuit, Source electrode Ps56 connects Pd55；The grid Pg57 of the 57th PMOS connects CK, drain electrode Pd57 and connects The source electrode Ps58 of the 58th PMOS, source electrode Ps57 connect VDD；The grid of the 58th PMOS Pole Pg58 connects the drain electrode Pd54 of the 54th PMOS, drain electrode Pd58 and connects the 57th NMOS The drain electrode Nd57 of pipe the outfan cn2, source electrode Ps58 as clock circuit connect Pd57；5th The grid Pg59 of 19 PMOS connects the grid Ng59 of the 59th NMOS tube and as clock circuit An outfan c1, drain electrode Pd59 connect the drain electrode Pd56 of the 56th PMOS, and connect output End cn1, source electrode Ps59 connect VDD；The grid Pg60 of the 60th PMOS connects the 60th NMOS The grid Ng60 of pipe the outfan c2, drain electrode Pd60 as clock circuit connect the 60th NMOS The drain electrode Nd60 and outfan cn2 of pipe, source electrode Ps60 connect VDD；The grid of the 61st PMOS Pg61 connects outfan cn1, drain electrode Pd61 and connects outfan c1, source electrode Ps61 and connect VDD；60th The grid Pg62 of two PMOS connects outfan cn2, drain electrode Pd62 and connects outfan c2, source electrode Ps62 Connect VDD；The grid Ng51 of the 51st NMOS tube connects CK, drain electrode Nd51 and connects the 51st The drain electrode Pd51 of PMOS；The grid Ng52 of the 52nd NMOS tube connects the 51st NMOS tube Drain electrode Nd51, drain electrode Nd52 connect the 52nd PMOS drain electrode Pd52, source electrode Ns52 connect VSS；The grid Ng53 of the 53rd NMOS tube connects the drain electrode Nd52 of the 52nd NMOS tube, leakage Pole Nd53 connects the drain electrode Pd53, source electrode Ns53 of the 53rd PMOS and connects VSS；54th The grid Ng54 of NMOS tube connects the drain electrode Nd53 of the 53rd NMOS tube, drain electrode Nd54 and connects the The drain electrode Pd54 of 54 PMOS, source electrode Ns54 connect VSS；The grid of the 55th NMOS tube Ng55 connects the drain electrode Nd54, source electrode Ns55 of the 54th NMOS tube and connects the 56th NMOS tube Drain electrode Nd56, drain electrode connect cn1；The grid Ng56 of the 56th NMOS tube connects CK, drain electrode Nd56 connects the source electrode Nd55, source electrode Ns56 of the 55th NMOS tube and connects VSS；57th NMOS The grid Ng57 of pipe connects the drain electrode Nd54, source electrode Ns57 of the 54th NMOS tube and connects the 58th The drain electrode Nd58 of NMOS tube, drain electrode connects cn2；The grid Ng58 of the 58th NMOS tube connects CK, Drain electrode Nd58 connects the source electrode Nd57, source electrode Ns58 of the 57th NMOS tube and connects VSS；50th The grid Ng59 of nine NMOS tube connects outfan c1, drain electrode Nd59 and connects outfan cn2, source electrode Ns59 Connect the drain electrode Nd63 of the 63rd NMOS tube；The grid Ng60 of the 60th NMOS tube connects output End c2, drain electrode Nd60 connect outfan cn2, source electrode Ns60 and connect the drain electrode of the 64th NMOS tube Nd64；The grid Ng61 of the 61st NMOS tube connects outfan cn1, drain electrode Nd61 and connects outfan C1, source electrode Ns61 connect VSS；The grid Ng62 of the 62nd NMOS tube connects outfan cn2, leakage Pole Nd62 connects outfan c2, source electrode Ns62 and connects VSS；The drain electrode Nd63 of the 63rd NMOS tube Connect the source electrode Ns59 of the 59th NMOS tube, grid Ng63 and connect outfan c1, source electrode Ns63 even Meet VSS；The drain electrode Nd64 of the 64th NMOS tube connects the source electrode Ns60 of the 60th NMOS tube, Grid Ng64 connects outfan c1, source electrode Ns64 and connects VSS.
As shown in Figure 4, buffer circuit has an input and an outfan, and input is D, outfan For D1.Buffer circuit is made up of eight PMOS and eight NMOS tube, all PMOS in buffer circuit The substrate of pipe connects power vd D, the Substrate ground VSS of all NMOS tube.The grid of the first PMOS Pole Pg1 connects input D and the grid Ng1 with the first NMOS tube connects, and drain electrode Pd1 connects a NMOS The drain electrode Ng1 of pipe, source electrode Ps1 connect VDD；The grid Pg2 of the second PMOS connects a PMOS The drain electrode Pd1 of pipe, drain electrode Pd2 connect the drain electrode Nd2, source electrode Ps2 of the second NMOS tube and connect VDD； The grid Pg3 of the 3rd PMOS connects the drain electrode Pd2 of the second PMOS, drain electrode Pd3 and connects the 3rd The drain electrode Nd3 of NMOS tube, source electrode Ps3 connect VDD；The grid Pg4 of the 4th PMOS connects the 3rd The drain electrode Pd3 of PMOS, drain electrode Pd4 connect the drain electrode Nd4, source electrode Ps4 of the 4th NMOS tube and connect VDD；The grid Pg5 of the 5th PMOS connects the drain electrode Pd4 of the 4th PMOS, drain electrode Pd5 and connects The drain electrode Nd5 of the 5th NMOS tube, source electrode Ps5 connect VDD；The grid Pg6 of the 6th PMOS is even Meet the drain electrode Pd5 of the 5th PMOS, drain electrode Pd6 and connect the drain electrode Nd6, source electrode Ps6 of the 6th NMOS tube Connect VDD；The grid Pg7 of the 7th PMOS connects the drain electrode Pd6 of the 6th PMOS, and drain Pd7 Connect the drain electrode Nd7 of the 7th NMOS tube, source electrode Ps7 and connect VDD；The grid Pg8 of the 8th PMOS Connect the drain electrode Pd7 of the 7th PMOS, drain electrode Pd8 and connect drain electrode Nd8 the conduct of the 8th NMOS tube The outfan D1 of buffer, source electrode Ps8 connect VDD；The grid Ng1 of the first NMOS tube connects Pg1, Drain electrode Nd1 connects Pd1, source electrode Ns1 and connects VSS;The grid Ng2 of the second NMOS tube connects a NMOS The drain electrode Nd1 of pipe, drain electrode Nd2 connect Pd2, source electrode Ns2 and connect VSS；The grid of the 3rd NMOS tube Ng3 connects the drain electrode Nd2 of the second NMOS tube, drain electrode Nd3 and connects Pd3, source electrode Ns3 and connect VSS； The grid Ng4 of the 4th NMOS tube connects the drain electrode Nd3 of the 3rd NMOS tube, drain electrode Nd4 and connects Pd4, Source electrode Ns4 connects VSS；The grid Ng5 of the 5th NMOS tube connects the drain electrode Nd4 of the 4th NMOS tube, Drain electrode Nd5 connects Pd5, source electrode Ns5 and connects VSS；The grid Ng6 of the 6th NMOS tube connects the 5th The drain electrode Nd5 of NMOS tube, drain electrode Nd6 connect Pd6, source electrode Ns6 and connect VSS；7th NMOS tube Grid Ng7 connect the 6th NMOS tube drain electrode Nd6, drain electrode Nd7 connect Pd7, source electrode Ns7 connect VSS；The grid Ng8 of the 8th NMOS tube connects the drain electrode Nd7 of the 7th NMOS tube, and drain electrode Nd8 is even Meet Pd8, source electrode Ns8 and connect VSS.
As it is shown in figure 5, scan control buffer circuit has an input and an outfan, input is SE, Outfan is SEN.Scan control buffer circuit is by the 39th PMOS and the 39th NMOS tube group Become.Substrate and the source electrode Ps39 of the 39th PMOS are all connected with power vd D, the 39th NMOS The substrate of pipe and source electrode Ns39 equal ground connection VSS.The grid Pg39 of the 39th PMOS connects SE, leakage Pole Pd39 connects the drain electrode Nd39 of the 39th NMOS tube, and as the outfan of scan control circuit SEN；The grid Ng39 of the 39th NMOS tube connects SE, drain electrode Nd39 and connects Pd39.
As shown in Figure 6, reset buffer circuit has an input and two outfans, and input is RN, defeated Going out end is R1, R2.Reset buffer circuit is made up of eight NMOS tube and eight PMOS, resets slow The substrate rushing all PMOS in circuit connects power vd D, the Substrate ground VSS of all NMOS tube. The grid Pg41 of the 41st PMOS connects RN, drain electrode Pd41 and connects the 41st NMOS tube Drain electrode Nd41, source electrode Ps41 connect power vd D；The grid Pg42 of the 42nd PMOS connects the The drain electrode Pd41 of 41 PMOS, drain electrode Pd42 connect the drain electrode Nd42 of the 42nd NMOS tube, Source electrode Ps42 connects power vd D；The grid Pg43 of the 43rd PMOS connects the 42nd PMOS The drain electrode Pd42 of pipe, drain electrode Pd43 connect the drain electrode Nd43, source electrode Ps43 of the 43rd NMOS tube even Meet power vd D；The grid Pg44 of the 44th PMOS connects the drain electrode of the 43rd PMOS Pd43, drain electrode Pd44 connect the drain electrode Nd44, source electrode Ps44 of the 44th NMOS tube and connect power vd D； The grid Pg45 of the 45th PMOS connects RN, drain electrode Pd45 and connects the 46th PMOS Source electrode Ps46, source electrode Ps45 connect VDD；The grid Pg46 of the 46th PMOS connects the 44th The drain electrode Pd44 of PMOS, drain electrode Pd46 connect the drain electrode Nd45 of the 45th NMOS tube, and conduct One outfan R1, source electrode Ps46 of reset buffer circuit connect Pd45；The grid of the 47th PMOS Pole Pg47 connects RN, drain electrode Pd47 and connects the source electrode Ps48, source electrode Ps47 of the 48th PMOS even Meet VDD；The grid Pg48 of the 48th PMOS connects the drain electrode Pd44 of the 44th PMOS, Drain electrode Pd48 connects the drain electrode Nd47 of the 47th NMOS tube, and as reset buffer circuit is defeated Going out and hold R2, source electrode Ps48 connects Pd47；The grid Ng41 of the 41st NMOS tube connects RN, leakage Pole Nd41 connects the drain electrode Pd41, source electrode Ns41 of the 41st PMOS and connects VSS；42nd The grid Ng42 of NMOS tube connects the drain electrode Nd41 of the 41st NMOS tube, drain electrode Nd42 and connects the The drain electrode Pd42 of 42 PMOS, source electrode Ns42 connect VSS；The grid of the 43rd NMOS tube Ng43 connects the drain electrode Nd42 of the 42nd NMOS tube, drain electrode Nd43 and connects the 43rd PMOS Drain electrode Pd43, source electrode Ns43 connect VSS；The grid Ng44 of the 44th NMOS tube connects the 4th The drain electrode Nd43 of 13 NMOS tube, drain electrode Nd44 connect the drain electrode Pd44 of the 44th PMOS, Source electrode Ns44 connects VSS；The grid Ng45 of the 45th NMOS tube connects the 44th NMOS tube Drain electrode Nd44, source electrode Ns45 connect the 46th NMOS tube drain electrode Nd46, drain electrode Nd45 connect R1；The grid Ng46 of the 46th NMOS tube connects RN, drain electrode Nd46 and connects the 45th NMOS The source electrode Nd45 of pipe, source electrode Ns46 connect VSS；The grid Ng47 of the 47th NMOS tube connects the The drain electrode Nd44 of 44 NMOS tube, source electrode Ns47 connect the drain electrode Nd48 of the 48th NMOS tube, Drain electrode Nd47 connects R2；The grid Ng48 of the 48th NMOS tube connects RN, drain electrode Nd48 and connects The source electrode Nd47 of the 47th NMOS tube, source electrode Ns48 connect VSS.
As it is shown in fig. 7, main latch has 11 inputs and two outfans, input is D, D1, SI, SE, SEN, R1, R2, c1, c2, cn1, cn2；Outfan is m1, m1r.Main latch is by 18 Individual PMOS and 18 NMOS tube compositions, in main latch, the substrate of all PMOS connects power supply VDD, the Substrate ground VSS of all NMOS tube.The grid Pg9 of the 9th PMOS connects SI, leakage Pole Pd9 connects the source electrode Ps10, source electrode Ps9 of the tenth PMOS and connects power vd D；Tenth PMOS The grid Pg10 of pipe connects SEN, drain electrode Pd10 and connects the source electrode Ps13 of the 13rd PMOS, source electrode Ps10 connects Pd9；The grid Pg11 of the 11st PMOS connects SE, drain electrode Pd11 and connects the 12nd The source electrode Ps12 of PMOS, source electrode Ps11 connect power vd D；The grid Pg12 of the 12nd PMOS Connect D, drain electrode Pd12 to connect Ps13, source electrode Ps12 and connect Pd11；The grid of the 13rd PMOS Pg13 connects c1, drain electrode Pd13 and connects the drain electrode Nd9, source electrode Ps13 of the 9th NMOS tube and connect Pd10； The grid Pg14 of the 14th PMOS connects SI, drain electrode Pd14 and connects the source electrode of the 15th PMOS Ps15, source electrode Ps14 connect power vd D；The grid Pg15 of the 15th PMOS connects SEN, drain electrode Pd15 connects the source electrode Ps18, source electrode Ps15 of the 18th PMOS and connects Pd14；16th PMOS Grid Pg16 connect SE, drain electrode Pd16 connect the 17th PMOS source electrode Ps17, source electrode Ps16 Connect power vd D；The grid Pg17 of the 17th PMOS connects D1, drain electrode Pd17 and connects the 18th The source electrode Ps18 of PMOS, source electrode Ps17 connect Pd16；The grid Pg18 of the 18th PMOS connects C2, drain electrode Pd18 connect the drain electrode Nd14, source electrode Ps18 of the 14th NMOS tube and connect Pd15；Tenth The grid Pg19 of nine PMOS connects R1, drain electrode Pd19 and connects the source electrode Ps20 of the 20th PMOS, Source electrode Ps19 connects power vd D；The grid Pg20 of the 20th PMOS connects Pd13, and drain Pd20 Connect the drain electrode Nd20 of the 20th NMOS tube, and as an outfan m1r of main latch, source electrode Ps20 connects the drain electrode Pd19 of the 19th PMOS；The grid Pg21 of the 21st PMOS connects R2, drain electrode Pd21 connect the source electrode Ps22, source electrode Ps21 of the 22nd PMOS and connect power vd D； The grid Pg22 of the 22nd PMOS connects Pd18, drain electrode Pd22 and connects the 22nd NMOS tube Drain electrode Nd20, and as main latch an outfan m1, source electrode Ps22 connect the 21st PMOS The drain electrode Pd21 of pipe；The grid Pg23 of the 23rd PMOS connects Pd22, drain electrode Pd23 and connects the The source electrode Ps24 of 24 PMOS, source electrode Ps23 connect power vd D；24th PMOS Grid Pg24 connects cn1, drain electrode Pd24 and connects the drain electrode Nd23, source electrode Ps24 of the 23rd NMOS tube Connect Pd23；The grid Pg25 of the 25th PMOS connects Pd20, drain electrode Pd25 and connects the 20th The source electrode Ps26 of six PMOS, source electrode Ps25 connect power vd D；The grid of the 26th PMOS Pg26 connects cn2, drain electrode Pd26 and connects drain electrode Nd25 and Pd18 of the 25th NMOS tube, source electrode Ps26 connects Pd25；The grid Ng9 of the 9th NMOS tube connects cn1, drain electrode Nd9 and connects Pd13, source Pole Ns9 connects the drain electrode Nd10 of the tenth NMOS tube；The grid Ng10 of the tenth NMOS tube connects SE, Drain electrode Nd10 connects Ns9, source electrode Ns10 and connects the drain electrode Nd11 of the 11st NMOS tube；11st NMOS The grid Ng11 of pipe connects SI, drain electrode Nd11 and connects Ns10, source electrode Ns11 ground connection VSS；12nd The grid Ng12 of NMOS tube connects D, drain electrode Nd12 and connects Ns9, source electrode Ns12 and connect the 13rd NMOS The drain electrode Nd13 of pipe；The grid Ng13 of the 13rd NMOS tube connects SEN, drain electrode Nd13 and connects Ns12, Source electrode Ns13 ground connection VSS；The grid Ng14 of the 14th NMOS tube connects cn2, drain electrode Nd14 and connects Pd18, source electrode Ns14 connect the drain electrode Nd15 of the 15th NMOS tube；The grid of the 15th NMOS tube Ng15 connects SE, drain electrode Nd15 and connects Ns14, source electrode Ns15 and connect the drain electrode of the 16th NMOS tube Nd16；The grid Ng16 of the 16th NMOS tube connects SI, drain electrode Nd16 and connects Ns15, source electrode Ns16 Ground connection VSS；The grid Ng17 of the 17th NMOS tube connects D1, drain electrode Nd17 and connects Ns14, source electrode Ns17 connects the drain electrode Nd18 of the 18th NMOS tube；The grid Ng18 of the 18th NMOS tube connects SEN, Drain electrode Nd18 connects Ns17, source electrode Ns18 ground connection VSS；The grid Ng19 of the 19th NMOS tube connects Pd18, drain electrode Nd19 connect Pd20, source electrode Ns19 ground connection VSS；The grid Ng20 of the 20th NMOS tube Connect R2, drain electrode Nd20 and connect Pd20, source electrode Ns20 ground connection VSS；The grid of the 21st NMOS tube Pole Ng21 connects Pd13, drain electrode Nd21 and connects Pd22, source electrode Ns21 ground connection VSS；22nd NMOS The grid Ng22 of pipe connects R1, drain electrode Nd22 and connects Pd22, source electrode Ns22 ground connection VSS；23rd The grid Ng23 of NMOS tube connects c1, drain electrode Nd23 and connects Pd24, source electrode Ns23 and connect the 24th The drain electrode Nd24 of NMOS tube；The grid Ng24 of the 24th NMOS tube connects Pd20, and drain Nd24 Connect Ns23, source electrode Ns24 ground connection VSS；The grid Ng25 of the 25th NMOS tube connects c2, leakage Pole Nd25 connects Pd26, source electrode Ns25 and connects the drain electrode Nd26 of the 26th NMOS tube；26th The grid Ng26 of NMOS tube connects Pd22, drain electrode Nd26 and connects Ns25, source electrode Ns26 ground connection VSS. 9th PMOS, the tenth PMOS, the 11st PMOS and the tenth NMOS tube, the 11st Scan Architecture in NMOS tube, the 13rd NMOS tube composition main latch；19th PMOS and Resetting structure in 20th NMOS tube composition main latch.
As shown in Figure 8, having eight inputs and two outfans from latch, input is R1, R2, c1, C2, cn1, cn2, m1, m1r；Outfan is s1, s1r.From latch by 12 PMOS and ten Two NMOS tube compositions, from latch, the substrate of all PMOS connects power vd D, all The Substrate ground VSS of NMOS tube.The grid Pg27 of the 27th PMOS connects m1r, and drain Pd27 Connect the source electrode Ps28 of the 28th PMOS, source electrode Ps27 and connect power vd D；28th PMOS The grid Pg28 of pipe connects cn1, drain electrode Pd28 and connects the drain electrode Nd27 of the 27th NMOS tube, source electrode Ps28 connects Pd27；The grid Pg29 of the 29th PMOS connects m1, drain electrode Pd29 and connects the 3rd The source electrode Ps30 of ten PMOS, source electrode Ps29 connect power vd D；The grid Pg30 of the 30th PMOS Connect cn2, drain electrode Pd30 to connect the drain electrode Nd29, source electrode Ps30 of the 29th NMOS tube and connect Pd29； The grid Pg31 of the 31st PMOS connects R1, drain electrode Pd31 and connects the 32nd PMOS Source electrode Ps32, source electrode Ps31 connect power vd D；The grid Pg32 of the 32nd PMOS connects Pd28, Drain electrode Pd32 connects the drain electrode Nd32 of the 32nd NMOS tube, and as from latch outfan S1r, source electrode Ps32 connect the drain electrode Pd31 of the 31st PMOS；The grid of the 33rd PMOS Pg33 connects R2, drain electrode Pd33 and connects the source electrode Ps34, source electrode Ps33 of the 34th PMOS and connect Power vd D；The grid Pg34 of the 34th PMOS connects Pd30, drain electrode Pd34 and connects the 30th The drain electrode Nd34 of four NMOS tube, and connect the as from latch outfan s1, source electrode Ps34 The drain electrode Pd33 of 33 PMOS；The grid Pg35 of the 35th PMOS connects Pd34, drain electrode Pd35 connects the source electrode Ps36, source electrode Ps35 of the 36th PMOS and connects power vd D；36th The grid Pg36 of PMOS connects cn1, drain electrode Pd36 and connects the drain electrode Nd35 of the 35th NMOS tube With Pd28, source electrode Ps36 connect Pd35；The grid Pg37 of the 37th PMOS connects Pd32, leakage Pole Pd37 connects the source electrode Ps38, source electrode Ps37 of the 38th PMOS and connects power vd D；30th The grid Pg38 of eight PMOS connects cn2, drain electrode Pd38 and connects the drain electrode Nd37 of the 37th NMOS tube With Pd30, source electrode Ps38 connect Pd37；The grid Ng27 of the 27th NMOS tube connects c, drain electrode Nd27 connects Pd28, source electrode Ns27 and connects the drain electrode Nd28 of the 28th NMOS tube；28th NMOS The grid Ng28 of pipe connects m1, drain electrode Nd28 and connects Ns27, source electrode Ns28 ground connection VSS；20th The grid Ng29 of nine NMOS tube connects c2, drain electrode Nd29 and connects Pd30, source electrode Ns29 and connect the 3rd The drain electrode Nd30 of ten NMOS tube；The grid Ng30 of the 30th NMOS tube connects m1r, and drain Nd30 Connect Ns29, source electrode Ns30 ground connection VSS；The grid Ng31 of the 31st NMOS tube connects Pd30, Drain electrode Nd31 connects Pd32, source electrode Ns31 ground connection VSS；The grid Ng32 of the 32nd NMOS tube Connect R2, drain electrode Nd32 and connect Pd32, source electrode Ns32 ground connection VSS；The grid of the 33rd NMOS tube Pole Ng33 connects Pd28, drain electrode Nd33 and connects Pd34, source electrode Ns33 ground connection VSS；34th NMOS The grid Ng34 of pipe connects R1, drain electrode Nd34 and connects Pd34, source electrode Ns34 ground connection VSS；35th The grid Ng35 of NMOS tube connects c1, drain electrode Nd35 and connects Pd36, source electrode Ns35 and connect the 36th The drain electrode Nd36 of NMOS tube；The grid Ng36 of the 36th NMOS tube connects Pd32, and drain Nd36 Connect Ns35, source electrode Ns36 ground connection VSS；The grid Ng37 of the 37th NMOS tube connects c2, leakage Pole Nd37 connects Pd38, source electrode Ns37 and connects the drain electrode Nd38 of the 38th NMOS tube；38th The grid Ng38 of NMOS tube connects Pd34, drain electrode Nd38 and connects Ns37, source electrode Ns38 ground connection VSS； 31st PMOS and the 32nd NMOS tube composition resetting structure from latch.
As it is shown in figure 9, output buffer has two inputs and an outfan, input connect s1 and S1r, outfan is Q.Output buffer is made up of two PMOS and two NMOS tube.Output is slow The substrate rushing all PMOS of circuit connects power vd D, the Substrate ground VSS of all NMOS tube. The grid Pg49 of the 49th PMOS meets input s1r, drain electrode Pd49 and connects the 49th NMOS The drain electrode Nd49 of pipe, source electrode Ps49 meet power vd D；The grid Pg50 of the 50th PMOS meets Pd49, Drain electrode Pd50 connects the drain electrode Nd50 of the 50th NMOS tube, and as the output Q of output buffer； Source electrode Ps50 meets power vd D；The grid Ng49 of the 49th NMOS tube meets input s1, and drain Nd49 Connect Pd49, source electrode Ns49 ground connection VSS；The grid Ng50 of the 50th NMOS tube meets Nd49, drain electrode Nd50 connects Pd50, source electrode Ns50 ground connection VSS.
Beijing Institute of Atomic Energy's H-13 tandem accelerator can produce LET value and be respectively 2.88MeV·cm2/mg、8.62MeV·cm2/mg、12.6MeV·cm2/ mg and 17.0MeV cm2/mg Four kinds of ground heavy ion irradiation test environments.Unguyed for the tradition being in normal operating conditions is resetted Scan Architecture d type flip flop, tradition duplication redundancy reinforce reducible Scan Architecture d type flip flop, the time Reducible Scan Architecture d type flip flop of sampling reinforcing, the Chinese patent of Application No. 201110323908.2 Propose primary particle inversion resistant reset Scan Architecture d type flip flop and anti-single particle of the present invention upset and simple grain Reducible Scan Architecture d type flip flop of sub-transient state connects the outfan of identical 1000 grade reverser chain respectively And work with the clock frequency of 40MHz, the input of 1000 grades of reverser chains connects low level.By above-mentioned electricity Road is placed in the LET value of Beijing Institute of Atomic Energy's H-13 tandem accelerator generation and is respectively 2.88MeV·cm2/mg、8.62MeV·cm2/mg、12.6MeV·cm2/ mg and 21.3MeV cm2/mg Ground heavy ion irradiation test environment in, each during adding up the heavy ion irradiation of each LET reducible sweep Retouch structure d type flip flop make a mistake output number of times.The total fluence of heavy ion irradiation of every kind of LET is 107ion/cm2.Table 1 is the ground heavy particle using Beijing Institute of Atomic Energy's H-13 tandem accelerator to carry out Irradiation tests the unguyed reducible Scan Architecture d type flip flop of the tradition obtained, tradition duplication redundancy is reinforced Reducible Scan Architecture d type flip flop, time sampling reinforce reducible Scan Architecture d type flip flop, The primary particle inversion resistant Scan Architecture D that resets that the Chinese patent of Application No. 201110323908.2 proposes Reducible Scan Architecture d type flip flop of trigger and anti-single particle of the present invention upset and single-ion transient state exists LET value is respectively 2.88MeV cm2/mg、8.62MeV·cm2/mg、12.6MeV·cm2/ mg and 21.3MeV·cm2Make a mistake during the ground heavy ion irradiation of/mg the number of times exported.Every kind of LET The total fluence of heavy ion irradiation be 107ion/cm2.From the statistics of table 1 it can be seen that the anti-single particle of the present invention Upset and single-ion transient state ability are better than the unguyed reducible Scan Architecture d type flip flop of tradition, the time adopts Reducible Scan Architecture d type flip flop, the Chinese patent of Application No. 201110323908.2 that sample is reinforced carry The primary particle inversion resistant Scan Architecture d type flip flop that resets gone out is reducible with what tradition duplication redundancy was reinforced Scan Architecture d type flip flop, is suitable for anti-single particle upset and the standard of single-ion transient state reinforcing integrated circuit Cell library, is applied to the fields such as Aeronautics and Astronautics.
Table 1

Claims (1)

1. anti-single particle upset and reducible Scan Architecture d type flip flop of single-ion transient state, including time Clock circuit, scan control buffer circuit, reset buffer circuit, main latch, slow from latch, output Rush circuit, it is characterised in that reducible Scan Architecture D of anti-single particle upset and single-ion transient state triggers Device also includes buffer circuit；Main latch and from latch be redundancy reinforce latch；Main latch With from latch tandem, and all it is connected with clock circuit, reset buffer circuit；Main latch also with Buffer circuit, scan control buffer circuit are connected, and are also connected with output buffer from latch；Have five Individual input and an outfan；Five inputs are clock signal input terminal CK, data signal respectively Input D, scan control signal input SE, scan data input SI and reset signal input RN；Outfan is Q；
Described clock circuit has an input and four outfans, and input is CK, outfan be c1, c2、cn1、cn2；Clock circuit is made up of 12 PMOS and 14 NMOS, institute in circuit The substrate having PMOS connects power vd D, the Substrate ground VSS of all NMOS tube；50th The grid Pg51 of one PMOS connects CK, drain electrode Pd51 and connects the leakage of the 51st NMOS tube Pole Nd51；The grid Pg52 of the 52nd PMOS connects the drain electrode Pd51 of the 51st PMOS, Drain electrode Pd52 connects the drain electrode Nd52, source electrode Ps52 of the 52nd NMOS tube and connects power vd D； The grid Pg53 of the 53rd PMOS connects the drain electrode Pd52 of the 52nd PMOS, drain electrode Pd53 connects the drain electrode Nd53, source electrode Ps53 of the 53rd NMOS tube and connects power vd D；5th The grid Pg54 of 14 PMOS connects the drain electrode Pd53 of the 53rd PMOS, and drain Pd54 Connect the drain electrode Nd54 of the 54th NMOS tube, source electrode Ps54 and connect power vd D；55th The grid Pg55 of PMOS connects CK, drain electrode Pd55 and connects the source electrode of the 56th PMOS Ps56, source electrode Ps55 connect VDD；The grid Pg56 of the 56th PMOS connects the 54th The drain electrode Pd54 of PMOS, drain electrode Pd56 connect the drain electrode Nd55 of the 55th NMOS tube, and An outfan cn1, source electrode Ps56 as clock circuit connect Pd55；57th PMOS Grid Pg57 connect CK, drain electrode Pd57 connect the 58th PMOS source electrode Ps58, source electrode Ps57 connects VDD；The grid Pg58 of the 58th PMOS connects the 54th PMOS Drain electrode Pd54, drain electrode Pd58 connect the drain electrode Nd57 of the 57th NMOS tube and as clock circuit An outfan cn2, source electrode Ps58 connect Pd57；The grid Pg59 of the 59th PMOS Connect the grid Ng59 of the 59th NMOS tube and as an outfan c1 of clock circuit, leakage Pole Pd59 connects the drain electrode Pd56 of the 56th PMOS, and connects outfan cn1, source electrode Ps59 Connect VDD；The grid Pg60 of the 60th PMOS connects the grid Ng60 of the 60th NMOS tube And connect the drain electrode of the 60th NMOS tube as an outfan c2 of clock circuit, drain electrode Pd60 Nd60 and outfan cn2, source electrode Ps60 connect VDD；The grid Pg61 of the 61st PMOS Connect outfan cn1, drain electrode Pd61 to connect outfan c1, source electrode Ps61 and connect VDD；60th The grid Pg62 of two PMOS connects outfan cn2, drain electrode Pd62 and connects outfan c2, source electrode Ps62 connects VDD；The grid Ng51 of the 51st NMOS tube connects CK, drain electrode Nd51 and connects The drain electrode Pd51 of the 51st PMOS；The grid Ng52 of the 52nd NMOS tube connects the 5th The drain electrode Nd51 of 11 NMOS tube, drain electrode Nd52 connect the drain electrode Pd52 of the 52nd PMOS, Source electrode Ns52 connects VSS；The grid Ng53 of the 53rd NMOS tube connects the 52nd NMOS The drain electrode Nd52 of pipe, drain electrode Nd53 connect the drain electrode Pd53, source electrode Ns53 of the 53rd PMOS Connect VSS；The grid Ng54 of the 54th NMOS tube connects the drain electrode of the 53rd NMOS tube Nd53, drain electrode Nd54 connect the drain electrode Pd54, source electrode Ns54 of the 54th PMOS and connect VSS； The grid Ng55 of the 55th NMOS tube connects the drain electrode Nd54 of the 54th NMOS tube, source electrode Ns55 connects the drain electrode Nd56 of the 56th NMOS tube, and drain electrode connects cn1；56th NMOS The grid Ng56 of pipe connects CK, drain electrode Nd56 and connects the source electrode Nd55 of the 55th NMOS tube, Source electrode Ns56 connects VSS；The grid Ng57 of the 57th NMOS tube connects the 54th NMOS The drain electrode Nd54 of pipe, source electrode Ns57 connect the drain electrode Nd58 of the 58th NMOS tube, and drain electrode connects cn2；The grid Ng58 of the 58th NMOS tube connects CK, drain electrode Nd58 and connects the 57th The source electrode Nd57 of NMOS tube, source electrode Ns58 connect VSS；The grid Ng59 of the 59th NMOS tube Connect outfan c1, drain electrode Nd59 to connect outfan cn2, source electrode Ns59 and connect the 63rd NMOS The drain electrode Nd63 of pipe；The grid Ng60 of the 60th NMOS tube connects outfan c2, and drain Nd60 Connect outfan cn2, source electrode Ns60 and connect the drain electrode Nd64 of the 64th NMOS tube；61st The grid Ng61 of NMOS tube connects outfan cn1, drain electrode Nd61 and connects outfan c1, source electrode Ns61 Connect VSS；The grid Ng62 of the 62nd NMOS tube connects outfan cn2, and drain electrode Nd62 is even Meet outfan c2, source electrode Ns62 and connect VSS；The drain electrode Nd63 of the 63rd NMOS tube connects the The source electrode Ns59 of 59 NMOS tube, grid Ng63 connect outfan c1, source electrode Ns63 and connect VSS；The drain electrode Nd64 of the 64th NMOS tube connects the source electrode Ns60 of the 60th NMOS tube, Grid Ng64 connects outfan c1, source electrode Ns64 and connects VSS；
Described buffer circuit has an input and an outfan, and input is D, and outfan is D1； Buffer circuit is made up of eight PMOS and eight NMOS tube, all PMOS in buffer circuit Substrate connect power vd D, the Substrate ground VSS of all NMOS tube；The grid of the first PMOS Pole Pg1 connects input D and the grid Ng1 with the first NMOS tube connects, and drain electrode Pd1 connects first The drain electrode Ng1 of NMOS tube, source electrode Ps1 connect VDD；The grid Pg2 of the second PMOS connects The drain electrode Pd1 of the first PMOS, drain electrode Pd2 connect the drain electrode Nd2 of the second NMOS tube, source electrode Ps2 connects VDD；The grid Pg3 of the 3rd PMOS connects the drain electrode Pd2 of the second PMOS, Drain electrode Pd3 connects the drain electrode Nd3, source electrode Ps3 of the 3rd NMOS tube and connects VDD；4th PMOS The grid Pg4 of pipe connects the drain electrode Pd3 of the 3rd PMOS, drain electrode Pd4 and connects the 4th NMOS tube Drain electrode Nd4, source electrode Ps4 connect VDD；The grid Pg5 of the 5th PMOS connects the 4th PMOS The drain electrode Pd4 of pipe, drain electrode Pd5 connect the drain electrode Nd5, source electrode Ps5 of the 5th NMOS tube and connect VDD； The grid Pg6 of the 6th PMOS connects the drain electrode Pd5 of the 5th PMOS, drain electrode Pd6 and connects the The drain electrode Nd6 of six NMOS tube, source electrode Ps6 connect VDD；The grid Pg7 of the 7th PMOS is even Meet the drain electrode Pd6 of the 6th PMOS, drain electrode Pd7 and connect the drain electrode Nd7 of the 7th NMOS tube, source Pole Ps7 connects VDD；The grid Pg8 of the 8th PMOS connects the drain electrode Pd7 of the 7th PMOS, Drain electrode Pd8 connects the drain electrode Nd8 of the 8th NMOS tube and as the outfan D1 of buffer, source electrode Ps8 connects VDD；The grid Ng1 of the first NMOS tube connects Pg1, drain electrode Nd1 and connects Pd1, Source electrode Ns1 connects VSS；The grid Ng2 of the second NMOS tube connects the drain electrode Nd1 of the first NMOS tube, Drain electrode Nd2 connects Pd2, source electrode Ns2 and connects VSS；The grid Ng3 of the 3rd NMOS tube connects the The drain electrode Nd2 of two NMOS tube, drain electrode Nd3 connect Pd3, source electrode Ns3 and connect VSS；4th NMOS The grid Ng4 of pipe connects the drain electrode Nd3 of the 3rd NMOS tube, drain electrode Nd4 and connects Pd4, source electrode Ns4 Connect VSS；The grid Ng5 of the 5th NMOS tube connects the drain electrode Nd4 of the 4th NMOS tube, drain electrode Nd5 connects Pd5, source electrode Ns5 and connects VSS；The grid Ng6 of the 6th NMOS tube connects the 5th NMOS The drain electrode Nd5 of pipe, drain electrode Nd6 connect Pd6, source electrode Ns6 and connect VSS；7th NMOS tube Grid Ng7 connects the drain electrode Nd6 of the 6th NMOS tube, drain electrode Nd7 and connects Pd7, source electrode Ns7 even Meet VSS；The grid Ng8 of the 8th NMOS tube connects the drain electrode Nd7 of the 7th NMOS tube, drain electrode Nd8 connects Pd8, source electrode Ns8 and connects VSS；
Described scan control buffer circuit has an input and an outfan, and input is SE, defeated Going out end is SEN；Scan control buffer circuit is by the 39th PMOS and the 39th NMOS tube Composition；Substrate and the source electrode Ps39 of the 39th PMOS are all connected with power vd D, and the 39th The substrate of NMOS tube and source electrode Ns39 equal ground connection VSS；The grid Pg39 of the 39th PMOS Connect SE, drain electrode Pd39 and connect the drain electrode Nd39 of the 39th NMOS tube, and as scan control The outfan SEN of circuit；The grid Ng39 of the 39th NMOS tube connects SE, and drain Nd39 Connect Pd39；
Described reset buffer circuit has an input and two outfans, and input is RN, outfan It is R1, R2；Reset buffer circuit is made up of eight NMOS tube and eight PMOS, and reset buffering In circuit, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube； The grid Pg41 of the 41st PMOS connects RN, drain electrode Pd41 and connects the 41st NMOS The drain electrode Nd41 of pipe, source electrode Ps41 connect power vd D；The grid Pg42 of the 42nd PMOS Connect the drain electrode Pd41 of the 41st PMOS, drain electrode Pd42 and connect the 42nd NMOS tube Drain electrode Nd42, source electrode Ps42 connect power vd D；The grid Pg43 of the 43rd PMOS connects The drain electrode Pd42 of the 42nd PMOS, drain electrode Pd43 connect the drain electrode of the 43rd NMOS tube Nd43, source electrode Ps43 connect power vd D；The grid Pg44 of the 44th PMOS connects the 4th The drain electrode Pd43 of 13 PMOS, drain electrode Pd44 connect the drain electrode Nd44 of the 44th NMOS tube, Source electrode Ps44 connects power vd D；The grid Pg45 of the 45th PMOS connects RN, drain electrode Pd45 connects the source electrode Ps46, source electrode Ps45 of the 46th PMOS and connects VDD；46th The grid Pg46 of PMOS connects the drain electrode Pd44 of the 44th PMOS, drain electrode Pd46 and connects The drain electrode Nd45 of the 45th NMOS tube, and as an outfan R1 of reset buffer circuit, source Pole Ps46 connects Pd45；The grid Pg47 of the 47th PMOS connects RN, and drain electrode Pd47 is even Meet the source electrode Ps48 of the 48th PMOS, source electrode Ps47 and connect VDD；48th PMOS The grid Pg48 of pipe connects the drain electrode Pd44 of the 44th PMOS, drain electrode Pd48 and connects the 40th The drain electrode Nd47 of seven NMOS tube, and as an outfan R2, source electrode Ps48 of reset buffer circuit Connect Pd47；The grid Ng41 of the 41st NMOS tube connects RN, drain electrode Nd41 and connects the 4th The drain electrode Pd41 of 11 PMOS, source electrode Ns41 connect VSS；The grid of the 42nd NMOS tube Pole Ng42 connects the drain electrode Nd41 of the 41st NMOS tube, drain electrode Nd42 and connects the 42nd PMOS The drain electrode Pd42 of pipe, source electrode Ns42 connect VSS；The grid Ng43 of the 43rd NMOS tube connects The drain electrode Nd42 of the 42nd NMOS tube, drain electrode Nd43 connect the drain electrode of the 43rd PMOS Pd43, source electrode Ns43 connect VSS；The grid Ng44 of the 44th NMOS tube connects the 43rd The drain electrode Nd43 of NMOS tube, drain electrode Nd44 connect the drain electrode Pd44 of the 44th PMOS, source Pole Ns44 connects VSS；The grid Ng45 of the 45th NMOS tube connects the 44th NMOS tube Drain electrode Nd44, source electrode Ns45 connect the 46th NMOS tube drain electrode Nd46, drain Nd45 Connect R1；The grid Ng46 of the 46th NMOS tube connects RN, drain electrode Nd46 and connects the 40th The source electrode Nd45 of five NMOS tube, source electrode Ns46 connect VSS；The grid of the 47th NMOS tube Ng47 connects the drain electrode Nd44, source electrode Ns47 of the 44th NMOS tube and connects the 48th NMOS The drain electrode Nd48 of pipe, drain electrode Nd47 connect R2；The grid Ng48 of the 48th NMOS tube connects RN, drain electrode Nd48 connect the source electrode Nd47, source electrode Ns48 of the 47th NMOS tube and connect VSS；
Described main latch has 11 inputs and two outfans, and input is D, D1, SI, SE, SEN, R1, R2, c1, c2, cn1, cn2；Outfan is m1, m1r；Main latch is by 18 PMOS and 18 NMOS tube compositions, in main latch, the substrate of all PMOS connects electricity Source VDD, the Substrate ground VSS of all NMOS tube；The grid Pg9 of the 9th PMOS connects SI, drain electrode Pd9 connect the source electrode Ps10, source electrode Ps9 of the tenth PMOS and connect power vd D；The The grid Pg10 of ten PMOS connects SEN, drain electrode Pd10 and connects the source electrode of the 13rd PMOS Ps13, source electrode Ps10 connect Pd9；The grid Pg11 of the 11st PMOS connects SE, and drain Pd11 Connect the source electrode Ps12 of the 12nd PMOS, source electrode Ps11 and connect power vd D；12nd PMOS The grid Pg12 of pipe connects D, drain electrode Pd12 and connects Ps13, source electrode Ps12 and connect Pd11；13rd The grid Pg13 of PMOS connects c1, drain electrode Pd13 and connects the drain electrode Nd9 of the 9th NMOS tube, Source electrode Ps13 connects Pd10；The grid Pg14 of the 14th PMOS connects SI, drain electrode Pd14 and connects The source electrode Ps15 of the 15th PMOS, source electrode Ps14 connect power vd D；15th PMOS Grid Pg15 connect SEN, drain electrode Pd15 connect the 18th PMOS source electrode Ps18, source electrode Ps15 connects Pd14；The grid Pg16 of the 16th PMOS connects SE, drain electrode Pd16 and connects the tenth The source electrode Ps17 of seven PMOS, source electrode Ps16 connect power vd D；The grid of the 17th PMOS Pole Pg17 connects D1, drain electrode Pd17 and connects the source electrode Ps18, source electrode Ps17 of the 18th PMOS Connect Pd16；The grid Pg18 of the 18th PMOS connects c2, drain electrode Pd18 and connects the 14th The drain electrode Nd14 of NMOS tube, source electrode Ps18 connect Pd15；The grid Pg19 of the 19th PMOS Connect R1, drain electrode Pd19 to connect the source electrode Ps20, source electrode Ps19 of the 20th PMOS and connect power supply VDD；The grid Pg20 of the 20th PMOS connects Pd13, drain electrode Pd20 and connects the 20th NMOS The drain electrode Nd20 of pipe, and as an outfan m1r, the source electrode Ps20 connection the 19th of main latch The drain electrode Pd19 of PMOS；The grid Pg21 of the 21st PMOS connects R2, and drain Pd21 Connect the source electrode Ps22 of the 22nd PMOS, source electrode Ps21 and connect power vd D；22nd The grid Pg22 of PMOS connects Pd18, drain electrode Pd22 and connects the drain electrode of the 22nd NMOS tube Nd20, and as an outfan m1, source electrode Ps22 connection the 21st PMOS of main latch The drain electrode Pd21 of pipe；The grid Pg23 of the 23rd PMOS connects Pd22, drain electrode Pd23 and connects The source electrode Ps24 of the 24th PMOS, source electrode Ps23 connect power vd D；24th PMOS The grid Pg24 of pipe connects cn1, drain electrode Pd24 and connects the drain electrode Nd23 of the 23rd NMOS tube, Source electrode Ps24 connects Pd23；The grid Pg25 of the 25th PMOS connects Pd20, and drain Pd25 Connect the source electrode Ps26 of the 26th PMOS, source electrode Ps25 and connect power vd D；26th The grid Pg26 of PMOS connects cn2, drain electrode Pd26 and connects the drain electrode of the 25th NMOS tube Nd25 and Pd18, source electrode Ps26 connect Pd25；The grid Ng9 of the 9th NMOS tube connects cn1, Drain electrode Nd9 connects Pd13, source electrode Ns9 and connects the drain electrode Nd10 of the tenth NMOS tube；Tenth NMOS The grid Ng10 of pipe connects SE, drain electrode Nd10 and connects Ns9, source electrode Ns10 and connect the 11st NMOS The drain electrode Nd11 of pipe；The grid Ng11 of the 11st NMOS tube connects SI, drain electrode Nd11 and connects Ns10, Source electrode Ns11 ground connection VSS；The grid Ng12 of the 12nd NMOS tube connects D, and drain electrode Nd12 is even Meet Ns9, source electrode Ns12 and connect the drain electrode Nd13 of the 13rd NMOS tube；13rd NMOS tube Grid Ng13 connects SEN, drain electrode Nd13 and connects Ns12, source electrode Ns13 ground connection VSS；14th The grid Ng14 of NMOS tube connects cn2, drain electrode Nd14 and connects Pd18, source electrode Ns14 and connect the tenth The drain electrode Nd15 of five NMOS tube；The grid Ng15 of the 15th NMOS tube connects SE, and drain Nd15 Connect Ns14, source electrode Ns15 and connect the drain electrode Nd16 of the 16th NMOS tube；16th NMOS The grid Ng16 of pipe connects SI, drain electrode Nd16 and connects Ns15, source electrode Ns16 ground connection VSS；Tenth The grid Ng17 of seven NMOS tube connects D1, drain electrode Nd17 and connects Ns14, source electrode Ns17 and connect the The drain electrode Nd18 of 18 NMOS tube；The grid Ng18 of the 18th NMOS tube connects SEN, drain electrode Nd18 connects Ns17, source electrode Ns18 ground connection VSS；The grid Ng19 of the 19th NMOS tube connects Pd18, drain electrode Nd19 connect Pd20, source electrode Ns19 ground connection VSS；The grid of the 20th NMOS tube Ng20 connects R2, drain electrode Nd20 and connects Pd20, source electrode Ns20 ground connection VSS；21st NMOS The grid Ng21 of pipe connects Pd13, drain electrode Nd21 and connects Pd22, source electrode Ns21 ground connection VSS；The The grid Ng22 of 22 NMOS tube connects R1, and drain electrode Nd22 connection Pd22, source electrode Ns22 connect Ground VSS；The grid Ng23 of the 23rd NMOS tube connects c1, drain electrode Nd23 and connects Pd24, Source electrode Ns23 connects the drain electrode Nd24 of the 24th NMOS tube；The grid of the 24th NMOS tube Ng24 connects Pd20, drain electrode Nd24 and connects Ns23, source electrode Ns24 ground connection VSS；25th NMOS The grid Ng25 of pipe connects c2, drain electrode Nd25 and connects Pd26, source electrode Ns25 and connect the 26th NMOS The drain electrode Nd26 of pipe；The grid Ng26 of the 26th NMOS tube connects Pd22, and drain electrode Nd26 is even Meet Ns25, source electrode Ns26 ground connection VSS；9th PMOS, the tenth PMOS, the 11st PMOS and the tenth NMOS tube, the 11st NMOS tube, the 13rd NMOS tube main lock of composition Scan Architecture in storage；In 19th PMOS and the 20th NMOS tube composition main latch Resetting structure；
Described have eight inputs and two outfans from latch, and input is R1, R2, c1, c2, Cn1, cn2, m1, m1r；Outfan is s1, s1r；From latch by 12 PMOS and ten Two NMOS tube compositions, from latch, the substrate of all PMOS connects power vd D, all The Substrate ground VSS of NMOS tube；The grid Pg27 of the 27th PMOS connects m1r, drain electrode Pd27 connects the source electrode Ps28, source electrode Ps27 of the 28th PMOS and connects power vd D；Second The grid Pg28 of 18 PMOS connects cn1, drain electrode Pd28 and connects the 27th NMOS tube Drain electrode Nd27, source electrode Ps28 connect Pd27；The grid Pg29 of the 29th PMOS connects m1, Drain electrode Pd29 connects the source electrode Ps30, source electrode Ps29 of the 30th PMOS and connects power vd D；The The grid Pg30 of 30 PMOS connects cn2, drain electrode Pd30 and connects the 29th NMOS tube Drain electrode Nd29, source electrode Ps30 connect Pd29；The grid Pg31 of the 31st PMOS connects R1, Drain electrode Pd31 connects the source electrode Ps32, source electrode Ps31 of the 32nd PMOS and connects power vd D； The grid Pg32 of the 32nd PMOS connects Pd28, drain electrode Pd32 and connects the 32nd NMOS The drain electrode Nd32 of pipe, and connect the 30th as from latch outfan s1r, source electrode Ps32 The drain electrode Pd31 of one PMOS；The grid Pg33 of the 33rd PMOS connects R2, and drain Pd33 Connect the source electrode Ps34 of the 34th PMOS, source electrode Ps33 and connect power vd D；34th The grid Pg34 of PMOS connects Pd30, drain electrode Pd34 and connects the drain electrode of the 34th NMOS tube Nd34, and connect the 33rd PMOS as from latch outfan s1, source electrode Ps34 Drain electrode Pd33；The grid Pg35 of the 35th PMOS connects Pd34, drain electrode Pd35 and connects the The source electrode Ps36 of 36 PMOS, source electrode Ps35 connect power vd D；36th PMOS The grid Pg36 of pipe connect cn1, drain electrode Pd36 connect the 35th NMOS tube drain electrode Nd35 and Pd28, source electrode Ps36 connect Pd35；The grid Pg37 of the 37th PMOS connects Pd32, leakage Pole Pd37 connects the source electrode Ps38, source electrode Ps37 of the 38th PMOS and connects power vd D；The The grid Pg38 of 38 PMOS connects cn2, drain electrode Pd38 and connects the 37th NMOS tube Drain electrode Nd37 and Pd30, source electrode Ps38 connect Pd37；The grid Ng27 of the 27th NMOS tube Connect c, drain electrode Nd27 to connect Pd28, source electrode Ns27 and connect the drain electrode Nd28 of the 28th NMOS tube； The grid Ng28 of the 28th NMOS tube connects m1, drain electrode Nd28 and connects Ns27, source electrode Ns28 Ground connection VSS；The grid Ng29 of the 29th NMOS tube connects c2, drain electrode Nd29 and connects Pd30, Source electrode Ns29 connects the drain electrode Nd30 of the 30th NMOS tube；The grid Ng30 of the 30th NMOS tube Connect m1r, drain electrode Nd30 and connect Ns29, source electrode Ns30 ground connection VSS；31st NMOS tube Grid Ng31 connect Pd30, drain electrode Nd31 connect Pd32, source electrode Ns31 ground connection VSS；3rd The grid Ng32 of 12 NMOS tube connects R2, drain electrode Nd32 and connects Pd32, source electrode Ns32 ground connection VSS；The grid Ng33 of the 33rd NMOS tube connects Pd28, drain electrode Nd33 and connects Pd34, source Pole Ns33 ground connection VSS；The grid Ng34 of the 34th NMOS tube connects R1, and drain electrode Nd34 is even Meet Pd34, source electrode Ns34 ground connection VSS；The grid Ng35 of the 35th NMOS tube connects c1, Drain electrode Nd35 connects Pd36, source electrode Ns35 and connects the drain electrode Nd36 of the 36th NMOS tube；The The grid Ng36 of 36 NMOS tube connects Pd32, drain electrode Nd36 and connects Ns35, source electrode Ns36 Ground connection VSS；The grid Ng37 of the 37th NMOS tube connects c2, drain electrode Nd37 and connects Pd38, Source electrode Ns37 connects the drain electrode Nd38 of the 38th NMOS tube；The grid of the 38th NMOS tube Ng38 connects Pd34, drain electrode Nd38 and connects Ns37, source electrode Ns38 ground connection VSS；31st PMOS Pipe and the 32nd NMOS tube composition resetting structure from latch；
Described output buffer has two inputs and an outfan, and input connects s1 and s1r, Outfan is Q；Output buffer is made up of two PMOS and two NMOS tube；Output is slow The substrate rushing all PMOS of circuit connects power vd D, the Substrate ground VSS of all NMOS tube； The grid Pg49 of the 49th PMOS meets input s1r, drain electrode Pd49 and connects the 49th NMOS The drain electrode Nd49 of pipe, source electrode Ps49 meet power vd D；The grid Pg50 of the 50th PMOS connects Pd49, drain electrode Pd50 connect the drain electrode Nd50 of the 50th NMOS tube, and as output buffer Output Q；Source electrode Ps50 meets power vd D；The grid Ng49 of the 49th NMOS tube connects input End s1, drain electrode Nd49 connect Pd49, source electrode Ns49 ground connection VSS；The grid of the 50th NMOS tube Ng50 meets Nd49, drain electrode Nd50 and connects Pd50, source electrode Ns50 ground connection VSS.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6204707B1 (en) * 1998-08-26 2001-03-20 Kabushiki Kaisha Toshiba Flip-flop circuit with clock signal control function and clock control circuit
CN101447786A (en) * 2008-12-29 2009-06-03 北京时代民芯科技有限公司 Buffer cell circuit for resisting single-particle transient state
CN102394602A (en) * 2011-10-21 2012-03-28 中国人民解放军国防科学技术大学 Single event upset-resisting scanning structure D trigger capable of setting and resetting
CN103219970A (en) * 2013-04-02 2013-07-24 工业和信息化部电子第五研究所 Single-particle transient pulse width expanding method and circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6204707B1 (en) * 1998-08-26 2001-03-20 Kabushiki Kaisha Toshiba Flip-flop circuit with clock signal control function and clock control circuit
CN101447786A (en) * 2008-12-29 2009-06-03 北京时代民芯科技有限公司 Buffer cell circuit for resisting single-particle transient state
CN102394602A (en) * 2011-10-21 2012-03-28 中国人民解放军国防科学技术大学 Single event upset-resisting scanning structure D trigger capable of setting and resetting
CN103219970A (en) * 2013-04-02 2013-07-24 工业和信息化部电子第五研究所 Single-particle transient pulse width expanding method and circuit

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