CN103825579B - Anti-single particle upset and the resetted d type flip flop of single-ion transient state - Google Patents

Anti-single particle upset and the resetted d type flip flop of single-ion transient state Download PDF

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CN103825579B
CN103825579B CN201310670222.XA CN201310670222A CN103825579B CN 103825579 B CN103825579 B CN 103825579B CN 201310670222 A CN201310670222 A CN 201310670222A CN 103825579 B CN103825579 B CN 103825579B
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connects
drain electrode
nmos tube
pmos
grid
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CN103825579A (en
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陈书明
王崇峰
姚龙
孙永节
梁斌
池雅庆
郭阳
陈建军
刘祥远
许文涛
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National University of Defense Technology
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Abstract

The invention discloses anti-single particle upset and the resetted d type flip flop of single-ion transient state, it is therefore an objective to solve to reset d type flip flop anti-single particle transient state and the highest problem of anti-single particle upset ability.The present invention by clock circuit, reset buffer circuit, main latch, forms from latch, output buffer and buffer circuits.Main latch and be the latch that redundancy is reinforced, main latch and from latch tandem from latch, is all connected with clock circuit and reset buffer circuit.Main latch is also connected with buffer circuits, is also connected with output buffer from latch.Separate main latch and the C being mutually redundant from latch2Pull-up PMOS in MOS circuit and pull-down NMOS pipe, improve the primary particle inversion resistant ability of the present invention.Buffer circuits makes not make a mistake under long-term single event transient pulse, and duplication redundancy path further increases the ability of anti-single particle transient state.

Description

Anti-single particle upset and the resetted d type flip flop of single-ion transient state
Technical field
The present invention relates to a kind of D master-slave flip-flop, particularly to a kind of anti-single particle upset (Single Event Upset, SEU) and the resetted d type flip flop of anti-single particle transient state (Single Event Transient, SET).
Background technology
Cosmic space exists a large amount of high energy particle (proton, electronics, heavy ion etc.), in integrated circuit time Sequence circuit is by after these high-energy particle bombardments, and its state kept is likely to occur upset, and this effect is referred to as Single event upset effecf, the LET(linear energy transfer of single-particle bombardment integrated circuit) value is the highest, more holds It is easily generated Single event upset effecf.Combinational circuit in integrated circuit is by, after these high-energy particle bombardments, having May produce transient electrical pulses, this effect is referred to as single-ion transient state effect, the LET of single-particle bombardment integrated circuit Being worth the highest, the transient electrical pulses persistent period of generation is the longest, and electric pulse is the easiest to be gathered by sequence circuit.As Really the state of sequence circuit makes a mistake upset, or the transient electrical pulses that produces of single-ion transient state effect by time Sequence circuit error gathers, and integrated circuit operation instability all can be caused even to produce fatal mistake, and this is in boat My god, military field is particularly acute.Therefore, integrated circuit is reinforced thus reduce Single event upset effecf More and more important with single-ion transient state effect.
D type flip flop is to use one of most timing unit in integrated circuit, the upset of its anti-single particle and simple grain The anti-single particle of whole integrated circuit is overturn by the ability of sub-transient state and the ability of single-ion transient state plays crucial work With, d type flip flop is reinforced accordingly anti-single particle upset and the single-ion transient state energy that can make integrated circuit Power is improved.
Traditional d type flip flop is D master-slave flip-flop, typically by main latch with from level series of latches structure Become.Common lock storage is replaced with DICE(Dual Interlocked Storage Cell, dual interlocked storage cell) Primary particle inversion resistant d type flip flop can be realized etc. redundancy ruggedized construction.Transform input and output on this basis Port, it is possible to achieve anti-single particle upset simultaneously and single-ion transient state.M.J.Myjak et al. is at The47th IEEE International Midwest Symposium the 47th IEEE electricity of on Circuits and Systems( Road and the international conference of system Midwest) on " the Enhanced Fault-Tolerant CMOS Memory that delivers Elements " (strengthening fault-tolerant cmos memory cell) (2004, the I-453～I-456 page) upper proposition The DICE circuit of a kind of improvement, this circuit uses DICE circuit to carry out anti-single particle upset and reinforces, and handle Bidirectional data line divide into two write data lines and two read data lines, by the duplication redundancy of data wire, makes Travel to the single event transient pulse of DICE circuit by a certain data wire at any time and be difficult to cause whole The upset of individual circuit state, thus realize the reinforcing for single-ion transient state.But the duplication redundancy of data wire There is positive feedback loop, latch information upset can be produced under the single event transient pulse of longer duration, Anti-single particle transient state ability is the highest.
D.G.Mavis etc. are in IEEE Reliability Physics Symposium(world Reliability Physics meeting) On " the Soft error rate mitigation techniques for modern microcircuits " that deliver (reduce existing Technology for microcircuit soft error rate) (2002 page 216 page-225) propose time sampling D touch Send out device circuit.This circuit introduces delay and voting circuit in the feedback loop of latch data, thus possesses Certain anti-single particle upset and single-ion transient state ability.But voting circuit itself does not possess anti-single particle transient state Ability, under single event transient pulse can output error data, anti-single particle transient state ability is the highest.
The Chinese patent of Application No. 200910046337.5 discloses a kind of anti-single particle upset and single-particle wink The d type flip flop of state pulse.This invention is a kind of d type flip flop being similar to that time sampling structure, including Two variable connectors, two delay circuits, two protection gate circuits and three phase inverters, it is achieved that D triggers The anti-single particle upset of device and the reinforcing of single-ion transient state.This patent has the ability of anti-single particle transient state, but Outfan Q due to the 3rd reverser connects the input VIN0 of second variable connector, defines positive and negative It is fed back to road, latch information upset, anti-single particle can be produced under the single event transient pulse of longer duration Transient state ability is the highest.
Some integrated circuit needs to control the state of d type flip flop in integrated circuit, forces d type flip flop output height Level or low level.The original architecture basics of d type flip flop increases reset circuit and reset signal end, can To realize the resetting structure of d type flip flop self, and control d type flip flop reset function by reset signal. But the d type flip flop anti-single particle transient state that can reset at present and anti-single particle upset ability the highest, be unfavorable for aviation, The IC chip in the fields such as space flight uses.
The Chinese patent of Application No. 201110323795.6 discloses a kind of primary particle inversion resistant D that resets Trigger, as it is shown in figure 1, this invention by clock circuit, reset buffer circuit, main latch, from latch Device, output buffer form, and can normally work and not produce under the single-particle of higher LET value bombards Single-particle inversion.Owing to this invention and does not use buffer circuit before main latch in clock circuit, so Do not possess the ability of anti-single particle transient state, and main latch, be provided without duplication redundancy from latch, work as list When the LET value of particle bombardment is higher, some node upset on circuit then can cause whole circuit to overturn.
Summary of the invention
The technical problem to be solved in the present invention is, for current resetted d type flip flop anti-single particle transient state and The problem that anti-single particle upset ability is the highest, proposes the upset of a kind of anti-single particle and the resetted D of single-ion transient state Trigger.
Concretism of the present invention is: carries out duplication redundancy reinforcing to main latch with from latch, can resist list Particle overturns；Buffer circuit is added in clock circuit and before main latch, can be with anti-single particle transient state；Cut The disconnected positive feedback loop that may be caused by single event transient pulse from latch, can be in longer duration Anti-single particle transient state under do not overturn.
The resetted d type flip flop of anti-single particle of the present invention upset and single-ion transient state is slow by clock circuit, reset Rush circuit, main latch, form from latch, output buffer and buffer circuits.Main latch and It is the latch that redundancy is reinforced from latch.Main latch and from latch tandem and equal and clock Circuit and reset buffer circuit connect.Main latch is also connected with buffer circuits, from latch also with output Buffer circuit is connected.
The resetted d type flip flop of anti-single particle of the present invention upset and single-particle resistant transient pulse has three inputs With an outfan.Three inputs are clock signal input terminal CK, data signal input D respectively and answer Position signal input part RN；Outfan is Q.
Clock circuit has an input and four outfans, and input is CK, outfan is c1, c2, cn1, cn2.Clock circuit is made up of 12 PMOS and 14 NMOS, all PMOS in circuit Substrate connects power vd D, the Substrate ground VSS of all NMOS tube.The grid of the 43rd PMOS Pole Pg43 connects CK, drain electrode Pd43 and connects the drain electrode Nd43, source electrode Ps43 of the 43rd NMOS tube Connect power vd D；The grid Pg44 of the 44th PMOS connects the drain electrode of the 43rd PMOS Pd43, drain electrode Pd44 connect the drain electrode Nd44, source electrode Ps44 of the 44th NMOS tube and connect power vd D； The grid Pg45 of the 45th PMOS connects the drain electrode Pd44 of the 44th PMOS, and drain Pd45 Connect the drain electrode Nd45 of the 45th NMOS tube, source electrode Ps45 and connect power vd D；46th PMOS The grid Pg46 of pipe connects the drain electrode Pd45 of the 45th PMOS, drain electrode Pd46 and connects the 46th The drain electrode Nd46 of NMOS tube, source electrode Ps46 connect power vd D；The grid of the 47th PMOS Pg47 connects CK, drain electrode Pd47 and connects the source electrode Ps48, source electrode Ps47 of the 48th PMOS and connect VDD；The grid Pg48 of the 48th PMOS connects the drain electrode Pd46 of the 46th PMOS, leakage Pole Pd48 connects the drain electrode Nd47 of the 47th NMOS tube, and as an outfan cn1 of clock circuit； The grid Pg49 of the 49th PMOS connects CK, drain electrode Pd49 and connects the source of the 50th PMOS Pole Ps50, source electrode Ps49 connect VDD；The grid Pg50 of the 50th PMOS connects the 46th PMOS The drain electrode Pd46 of pipe, drain electrode Pd50 connect the drain electrode Nd49 of the 49th NMOS tube, and as clock electricity One outfan cn2 on road；The grid Pg51 of the 51st PMOS is as an output of clock circuit End c1, drain electrode Pd51 connect the drain electrode Pd48, source electrode Ps51 of the 48th PMOS and connect VDD； The grid Pg52 of the 52nd PMOS connects the grid Ng53 of the 53rd NMOS tube and as clock One outfan c2 of circuit, drain electrode Pd52 connect the 53rd NMOS tube drain electrode Nd53 and with output End cn2 is connected, and source electrode Ps52 connects VDD；The grid Pg53 of the 53rd PMOS connects outfan Cn1, drain electrode Pd53 connect outfan c1, source electrode Ps53 and connect VDD；The grid of the 54th PMOS Pole Pg54 connects outfan cn2, drain electrode Pd54 and connects outfan c2, source electrode Ps54 and connect VDD；4th The grid Ng43 of 13 NMOS tube connects CK, drain electrode Nd43 and connects the drain electrode of the 43rd PMOS Pd43；The grid Ng44 of the 44th NMOS tube connects the drain electrode Nd43 of the 43rd NMOS tube, Drain electrode Nd44 connects the drain electrode Pd44, source electrode Ns44 of the 44th PMOS and connects VSS；40th The grid Ng45 of five NMOS tube connects the drain electrode Nd44 of the 44th NMOS tube, drain electrode Nd45 and connects The drain electrode Pd45 of the 45th PMOS, source electrode Ns45 connect VSS；The grid of the 46th NMOS tube Pole Ng46 connects the drain electrode Nd45 of the 45th NMOS tube, drain electrode Nd46 and connects the 46th PMOS The drain electrode Pd46 of pipe, source electrode Ns46 connect VSS；The grid Ng47 of the 47th NMOS tube connects the The drain electrode Nd46 of 46 NMOS tube, source electrode Ns47 connect the drain electrode Nd48 of the 48th NMOS tube, Drain electrode connects cn1；The grid Ng48 of the 48th NMOS tube connects CK, drain electrode Nd48 and connects the 4th The source electrode Ns47 of 17 NMOS tube, source electrode Ns48 connect VSS；The grid of the 49th NMOS tube Ng49 connects the drain electrode Nd46, source electrode Ns49 of the 46th NMOS tube and connects the 50th NMOS tube Drain electrode Nd50, drain electrode connects cn2；The grid Ng50 of the 50th NMOS tube connects CK, and drain Nd50 Connect the source electrode Ns49 of the 49th NMOS tube, source electrode Ns50 and connect VSS；51st NMOS The grid Ng51 of pipe connects outfan c1, drain electrode Nd51 and connects outfan cn1, source electrode Ns51 and connect the The drain electrode Nd52 of 52 NMOS tube；The grid Ng52 of the 52nd NMOS tube connects outfan c1, Drain electrode Nd52 connects the 51st NMOS tube source electrode Ns51, source electrode Ns52 and connects VSS；53rd The grid Ng53 of NMOS tube connects outfan c2, drain electrode Nd53 and connects outfan cn2, source electrode Ns53 Connect the 54th NMOS tube drain electrode Nd54；The grid Ng54 of the 54th NMOS tube connects output End c2, drain electrode Nd54 connect the 53rd NMOS tube source electrode Ns53, source electrode Ns54 and connect VSS；The The grid Ng55 of 55 NMOS tube connects outfan cn1, drain electrode Nd55 and connects outfan c1, source electrode Ns55 connects VSS；The grid Ng56 of the 56th NMOS tube connects outfan cn2, and drain Nd56 Connect outfan c2, source electrode Ns56 and connect VSS.
Buffer circuits has an input and an outfan, and input is D, and outfan is D1.Buffering Circuit is made up of eight PMOS and eight NMOS tube, and in buffer circuit, the substrate of all PMOS is even Meet power vd D, the Substrate ground VSS of all NMOS tube.The grid Pg1 of the first PMOS connects Input D the grid Ng1 with the first NMOS tube connect, and drain electrode Pd1 connects the leakage of the first NMOS tube Pole Ng1, source electrode Ps1 connect VDD；The grid Pg2 of the second PMOS connects the leakage of the first PMOS Pole Pd1, drain electrode Pd2 connect the drain electrode Nd2, source electrode Ps2 of the second NMOS tube and connect VDD；3rd PMOS The grid Pg3 of pipe connects the drain electrode Pd2 of the second PMOS, drain electrode Pd3 and connects the leakage of the 3rd NMOS tube Pole Nd3, source electrode Ps3 connect VDD；The grid Pg4 of the 4th PMOS connects the leakage of the 3rd PMOS Pole Pd3, drain electrode Pd4 connect the drain electrode Nd4, source electrode Ps4 of the 4th NMOS tube and connect VDD；5th PMOS The grid Pg5 of pipe connects the drain electrode Pd4 of the 4th PMOS, drain electrode Pd5 and connects the leakage of the 5th NMOS tube Pole Nd5, source electrode Ps5 connect VDD；The grid Pg6 of the 6th PMOS connects the leakage of the 5th PMOS Pole Pd5, drain electrode Pd6 connect the drain electrode Nd6, source electrode Ps6 of the 6th NMOS tube and connect VDD；7th PMOS The grid Pg7 of pipe connects the drain electrode Pd6 of the 6th PMOS, drain electrode Pd7 and connects the leakage of the 7th NMOS tube Pole Nd7, source electrode Ps7 connect VDD；The grid Pg8 of the 8th PMOS connects the leakage of the 7th PMOS Pole Pd7, drain electrode Pd8 connect the drain electrode Nd8 of the 8th NMOS tube and as the output D1 of buffer, source Pole Ps8 connects VDD；The grid Ng1 of the first NMOS tube connects Pg1, drain electrode Nd1 and connects Pd1, source Pole Ns1 connects VSS;The grid Ng2 of the second NMOS tube connects the drain electrode Nd1 of the first NMOS tube, leakage Pole Nd2 connects Pd2, source electrode Ns2 and connects VSS；The grid Ng3 of the 3rd NMOS tube connects the 2nd NMOS The drain electrode Nd2 of pipe, drain electrode Nd3 connect Pd3, source electrode Ns3 and connect VSS；The grid of the 4th NMOS tube Ng4 connects the drain electrode Nd3 of the 3rd NMOS tube, drain electrode Nd4 and connects Pd4, source electrode Ns4 and connect VSS； The grid Ng5 of the 5th NMOS tube connects the drain electrode Nd4 of the 4th NMOS tube, drain electrode Nd5 and connects Pd5, Source electrode Ns5 connects VSS；The grid Ng6 of the 6th NMOS tube connects the drain electrode Nd5 of the 5th NMOS tube, Drain electrode Nd6 connects Pd6, source electrode Ns6 and connects VSS；The grid Ng7 of the 7th NMOS tube connects the 6th The drain electrode Nd6 of NMOS tube, drain electrode Nd7 connect Pd7, source electrode Ns7 and connect VSS；8th NMOS tube Grid Ng8 connect the 7th NMOS tube drain electrode Nd7, drain electrode Nd8 connect Pd8, source electrode Ns8 connect VSS。
Reset buffer circuit has an input and two outfans, and input is RN, and outfan is _ RN1_, _RN2_.Reset buffer circuit is made up of, in reset buffer circuit 8 NMOS tube and 8 PMOS The substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube.30th The grid Pg35 of five PMOS connects RN, drain electrode Pd35 and connects the drain electrode of the 35th NMOS tube Nd35, source electrode Ps35 connect power vd D；The grid Pg36 of the 36th PMOS connects the 35th The drain electrode Pd35 of PMOS, drain electrode Pd36 connect the drain electrode Nd36 of the 36th NMOS tube, source electrode Ps36 connects power vd D；The grid Pg37 of the 37th PMOS connects the 36th PMOS Drain electrode Pd36, drain electrode Pd37 connect the drain electrode Nd37, source electrode Ps37 of the 37th NMOS tube and connect electricity Source VDD；The grid Pg38 of the 38th PMOS connects the drain electrode Pd37 of the 37th PMOS, Drain electrode Pd38 connects the drain electrode Nd38, source electrode Ps38 of the 38th NMOS tube and connects power vd D；The The grid Pg39 of 39 PMOS connects RN, drain electrode Pd39 and connects the source electrode of the 40th PMOS Ps40, source electrode Ps39 connect VDD；The grid Pg40 of the 40th PMOS connects the 38th PMOS The drain electrode Pd38 of pipe, drain electrode Pd40 connect the drain electrode Nd39 of the 39th NMOS tube, and slow as resetting Outfan _ the RN1_, source electrode Ps40 that rush circuit connect Pd39；The grid of the 41st PMOS Pg41 connects RN, drain electrode Pd41 and connects the source electrode Ps42, source electrode Ps41 of the 42nd PMOS and connect VDD；The grid Pg42 of the 42nd PMOS connects the drain electrode Pd38 of the 38th PMOS, leakage Pole Pd42 connects the drain electrode Nd41 of the 41st NMOS tube, and as an output of reset buffer circuit End _ RN2_, source electrode Ps42 connect Pd41；The grid Ng35 of the 35th NMOS tube connects RN, leakage Pole Nd35 connects the drain electrode Pd35, source electrode Ns35 of the 35th PMOS and connects VSS；36th The grid Ng36 of NMOS tube connects the drain electrode Nd35 of the 35th NMOS tube, drain electrode Nd36 and connects the The drain electrode Pd36 of 36 PMOS, source electrode Ns36 connect VSS；The grid of the 37th NMOS tube Ng37 connects the drain electrode Nd36 of the 36th NMOS tube, drain electrode Nd37 and connects the 37th PMOS Drain electrode Pd37, source electrode Ns37 connect VSS；The grid Ng38 of the 38th NMOS tube connects the 3rd The drain electrode Nd37 of 17 NMOS tube, drain electrode Nd38 connect the drain electrode Pd38 of the 38th PMOS, Source electrode Ns38 connects VSS；The grid Ng39 of the 39th NMOS tube connects the 38th NMOS tube Drain electrode Nd38, source electrode Ns39 connect the 40th NMOS tube drain electrode Nd40, drain electrode Nd39 connect _RN1_；The grid Ng40 of the 40th NMOS tube connects RN, drain electrode Nd40 and connects the 39th NMOS The source electrode Ns39 of pipe, source electrode Ns40 connect VSS；The grid Ng41 of the 41st NMOS tube connects the The drain electrode Nd38 of 38 NMOS tube, source electrode Ns41 connect the drain electrode Nd42 of the 42nd NMOS tube, Drain electrode Nd41 connection _ RN2_；The grid Ng42 of the 42nd NMOS tube connects RN, and drain Nd42 Connect the source electrode Ns41 of the 41st NMOS tube, source electrode Ns42 and connect VSS.
Main latch has eight inputs and two outfans, input and D, D1, c1, c2, cn1, cn2, _ RN1_, _ RN2_ are connected；Outfan is m1, m1r.Main latch is by 14 PMOS and 14 NMOS forms, and in main latch, the substrate of all PMOS connects power vd D, all NMOS tube Substrate ground VSS.The grid Pg9 of the 9th PMOS connects D, drain electrode Pd9 and connects the tenth PMOS Source electrode Ps10, source electrode Ps9 connect VDD；The grid Pg10 of the tenth PMOS connects D1, source electrode Ps10 Connect the drain electrode Pd9 of the 9th PMOS, drain electrode Pd10 and connect the source electrode Ps11 of the 11st PMOS； The grid Pg11 of the 11st PMOS connects c1, source electrode Ps11 and connects the drain electrode Pd10 of the tenth PMOS, Drain electrode Pd11 connects the 9th NMOS drain electrode Nd9；The grid Pg12 of the 12nd PMOS connects D, drain electrode Connect the source electrode Ps13 of the 13rd PMOS, source electrode Ps12 and connect VDD；The grid Pg13 of the 13rd PMOS Connect D1, source electrode Ps13 and connect the drain electrode Pd12 of the 12nd PMOS, drain electrode Pd13 connection the 14th The source electrode Ps14 of PMOS；The grid Pg14 of the 14th PMOS connects c2, source electrode Ps14 and connects the The drain electrode Pd13 of 13 PMOS, drain electrode Pd14 connect the 12nd NMOS drain electrode Nd12；15th The grid Pg15 connection _ RN1_ of PMOS, drain electrode Pd15 connect the source electrode Ps16 of the 16th PMOS, Source electrode Ps15 connects power vd D；The grid Pg16 of the 16th PMOS connects Pd11, and drain Pd16 Connect the drain electrode Nd15 of the 15th NMOS tube and the output m1, source electrode Ps16 as main latch connects Pd15；The grid Pg17 connection _ RN2_ of the 17th PMOS, drain electrode Pd17 connect Ps18, source electrode Ps17 Connect power vd D；The grid Pg18 of the 18th PMOS connects Pd14, drain electrode Pd18 and connects the tenth The drain electrode Nd17 of seven NMOS tube, source electrode Ps18 connect Pd17；The grid Pg19 of the 19th PMOS Connect Pd18, drain electrode Pd19 to connect the source electrode Ps20, source electrode Ps19 of the 20th PMOS and connect power supply VDD；The grid Pg20 of the 20th PMOS connects cn1, drain electrode Pd20 and connects the 19th NMOS tube Drain electrode Nd19 and the 16th PMOS grid Pg16, source electrode Ps20 connect Pd19；21st PMOS The grid Pg21 of pipe connects Pd16, drain electrode Pd21 and connects the source electrode Ps22 of the 22nd PMOS, source electrode Ps21 connects power vd D；The grid Pg22 of the 22nd PMOS connects cn2, drain electrode Pd22 and connects The drain electrode Nd21 and the 18th PMOS grid Pg18 of the 21st NMOS tube, source electrode Ps22 connect Pd21；The grid Ng9 of the 9th NMOS tube connects cn1, source electrode Ns9 and connects the drain electrode of the tenth NMOS tube Nd10, drain electrode Nd9 connect the drain electrode Pd11 of the 11st PMOS；The grid Ng10 of the tenth NMOS tube Connect D1, drain electrode Nd10 to connect the source electrode Ns9, source electrode Ns10 of the 9th NMOS tube and connect Nd11；The The grid Ng11 of 11 NMOS tube connects input D, drain electrode Nd11 and connects Ns10, source electrode Ns11 and connect VSS；The grid Ng12 of the 12nd NMOS tube connects cn2, source electrode Ns12 and connects the 13rd NMOS tube Drain electrode Nd13, drain electrode Nd12 connect the 14th PMOS drain electrode Pd14；13rd NMOS tube Grid Ng13 connect D1, drain electrode Nd13 connect the 12nd NMOS tube source electrode Ns12, source electrode Ns13 Connect Nd14；The grid Ng14 of the 14th NMOS tube connects input D, drain electrode Nd14 and connects Ns13, Source electrode Ns11 connects VSS；The grid Ng15 of the 15th NMOS tube connects Pd14, drain electrode Nd15 and connects Pd16, source electrode Ns15 connect VSS；The grid Ng16 connection _ RN2_ of the 16th NMOS tube, drain electrode Nd16 connects Pd16, source electrode Ns16 and connects VSS；The grid Ng17 of the 17th NMOS tube connects Pd11, Drain electrode Nd17 connects Pd18, source electrode Ns17 ground connection VSS；The grid Ng18 of the 18th NMOS tube connects _ RN1_, drain electrode Nd18 connect Pd18 and connect VSS as main latch output m1r, source electrode Ns18； The grid Ng19 of the 19th NMOS tube connects c1, drain electrode Nd19 and connects Pd20, source electrode Ns19 and connect The drain electrode Nd20 of the 20th NMOS tube；The grid Ng20 of the 20th NMOS tube connects Pd16, drain electrode Nd20 connects Ns19, source electrode Ns20 ground connection VSS；The grid Ng21 of the 21st NMOS tube connects c2, Drain electrode Nd21 connects Pd22, source electrode Ns21 and connects the drain electrode Nd22 of the 22nd NMOS tube；20th The grid Ng22 of two NMOS tube connects Pd18, drain electrode Nd22 and connects Ns21, source electrode Ns22 ground connection VSS.
Eight inputs and two outfans are had from latch, input and c1, c2, cn1, cn2, m1, M1r, _ RN1_, _ RN2_ are connected；Outfan is s1, s1r.From latch by 12 PMOS and 12 NMOS tube compositions, from latch, the substrate of all PMOS connects power vd D, all The Substrate ground VSS of NMOS tube.The grid Pg23 of the 23rd PMOS connects m1r, and drain Pd23 Connect the source electrode Ps24 of the 24th PMOS, source electrode Ps23 and connect power vd D；24th PMOS The grid Pg24 of pipe connects cn1, drain electrode Pd24 and connects the drain electrode Nd23 of the 23rd NMOS tube, source electrode Connect Pd23；The grid Pg25 of the 25th PMOS connects m1, drain electrode Pd25 and connects the 26th The source electrode Ps26 of PMOS, source electrode Ps25 connect power vd D；The grid Pg26 of the 26th PMOS Connecting cn2, drain electrode Pd26 and connect the drain electrode Nd25 of the 25th NMOS tube, source electrode connects Pd25；The The grid Pg27 connection _ RN1_ of 27 PMOS, drain electrode Pd27 connect the 28th PMOS Source electrode Ps28, source electrode Ps27 connect power vd D；The grid Pg28 of the 28th PMOS connects Pd24, Drain electrode Pd28 connects the drain electrode Nd27 of the 27th NMOS tube and as the output s1 of main latch, source electrode Ps28 connects Pd27；The grid Pg29 connection _ RN2_ of the 29th PMOS, drain electrode Pd29 connect the The source electrode Ps30 of 30 PMOS, source electrode Ps29 connect power vd D；The grid of the 30th PMOS Pg30 connects Pd26, drain electrode Pd30 and connects the drain electrode Nd29 of the 29th NMOS tube and as from latch The output s1r of device, source electrode Ps30 connect Pd29；The grid Pg31 of the 31st PMOS connects Pd30, Drain electrode Pd31 connects the source electrode Ps32, source electrode Ps31 of the 32nd PMOS and connects power vd D；3rd The grid Pg32 of 12 PMOS connects c1, drain electrode Pd32 and connects the drain electrode of the 31st NMOS tube Nd31 and the 28th PMOS grid Pg28, source electrode Ps32 connect Pd31；33rd PMOS The grid Pg33 of pipe connects Pd28, drain electrode Pd33 and connects the source electrode Ps34 of the 34th PMOS, source electrode Ps33 connects power vd D；The grid Pg34 of the 34th PMOS connects c2, drain electrode Pd34 and connects The drain electrode Nd33 and the 30th PMOS grid Pg30 of the 33rd NMOS tube, source electrode Ps34 connect Pd33；The grid Ng23 of the 23rd NMOS tube connects c1, drain electrode Nd23 and connects Pd24, source electrode Ns23 Connect the drain electrode Nd24 of the 24th NMOS tube；The grid Ng24 of the 24th NMOS tube connects m1, Drain electrode Nd24 connects Ns23, source electrode Ns24 ground connection VSS；The grid Ng25 of the 25th NMOS tube Connect c2, drain electrode Nd25 to connect Pd26, source electrode Ns25 and connect the drain electrode Nd26 of the 26th NMOS tube； The grid Ng26 of the 26th NMOS tube connects m1r, and drain electrode Nd26 connection Ns25, source electrode Ns26 connect Ground VSS；The grid Ng27 of the 27th NMOS tube connects Pd26, drain electrode Nd27 and connects Pd28, source Pole Ns27 connects VSS；The grid Ng28 connection _ RN2_ of the 28th NMOS tube, drain electrode Nd28 is even Meet Pd28, source electrode Ns28 and connect VSS；The grid Ng29 of the 29th NMOS tube connects Pd24, leakage Pole Nd29 connects Pd30, source electrode Ns29 and connects VSS；The grid Ng30 of the 30th NMOS tube connects _ RN1_, drain electrode Nd30 connect Pd30, source electrode Ns30 and connect VSS；The grid of the 31st NMOS tube Pole Ng31 connects cn1, drain electrode Nd31 and connects Pd32, source electrode Ns31 and connect the 32nd NMOS tube Drain electrode Nd32；The grid Ng32 of the 32nd NMOS tube connects Pd28, drain electrode Nd32 and connects Ns31, Source electrode Ns32 ground connection VSS；The grid Ng33 of the 33rd NMOS tube connects cn2, and drain electrode Nd33 is even Meet Pd34, source electrode Ns33 and connect the drain electrode Nd34 of the 34th NMOS tube；34th NMOS tube Grid Ng34 connect Pd30, drain electrode Nd34 connect Ns33, source electrode Ns34 ground connection VSS.
Output buffer has two inputs and an outfan, and input connects s1 and s1r, and outfan is Q.Output buffer is made up of two PMOS and two NMOS tube, all in output buffer The substrate of PMOS connects power vd D, the Substrate ground VSS of all NMOS tube.55th PMOS The grid Pg55 of pipe connects s1r, drain electrode Pd55 and connects the drain electrode Nd57 of the 57th NMOS tube, source electrode Ps55 connects power vd D；The grid Pg56 of the 56th PMOS connects the 55th PMOS Drain electrode Pd55, drain electrode Pd56 connect the drain electrode Nd58 of the 58th NMOS tube, and as inverter circuit Output Q, source electrode Ps56 connect power vd D；The grid Ng57 of the 57th NMOS tube connects s1, Drain electrode Nd57 connects the drain electrode Pd55 of the 55th PMOS；The grid Ng58 of the 58th NMOS tube Connect the drain electrode Nd57 of the 57th NMOS tube, drain electrode Nd58 and connect the drain electrode of the 56th PMOS Pd56, source electrode Ns58 connect VSS.
The resetted d type flip flop work process of anti-single particle of the present invention upset and anti-single particle transient state is as follows:
The resetted d type flip flop of anti-single particle of the present invention upset and single-ion transient state can be carried out at any time Resetting, reset function is controlled by the i.e. reset signal input of RN.
When RN is low level, anti-single particle of the present invention upset and the resetted d type flip flop of single-ion transient state Enter reset state, i.e. main latch and from latch all by latching logic by force " 0 ", output buffer Outfan Q be low level.
When RN is high level, anti-single particle of the present invention upset resets and reset D with single-ion transient state Trigger is in normal operating conditions, and clock circuit receives CK, by shape in the middle of circuit after buffering it The inverter circuit become produces cn1 and cn2 reverse with CK, is produced by the inverter circuit of circuit end With CK c1 and c2 in the same direction, and cn1, cn2, c1 and c2 are passed to main latch and from latch. Buffer circuits receives D, and after being postponed by D, output and the D1 of D homophase, be between low period at CK, Cn1 and cn2 be high level, c1 and c2 be low level, main latch is opened, and receives D and D1, and to D With in D1 may with single event transient pulse filter, then by latch output with D homophase M1 and m1r, be in preservation state from latch, do not receive main latch output m1, m1r, but Preserve m1, m1r that a CK trailing edge samples；Being between high period at CK, cn1 and cn2 is Low level, c1 and c2 are high level, and main latch is in preservation state, preserve previous CK rising edge and adopt D and D1 that sample arrives also exports m1 and m1r with D homophase, opens from latch and receives main latch Output m1 and m1r, buffers m1 and m1r and exports and s1 and s1r of m1 and m1r homophase. Output buffer will receive output s1 and s1r from latch at any time, buffers s1 and s1r And export the Q with s1 and s1r homophase.
Reset buffer circuit input signal is postponed after by the C of duplication redundancy2MOS structure filters RN Middle may with single event transient pulse, and by output with RN homophase _ RN1_ and _ RN2_ send into lead Latch and from latch, carries out the control of reset behavior.
Use the present invention can reach techniques below effect:
The anti-single particle of the resetted d type flip flop of anti-single particle of the present invention upset and single-ion transient state overturns and anti- Single-ion transient state ability is better than the unguyed d type flip flop of tradition, the d type flip flop of time sampling reinforcing and tradition The d type flip flop that duplication redundancy is reinforced.The unguyed d type flip flop structure of tradition is transformed by the present invention, right Main latch and all carried out duplication redundancy reinforcing from latch, and for main latch and from latch C2 MOS circuit is improved, and i.e. separates the C being mutually redundant2Pull-up PMOS in MOS circuit and under Draw NMOS tube, improve the primary particle inversion resistant ability of the present invention.In clock circuit and before main latch Add buffer circuits, make the present invention not make a mistake under long-term single event transient pulse； By well-designed duplication redundancy path, cut off and just may be caused by single event transient pulse from latch Feedback circuit, further increases the ability of anti-single particle transient state.Anti-single particle of the present invention upset and single-particle Transient state reset and reset d type flip flop be suitable for anti-single particle upset and anti-single particle transient state reinforce integrated The standard cell lib of circuit, is applied to the fields such as Aeronautics and Astronautics.
Accompanying drawing explanation
Fig. 1 is that the primary particle inversion resistant d type flip flop that resets of Application No. 201110323795.6 is totally patrolled Collect structural representation
Fig. 2 is anti-single particle of the present invention upset and the resetted d type flip flop overall logic structure of single-ion transient state Schematic diagram.
Fig. 3 is the clock circuit knot of the resetted d type flip flop of anti-single particle of the present invention upset and single-ion transient state Structure schematic diagram.
Fig. 4 is anti-single particle of the present invention upset and buffer circuits in the resetted d type flip flop of single-ion transient state Structural representation.
Fig. 5 be anti-single particle of the present invention upset and single-ion transient state can reset buffer circuit in reset flip-flop Structural representation
Fig. 6 is anti-single particle of the present invention upset and main latch knot in the resetted d type flip flop of single-ion transient state Structure schematic diagram.
Fig. 7 is that anti-single particle of the present invention upset is tied from latch in the resetted d type flip flop of single-ion transient state Structure schematic diagram.
Fig. 8 is anti-single particle of the present invention upset and output buffering electricity in the resetted d type flip flop of single-ion transient state Line structure schematic diagram.
Detailed description of the invention
Fig. 2 is the resetted d type flip flop logical structure signal of anti-single particle of the present invention upset and single-ion transient state Figure.The present invention is by clock circuit (as shown in Figure 3), buffer circuits (as shown in Figure 4), reset buffering Circuit (as shown in Figure 5), main latch (as shown in Figure 6), from latch (as shown in Figure 7), output Buffer circuit (as shown in Figure 8) forms.Anti-single particle of the present invention upset and the resetted D of single-ion transient state Trigger has three inputs and an outfan.Three inputs be respectively CK i.e. clock signal input terminal, D i.e. data signal input and RN i.e. reset signal input；Outfan is Q.Clock circuit receives CK, C1, c2 and cn1, cn2 is exported respectively after CK is carried out buffered.Buffer circuits receives D, and right It carries out output and the D1 of D homophase after time delay.Main latch receives D and D1, c1, c2 and cn1, cn2 And _ RN1_, _ RN2_, main latch is in c1, c2 and cn1, cn2 and _ RN1_, the control of _ RN2_ M1, m1r is exported after D and D1 is carried out under system latch process.From latch receive m1, m1r and c1, C2 and cn1, cn2, _ RN1_, _ RN2_, from latch at c1, c2 and cn1, cn2, _ RN1_, _ RN2_ Control under m1, m1r are carried out latch process after export s1, s1r respectively.Output buffer reception s1, S1r, exports Q after it is carried out buffered.
As it is shown on figure 3, clock circuit has an input and four outfans, input is CK, outfan For c1, c2, cn1, cn2.Clock circuit is made up of, in circuit 12 PMOS and 14 NMOS The substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube.40th The grid Pg43 of three PMOS connects CK, drain electrode Pd43 and connects the drain electrode of the 43rd NMOS tube Nd43, source electrode Ps43 connect power vd D；The grid Pg44 of the 44th PMOS connects the 43rd The drain electrode Pd43 of PMOS, drain electrode Pd44 connect the drain electrode Nd44 of the 44th NMOS tube, source electrode Ps44 connects power vd D；The grid Pg45 of the 45th PMOS connects the 44th PMOS Drain electrode Pd44, drain electrode Pd45 connect the drain electrode Nd45, source electrode Ps45 of the 45th NMOS tube and connect electricity Source VDD；The grid Pg46 of the 46th PMOS connects the drain electrode Pd45 of the 45th PMOS, Drain electrode Pd46 connects the drain electrode Nd46, source electrode Ps46 of the 46th NMOS tube and connects power vd D；The The grid Pg47 of 47 PMOS connects CK, drain electrode Pd47 and connects the source of the 48th PMOS Pole Ps48, source electrode Ps47 connect VDD；The grid Pg48 of the 48th PMOS connects the 46th The drain electrode Pd46 of PMOS, drain electrode Pd48 connect the drain electrode Nd47 of the 47th NMOS tube, and conduct One outfan cn1 of clock circuit；The grid Pg49 of the 49th PMOS connects CK, and drain Pd49 Connect the source electrode Ps50 of the 50th PMOS, source electrode Ps49 and connect VDD；The grid of the 50th PMOS Pole Pg50 connects the drain electrode Pd46 of the 46th PMOS, drain electrode Pd50 and connects the 49th NMOS The drain electrode Nd49 of pipe, and as an outfan cn2 of clock circuit；The grid of the 51st PMOS Pg51 connects the drain electrode of the 48th PMOS as an outfan c1 of clock circuit, drain electrode Pd51 Pd48, source electrode Ps51 connect VDD；The grid Pg52 of the 52nd PMOS connects the 53rd NMOS The grid Ng53 of pipe the outfan c2, drain electrode Pd52 as clock circuit connect the 53rd NMOS The drain electrode Nd53 of pipe is also connected with outfan cn2, and source electrode Ps52 connects VDD；53rd PMOS Grid Pg53 connect outfan cn1, drain electrode Pd53 connect outfan c1, source electrode Ps53 connect VDD； The grid Pg54 of the 54th PMOS connects outfan cn2, drain electrode Pd54 and connects outfan c2, source Pole Ps54 connects VDD；The grid Ng43 of the 43rd NMOS tube connects CK, drain electrode Nd43 and connects The drain electrode Pd43 of the 43rd PMOS；The grid Ng44 of the 44th NMOS tube connects the 43rd The drain electrode Nd43 of NMOS tube, drain electrode Nd44 connect the drain electrode Pd44 of the 44th PMOS, source electrode Ns44 connects VSS；The grid Ng45 of the 45th NMOS tube connects the leakage of the 44th NMOS tube Pole Nd44, drain electrode Nd45 connect the drain electrode Pd45, source electrode Ns45 of the 45th PMOS and connect VSS； The grid Ng46 of the 46th NMOS tube connects the drain electrode Nd45 of the 45th NMOS tube, and drain Nd46 Connect the drain electrode Pd46 of the 46th PMOS, source electrode Ns46 and connect VSS；47th NMOS tube Grid Ng47 connect the 46th NMOS tube drain electrode Nd46, source electrode Ns47 connect the 48th The drain electrode Nd48 of NMOS tube, drain electrode connects cn1；The grid Ng48 of the 48th NMOS tube connects CK, Drain electrode Nd48 connects the source electrode Ns47, source electrode Ns48 of the 47th NMOS tube and connects VSS；40th The grid Ng49 of nine NMOS tube connects the drain electrode Nd46, source electrode Ns49 of the 46th NMOS tube and connects The drain electrode Nd50 of the 50th NMOS tube, drain electrode connects cn2；The grid Ng50 of the 50th NMOS tube is even Meet CK, drain electrode Nd50 to connect the source electrode Ns49, source electrode Ns50 of the 49th NMOS tube and connect VSS； The grid Ng51 of the 51st NMOS tube connects outfan c1, drain electrode Nd51 and connects outfan cn1, source Pole Ns51 connects the drain electrode Nd52 of the 52nd NMOS tube；The grid Ng52 of the 52nd NMOS tube Connect outfan c1, drain electrode Nd52 to connect the 51st NMOS tube source electrode Ns51, source electrode Ns52 and connect VSS；The grid Ng53 of the 53rd NMOS tube connects outfan c2, drain electrode Nd53 and connects outfan Cn2, source electrode Ns53 connect the 54th NMOS tube drain electrode Nd54；The grid of the 54th NMOS tube Ng54 connects outfan c2, drain electrode Nd54 and connects the 53rd NMOS tube source electrode Ns53, source electrode Ns54 Connect VSS；The grid Ng55 of the 55th NMOS tube connects outfan cn1, and drain electrode Nd55 connects defeated Going out and hold c1, source electrode Ns55 connects VSS；The grid Ng56 of the 56th NMOS tube connects outfan cn2, Drain electrode Nd56 connects outfan c2, source electrode Ns56 and connects VSS.
As shown in Figure 4, buffer circuits has an input and an outfan, and input is D, output End is D1.Buffer circuit is made up of eight PMOS and eight NMOS tube, all PMOS in buffer circuit The substrate of pipe connects power vd D, the Substrate ground VSS of all NMOS tube.The grid of the first PMOS Pole Pg1 connects input D and the grid Ng1 with the first NMOS tube connects, and drain electrode Pd1 connects a NMOS The drain electrode Ng1 of pipe, source electrode Ps1 connect VDD；The grid Pg2 of the second PMOS connects a PMOS The drain electrode Pd1 of pipe, drain electrode Pd2 connect the drain electrode Nd2, source electrode Ps2 of the second NMOS tube and connect VDD； The grid Pg3 of the 3rd PMOS connects the drain electrode Pd2 of the second PMOS, drain electrode Pd3 and connects the 3rd The drain electrode Nd3 of NMOS tube, source electrode Ps3 connect VDD；The grid Pg4 of the 4th PMOS connects the 3rd The drain electrode Pd3 of PMOS, drain electrode Pd4 connect the drain electrode Nd4, source electrode Ps4 of the 4th NMOS tube and connect VDD；The grid Pg5 of the 5th PMOS connects the drain electrode Pd4 of the 4th PMOS, drain electrode Pd5 and connects The drain electrode Nd5 of the 5th NMOS tube, source electrode Ps5 connect VDD；The grid Pg6 of the 6th PMOS is even Meet the drain electrode Pd5 of the 5th PMOS, drain electrode Pd6 and connect the drain electrode Nd6, source electrode Ps6 of the 6th NMOS tube Connect VDD；The grid Pg7 of the 7th PMOS connects the drain electrode Pd6 of the 6th PMOS, and drain Pd7 Connect the drain electrode Nd7 of the 7th NMOS tube, source electrode Ps7 and connect VDD；The grid Pg8 of the 8th PMOS Connect the drain electrode Pd7 of the 7th PMOS, drain electrode Pd8 and connect drain electrode Nd8 the conduct of the 8th NMOS tube The output D1 of buffer, source electrode Ps8 connect VDD；The grid Ng1 of the first NMOS tube connects Pg1, Drain electrode Nd1 connects Pd1, source electrode Ns1 and connects VSS;The grid Ng2 of the second NMOS tube connects a NMOS The drain electrode Nd1 of pipe, drain electrode Nd2 connect Pd2, source electrode Ns2 and connect VSS；The grid of the 3rd NMOS tube Ng3 connects the drain electrode Nd2 of the second NMOS tube, drain electrode Nd3 and connects Pd3, source electrode Ns3 and connect VSS； The grid Ng4 of the 4th NMOS tube connects the drain electrode Nd3 of the 3rd NMOS tube, drain electrode Nd4 and connects Pd4, Source electrode Ns4 connects VSS；The grid Ng5 of the 5th NMOS tube connects the drain electrode Nd4 of the 4th NMOS tube, Drain electrode Nd5 connects Pd5, source electrode Ns5 and connects VSS；The grid Ng6 of the 6th NMOS tube connects the 5th The drain electrode Nd5 of NMOS tube, drain electrode Nd6 connect Pd6, source electrode Ns6 and connect VSS；7th NMOS tube Grid Ng7 connect the 6th NMOS tube drain electrode Nd6, drain electrode Nd7 connect Pd7, source electrode Ns7 connect VSS；The grid Ng8 of the 8th NMOS tube connects the drain electrode Nd7 of the 7th NMOS tube, and drain electrode Nd8 is even Meet Pd8, source electrode Ns8 and connect VSS.
As it is shown in figure 5, reset buffer circuit has an input and two outfans, input is RN, defeated Going out end is _ RN1_, _ RN2_.Reset buffer circuit is made up of 8 NMOS tube and 8 PMOS, In reset buffer circuit, the substrate of all PMOS connects power vd D, and the substrate of all NMOS tube connects Ground VSS.The grid Pg35 of the 35th PMOS connects RN, drain electrode Pd35 and connects the 35th NMOS The drain electrode Nd35 of pipe, source electrode Ps35 connect power vd D；The grid Pg36 of the 36th PMOS is even Meet the drain electrode Pd35 of the 35th PMOS, drain electrode Pd36 and connect the drain electrode of the 36th NMOS tube Nd36, source electrode Ps36 connect power vd D；The grid Pg37 of the 37th PMOS connects the 36th The drain electrode Pd36 of PMOS, drain electrode Pd37 connect the drain electrode Nd37 of the 37th NMOS tube, source electrode Ps37 connects power vd D；The grid Pg38 of the 38th PMOS connects the 37th PMOS Drain electrode Pd37, drain electrode Pd38 connect the drain electrode Nd38, source electrode Ps38 of the 38th NMOS tube and connect electricity Source VDD；The grid Pg39 of the 39th PMOS connects RN, drain electrode Pd39 and connects the 40th PMOS The source electrode Ps40 of pipe, source electrode Ps39 connect VDD；The grid Pg40 of the 40th PMOS connects the 30th The drain electrode Pd38 of eight PMOS, drain electrode Pd40 connect the drain electrode Nd39 of the 39th NMOS tube, and An outfan _ RN1_, source electrode Ps40 as reset buffer circuit connect Pd39；41st PMOS The grid Pg41 of pipe connects RN, drain electrode Pd41 and connects the source electrode Ps42 of the 42nd PMOS, source electrode Ps41 connects VDD；The grid Pg42 of the 42nd PMOS connects the drain electrode of the 38th PMOS Pd38, drain electrode Pd42 connect the drain electrode Nd41 of the 41st NMOS tube, and as reset buffer circuit One outfan _ RN2_, source electrode Ps42 connect Pd41；The grid Ng35 of the 35th NMOS tube connects RN, drain electrode Nd35 connect the drain electrode Pd35, source electrode Ns35 of the 35th PMOS and connect VSS；The The grid Ng36 of 36 NMOS tube connects the drain electrode Nd35 of the 35th NMOS tube, and drain Nd36 Connect the drain electrode Pd36 of the 36th PMOS, source electrode Ns36 and connect VSS；37th NMOS tube Grid Ng37 connect the 36th NMOS tube drain electrode Nd36, drain electrode Nd37 connect the 37th The drain electrode Pd37 of PMOS, source electrode Ns37 connect VSS；The grid Ng38 of the 38th NMOS tube Connect the drain electrode Nd37 of the 37th NMOS tube, drain electrode Nd38 and connect the drain electrode of the 38th PMOS Pd38, source electrode Ns38 connect VSS；The grid Ng39 of the 39th NMOS tube connects the 38th NMOS The drain electrode Nd38 of pipe, source electrode Ns39 connect the drain electrode Nd40 of the 40th NMOS tube, drain electrode Nd39 and connect _RN1_；The grid Ng40 of the 40th NMOS tube connects RN, drain electrode Nd40 and connects the 39th NMOS The source electrode Ns39 of pipe, source electrode Ns40 connect VSS；The grid Ng41 of the 41st NMOS tube connects the The drain electrode Nd38 of 38 NMOS tube, source electrode Ns41 connect the drain electrode Nd42 of the 42nd NMOS tube, Drain electrode Nd41 connection _ RN2_；The grid Ng42 of the 42nd NMOS tube connects RN, and drain Nd42 Connect the source electrode Ns41 of the 41st NMOS tube, source electrode Ns42 and connect VSS.
As shown in Figure 6, main latch has eight inputs and two outfans, input and D, D1, c1, C2, cn1, cn2, _ RN1_, _ RN2_ are connected；Outfan is m1, m1r.Main latch is by 14 PMOS and 14 NMOS compositions, in main latch, the substrate of all PMOS connects power vd D, The Substrate ground VSS of all NMOS tube.The grid Pg9 of the 9th PMOS connects D, and drain electrode Pd9 is even Meet the source electrode Ps10 of the tenth PMOS, source electrode Ps9 and connect VDD；The grid Pg10 of the tenth PMOS connects D1, source electrode Ps10 connect the drain electrode Pd9 of the 9th PMOS, drain electrode Pd10 and connect the 11st PMOS Source electrode Ps11；The grid Pg11 of the 11st PMOS connects c1, source electrode Ps11 and connects the tenth PMOS The drain electrode Pd10 of pipe, drain electrode Pd11 connect the 9th NMOS drain electrode Nd9；The grid Pg12 of the 12nd PMOS Connecting D, drain electrode connects the source electrode Ps13, source electrode Ps12 of the 13rd PMOS and connects VDD；13rd PMOS Grid Pg13 connect D1, source electrode Ps13 connect the 12nd PMOS drain electrode Pd12, drain Pd13 Connect the source electrode Ps14 of the 14th PMOS；The grid Pg14 of the 14th PMOS connects c2, source electrode Ps14 connects the drain electrode Pd13 of the 13rd PMOS, drain electrode Pd14 and connects the 12nd NMOS drain electrode Nd12； The grid Pg15 connection _ RN1_ of the 15th PMOS, drain electrode Pd15 connect the source of the 16th PMOS Pole Ps16, source electrode Ps15 connect power vd D；The grid Pg16 of the 16th PMOS connects Pd11, Drain electrode Pd16 connects the drain electrode Nd15 of the 15th NMOS tube and as the output m1 of main latch, source electrode Ps16 connects Pd15；The grid Pg17 connection _ RN2_ of the 17th PMOS, drain electrode Pd17 connect Ps18, Source electrode Ps17 connects power vd D；The grid Pg18 of the 18th PMOS connects Pd14, and drain Pd18 Connect the drain electrode Nd17 of the 17th NMOS tube, source electrode Ps18 and connect Pd17；The grid of the 19th PMOS Pole Pg19 connects Pd18, drain electrode Pd19 and connects the source electrode Ps20, source electrode Ps19 of the 20th PMOS even Meet power vd D；The grid Pg20 of the 20th PMOS connects cn1, drain electrode Pd20 and connects the 19th The drain electrode Nd19 and the 16th PMOS grid Pg16 of NMOS tube, source electrode Ps20 connects Pd19；The The grid Pg21 of 21 PMOS connects Pd16, drain electrode Pd21 and connects the source of the 22nd PMOS Pole Ps22, source electrode Ps21 connect power vd D；The grid Pg22 of the 22nd PMOS connects cn2, Drain electrode Pd22 connects the drain electrode Nd21 and the 18th PMOS grid Pg18 of the 21st NMOS tube, Source electrode Ps22 connects Pd21；The grid Ng9 of the 9th NMOS tube connects cn1, source electrode Ns9 and connects the tenth The drain electrode Nd10 of NMOS tube, drain electrode Nd9 connect the drain electrode Pd11 of the 11st PMOS；Tenth NMOS The grid Ng10 of pipe connects D1, drain electrode Nd10 and connects the source electrode Ns9, source electrode Ns10 of the 9th NMOS tube Connect Nd11；The grid Ng11 of the 11st NMOS tube connects input D, drain electrode Nd11 and connects Ns10, Source electrode Ns11 connects VSS；The grid Ng12 of the 12nd NMOS tube connects cn2, source electrode Ns12 and connects The drain electrode Nd13 of the 13rd NMOS tube, drain electrode Nd12 connect the drain electrode Pd14 of the 14th PMOS； The grid Ng13 of the 13rd NMOS tube connects D1, drain electrode Nd13 and connects the source electrode of the 12nd NMOS tube Ns12, source electrode Ns13 connect Nd14；The grid Ng14 of the 14th NMOS tube connects input D, drain electrode Nd14 connects Ns13, source electrode Ns11 and connects VSS；The grid Ng15 of the 15th NMOS tube connects Pd14, Drain electrode Nd15 connects Pd16, source electrode Ns15 and connects VSS；The grid Ng16 of the 16th NMOS tube connects _ RN2_, drain electrode Nd16 connect Pd16, source electrode Ns16 and connect VSS；The grid of the 17th NMOS tube Ng17 connects Pd11, drain electrode Nd17 and connects Pd18, source electrode Ns17 ground connection VSS；18th NMOS The grid Ng18 connection _ RN1_ of pipe, drain electrode Nd18 connect Pd18 and export m1r, source as main latch Pole Ns18 connects VSS；The grid Ng19 of the 19th NMOS tube connects c1, drain electrode Nd19 and connects Pd20, Source electrode Ns19 connects the drain electrode Nd20 of the 20th NMOS tube；The grid Ng20 of the 20th NMOS tube is even Meet Pd16, drain electrode Nd20 and connect Ns19, source electrode Ns20 ground connection VSS；The grid of the 21st NMOS tube Pole Ng21 connects c2, drain electrode Nd21 and connects Pd22, source electrode Ns21 and connect the 22nd NMOS tube Drain electrode Nd22；The grid Ng22 of the 22nd NMOS tube connects Pd18, drain electrode Nd22 and connects Ns21, Source electrode Ns22 ground connection VSS.
As it is shown in fig. 7, have eight inputs and two outfans from latch, input and c1, c2, cn1, Cn2, m1, m1r, _ RN1_, _ RN2_ are connected；Outfan is s1, s1r.From latch by 12 PMOS Pipe and 12 NMOS tube compositions, from latch, the substrate of all PMOS connects power vd D, The Substrate ground VSS of all NMOS tube.The grid Pg23 of the 23rd PMOS connects m1r, leakage Pole Pd23 connects the source electrode Ps24, source electrode Ps23 of the 24th PMOS and connects power vd D；20th The grid Pg24 of four PMOS connects cn1, drain electrode Pd24 and connects the drain electrode of the 23rd NMOS tube Nd23, source electrode connects Pd23；The grid Pg25 of the 25th PMOS connects m1, and drain electrode Pd25 is even Meet the source electrode Ps26 of the 26th PMOS, source electrode Ps25 and connect power vd D；26th PMOS The grid Pg26 of pipe connects cn2, drain electrode Pd26 and connects the drain electrode Nd25 of the 25th NMOS tube, source electrode Connect Pd25；The grid Pg27 connection _ RN1_ of the 27th PMOS, drain electrode Pd27 connect the 20th The source electrode Ps28 of eight PMOS, source electrode Ps27 connect power vd D；The grid of the 28th PMOS Pg28 connects Pd24, drain electrode Pd28 and connects the drain electrode Nd27 of the 27th NMOS tube and as main latch The output s1 of device, source electrode Ps28 connect Pd27；The grid Pg29 connection _ RN2_ of the 29th PMOS, Drain electrode Pd29 connects the source electrode Ps30, source electrode Ps29 of the 30th PMOS and connects power vd D；30th The grid Pg30 of PMOS connects Pd26, drain electrode Pd30 and connects the drain electrode Nd29 of the 29th NMOS tube And connect Pd29 as from the output s1r of latch, source electrode Ps30；The grid Pg31 of the 31st PMOS Connect Pd30, drain electrode Pd31 to connect the source electrode Ps32, source electrode Ps31 of the 32nd PMOS and connect power supply VDD；The grid Pg32 of the 32nd PMOS connects c1, drain electrode Pd32 and connects the 31st NMOS The drain electrode Nd31 and the 28th PMOS grid Pg28 of pipe, source electrode Ps32 connects Pd31；30th The grid Pg33 of three PMOS connects Pd28, drain electrode Pd33 and connects the source electrode of the 34th PMOS Ps34, source electrode Ps33 connect power vd D；The grid Pg34 of the 34th PMOS connects c2, drain electrode Pd34 connects drain electrode Nd33 and the 30th PMOS grid Pg30, the source electrode of the 33rd NMOS tube Ps34 connects Pd33；The grid Ng23 of the 23rd NMOS tube connects c1, drain electrode Nd23 and connects Pd24, Source electrode Ns23 connects the drain electrode Nd24 of the 24th NMOS tube；The grid Ng24 of the 24th NMOS tube Connect m1, drain electrode Nd24 and connect Ns23, source electrode Ns24 ground connection VSS；The grid of the 25th NMOS tube Pole Ng25 connects c2, drain electrode Nd25 and connects Pd26, source electrode Ns25 and connect the 26th NMOS tube Drain electrode Nd26；The grid Ng26 of the 26th NMOS tube connects m1r, drain electrode Nd26 and connects Ns25, Source electrode Ns26 ground connection VSS；The grid Ng27 of the 27th NMOS tube connects Pd26, and drain Nd27 Connect Pd28, source electrode Ns27 and connect VSS；The grid Ng28 connection _ RN2_ of the 28th NMOS tube, Drain electrode Nd28 connects Pd28, source electrode Ns28 and connects VSS；The grid Ng29 of the 29th NMOS tube Connect Pd24, drain electrode Nd29 to connect Pd30, source electrode Ns29 and connect VSS；The grid of the 30th NMOS tube Pole Ng30 connection _ RN1_, drain electrode Nd30 connect Pd30, source electrode Ns30 and connect VSS；31st NMOS The grid Ng31 of pipe connects cn1, drain electrode Nd31 and connects Pd32, source electrode Ns31 and connect the 32nd NMOS The drain electrode Nd32 of pipe；The grid Ng32 of the 32nd NMOS tube connects Pd28, drain electrode Nd32 and connects Ns31, source electrode Ns32 ground connection VSS；The grid Ng33 of the 33rd NMOS tube connects cn2, drain electrode Nd33 connects Pd34, source electrode Ns33 and connects the drain electrode Nd34 of the 34th NMOS tube；34th NMOS The grid Ng34 of pipe connects Pd30, drain electrode Nd34 and connects Ns33, source electrode Ns34 ground connection VSS.
As shown in Figure 8, output buffer has two inputs and an outfan, input connect s1 and S1r, outfan is Q.Output buffer is made up of two PMOS and two NMOS tube, and output is slow The substrate rushing all PMOS in circuit connects power vd D, the Substrate ground VSS of all NMOS tube. The grid Pg55 of the 55th PMOS connects s1r, drain electrode Pd55 and connects the 57th NMOS tube Drain electrode Nd57, source electrode Ps55 connect power vd D；The grid Pg56 of the 56th PMOS connects the The drain electrode Pd55 of 55 PMOS, drain electrode Pd56 connect the drain electrode Nd58 of the 58th NMOS tube, And connect power vd D as the output Q of inverter circuit, source electrode Ps56；57th NMOS tube Grid Ng57 connects s1, drain electrode Nd57 and connects the drain electrode Pd55 of the 55th PMOS；58th The grid Ng58 of NMOS tube connects the drain electrode Nd57 of the 57th NMOS tube, drain electrode Nd58 and connects the The drain electrode Pd56 of 56 PMOS, source electrode Ns58 connect VSS.
Beijing Institute of Atomic Energy's H-13 tandem accelerator can produce LET value and be respectively 2.88MeV·cm2/mg、8.62MeV·cm2/mg、12.6MeV·cm2/ mg and 17.0MeV cm2/mg Four kinds of ground heavy ion irradiation test environments.By resetted D unguyed for the tradition being in normal operating conditions Resetted d type flip flop, the resetted D of time sampling reinforcing that trigger, tradition duplication redundancy are reinforced trigger The primary particle inversion resistant D that resets that device, the Chinese patent of Application No. 201110323795.6 propose triggers The resetted d type flip flop of device and anti-single particle of the present invention upset and single-ion transient state connects identical 1000 respectively The outfan of level reverser chain also works with the clock frequency of 40MHz, and the input of 1000 grades of reverser chains is even Connect low level.Foregoing circuit is placed in the LET value point that Beijing Institute of Atomic Energy's H-13 tandem accelerator produces Wei 2.88MeV cm2/mg、8.62MeV·cm2/mg、12.6MeV·cm2/ mg and 21.3MeV cm2/mg Ground heavy ion irradiation test environment in, the D that respectively can reset during adding up the heavy ion irradiation of each LET touch Send out device make a mistake output number of times.The total fluence of heavy ion irradiation of every kind of LET is 107ion/cm2.Table 1 Ground heavy particle irradiation for using Beijing Institute of Atomic Energy's H-13 tandem accelerator to carry out tests the biography obtained Resetted d type flip flop that the resetted d type flip flop of uniting unguyed, tradition duplication redundancy are reinforced, time sampling The anti-single particle that the resetted d type flip flop of reinforcing, the Chinese patent of Application No. 201110323795.6 propose The resetted d type flip flop of upset and anti-single particle of the present invention overturn and the resetted d type flip flop of single-ion transient state It is respectively 2.88MeV cm in LET value2/mg、8.62MeV·cm2/mg、12.6MeV·cm2/mg With 21.3MeV cm2Make a mistake during the ground heavy ion irradiation of/mg the number of times exported.Every kind of LET The total fluence of heavy ion irradiation be 107ion/cm2.From the statistics of table 1 it can be seen that the anti-single particle of the present invention Upset and single-ion transient state ability are better than unguyed the resetted d type flip flop of tradition, time sampling is reinforced can Reset d type flip flop and the resetted d type flip flop of tradition duplication redundancy reinforcing, Application No. 201110323795.6 Chinese patent propose the primary particle inversion resistant d type flip flop that resets, be suitable for anti-single particle upset and Single-ion transient state reinforces the standard cell lib of integrated circuit, is applied to the fields such as Aeronautics and Astronautics.
Table 1

Claims (1)

1. anti-single particle upset and the resetted d type flip flop of single-ion transient state, including clock circuit, reset buffer circuit, main latch, from latch, output buffer, it is characterised in that anti-single particle upset and the resetted d type flip flop of single-ion transient state also include buffer circuits；Main latch and from latch be redundancy reinforce latch；Main latch and from latch tandem, and be all connected with clock circuit and reset buffer circuit；Main latch is also connected with buffer circuits, is also connected with output buffer from latch；There are three inputs and an outfan；Three inputs are clock signal input terminal CK, data signal input D and reset signal input RN respectively；Outfan is Q；
Described clock circuit has an input and four outfans, and input is CK, and outfan is c1, c2, cn1, cn2；Clock circuit is made up of 12 PMOS and 14 NMOS, and in circuit, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube；The grid Pg43 of the 43rd PMOS connects CK, drain electrode Pd43 and connects the drain electrode Nd43, source electrode Ps43 of the 43rd NMOS tube and connect power vd D；The grid Pg44 of the 44th PMOS connects the drain electrode Pd43 of the 43rd PMOS, drain electrode Pd44 and connects the drain electrode Nd44, source electrode Ps44 of the 44th NMOS tube and connect power vd D；The grid Pg45 of the 45th PMOS connects the drain electrode Pd44 of the 44th PMOS, drain electrode Pd45 and connects the drain electrode Nd45, source electrode Ps45 of the 45th NMOS tube and connect power vd D；The grid Pg46 of the 46th PMOS connects the drain electrode Pd45 of the 45th PMOS, drain electrode Pd46 and connects the drain electrode Nd46, source electrode Ps46 of the 46th NMOS tube and connect power vd D；The grid Pg47 of the 47th PMOS connects CK, drain electrode Pd47 and connects the source electrode Ps48, source electrode Ps47 of the 48th PMOS and connect VDD；The grid Pg48 of the 48th PMOS connects the drain electrode Pd46 of the 46th PMOS, drain electrode Pd48 and connects the drain electrode Nd47 of the 47th NMOS tube, and as an outfan cn1 of clock circuit；The grid Pg49 of the 49th PMOS connects CK, drain electrode Pd49 and connects the source electrode Ps50, source electrode Ps49 of the 50th PMOS and connect VDD；The grid Pg50 of the 50th PMOS connects the drain electrode Pd46 of the 46th PMOS, drain electrode Pd50 and connects the drain electrode Nd49 of the 49th NMOS tube, and as an outfan cn2 of clock circuit；The grid Pg51 of the 51st PMOS connects the drain electrode Pd48, source electrode Ps51 of the 48th PMOS connect VDD as an outfan c1 of clock circuit, drain electrode Pd51；The grid Pg52 of the 52nd PMOS connects the grid Ng53 of the 53rd NMOS tube and the outfan c2, drain electrode Pd52 as clock circuit connects the drain electrode Nd53 of the 53rd NMOS tube and be connected with outfan cn2, and source electrode Ps52 connects VDD；The grid Pg53 of the 53rd PMOS connects outfan cn1, drain electrode Pd53 and connects outfan c1, source electrode Ps53 and connect VDD；The grid Pg54 of the 54th PMOS connects outfan cn2, drain electrode Pd54 and connects outfan c2, source electrode Ps54 and connect VDD；The grid Ng43 of the 43rd NMOS tube connects CK, drain electrode Nd43 and connects the drain electrode Pd43 of the 43rd PMOS；The grid Ng44 of the 44th NMOS tube connects the drain electrode Nd43 of the 43rd NMOS tube, drain electrode Nd44 and connects the drain electrode Pd44, source electrode Ns44 of the 44th PMOS and connect VSS；The grid Ng45 of the 45th NMOS tube connects the drain electrode Nd44 of the 44th NMOS tube, drain electrode Nd45 and connects the drain electrode Pd45, source electrode Ns45 of the 45th PMOS and connect VSS；The grid Ng46 of the 46th NMOS tube connects the drain electrode Nd45 of the 45th NMOS tube, drain electrode Nd46 and connects the drain electrode Pd46, source electrode Ns46 of the 46th PMOS and connect VSS；The grid Ng47 of the 47th NMOS tube connects the drain electrode Nd48 of drain electrode Nd46, source electrode Ns47 connection the 48th NMOS tube of the 46th NMOS tube, and the drain electrode of the 47th NMOS tube connects cn1；The grid Ng48 of the 48th NMOS tube connects CK, drain electrode Nd48 and connects the source electrode Ns47, source electrode Ns48 of the 47th NMOS tube and connect VSS；The grid Ng49 of the 49th NMOS tube connects the drain electrode Nd50 of drain electrode Nd46, source electrode Ns49 connection the 50th NMOS tube of the 46th NMOS tube, and the drain electrode of the 49th NMOS tube connects cn2；The grid Ng50 of the 50th NMOS tube connects CK, drain electrode Nd50 and connects the source electrode Ns49, source electrode Ns50 of the 49th NMOS tube and connect VSS；The grid Ng51 of the 51st NMOS tube connects outfan c1, drain electrode Nd51 and connects outfan cn1, source electrode Ns51 and connect the drain electrode Nd52 of the 52nd NMOS tube；The grid Ng52 of the 52nd NMOS tube connects outfan c1, drain electrode Nd52 and connects the 51st NMOS tube source electrode Ns51, source electrode Ns52 and connect VSS；The grid Ng53 of the 53rd NMOS tube connects outfan c2, drain electrode Nd53 and connects outfan cn2, source electrode Ns53 connection the 54th NMOS tube drain electrode Nd54；The grid Ng54 of the 54th NMOS tube connects outfan c2, drain electrode Nd54 and connects the 53rd NMOS tube source electrode Ns53, source electrode Ns54 and connect VSS；The grid Ng55 of the 55th NMOS tube connects outfan cn1, drain electrode Nd55 and connects outfan c1, source electrode Ns55 and connect VSS；The grid Ng56 of the 56th NMOS tube connects outfan cn2, drain electrode Nd56 and connects outfan c2, source electrode Ns56 and connect VSS；
Described buffer circuits has an input and an outfan, and input is D, and outfan is D1；Buffer circuit is made up of eight PMOS and eight NMOS tube, and in buffer circuit, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube；The grid Pg1 of the first PMOS connects input D and the grid Ng1 with the first NMOS tube connects, and drain electrode Pd1 connects the drain electrode Ng1, source electrode Ps1 of the first NMOS tube and connects VDD；The grid Pg2 of the second PMOS connects the drain electrode Pd1 of the first PMOS, drain electrode Pd2 and connects the drain electrode Nd2, source electrode Ps2 of the second NMOS tube and connect VDD；The grid Pg3 of the 3rd PMOS connects the drain electrode Pd2 of the second PMOS, drain electrode Pd3 and connects the drain electrode Nd3, source electrode Ps3 of the 3rd NMOS tube and connect VDD；The grid Pg4 of the 4th PMOS connects the drain electrode Pd3 of the 3rd PMOS, drain electrode Pd4 and connects the drain electrode Nd4, source electrode Ps4 of the 4th NMOS tube and connect VDD；The grid Pg5 of the 5th PMOS connects the drain electrode Pd4 of the 4th PMOS pipe, drain electrode Pd5 and connects the drain electrode Nd5, source electrode Ps5 of the 5th NMOS tube and connect VDD；The grid Pg6 of the 6th PMOS connects the drain electrode Pd5 of the 5th PMOS, drain electrode Pd6 and connects the drain electrode Nd6, source electrode Ps6 of the 6th NMOS tube and connect VDD；The grid Pg7 of the 7th PMOS connects the drain electrode Pd6 of the 6th PMOS, drain electrode Pd7 and connects the drain electrode Nd7, source electrode Ps7 of the 7th NMOS tube and connect VDD；The grid Pg8 of the 8th PMOS connects the drain electrode Pd7 of the 7th PMOS, and drain electrode Pd8 connects the drain electrode Nd8 of the 8th NMOS tube and the output D1, source electrode Ps8 as buffer connects VDD；The grid Ng1 of the first NMOS tube connects Pg1, drain electrode Nd1 and connects Pd1, source electrode Ns1 and connect VSS；The grid Ng2 of the second NMOS tube connects the drain electrode Nd1 of the first NMOS tube, drain electrode Nd2 and connects Pd2, source electrode Ns2 and connect VSS；The grid Ng3 of the 3rd NMOS tube connects the drain electrode Nd2 of the second NMOS tube, drain electrode Nd3 and connects Pd3, source electrode Ns3 and connect VSS；The grid Ng4 of the 4th NMOS tube connects the drain electrode Nd3 of the 3rd NMOS tube, drain electrode Nd4 and connects Pd4, source electrode Ns4 and connect VSS；The grid Ng5 of the 5th NMOS tube connects the drain electrode Nd4 of the 4th NMOS tube, drain electrode Nd5 and connects Pd5, source electrode Ns5 and connect VSS；The grid Ng6 of the 6th NMOS tube connects the drain electrode Nd5 of the 5th NMOS tube, drain electrode Nd6 and connects Pd6, source electrode Ns6 and connect VSS；The grid Ng7 of the 7th NMOS tube connects the drain electrode Nd6 of the 6th NMOS tube, drain electrode Nd7 and connects Pd7, source electrode Ns7 and connect VSS；The grid Ng8 of the 8th NMOS tube connects the drain electrode Nd7 of the 7th NMOS tube, drain electrode Nd8 and connects Pd8, source electrode Ns8 and connect VSS；
Described reset buffer circuit has an input and two outfans, and input is RN, and outfan is _ RN1_, _ RN2_；Reset buffer circuit is made up of 8 NMOS tube and 8 PMOS, and in reset buffer circuit, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube；The grid Pg35 of the 35th PMOS connects RN, drain electrode Pd35 and connects the drain electrode Nd35, source electrode Ps35 of the 35th NMOS tube and connect power vd D；The grid Pg36 of the 36th PMOS connects the drain electrode Pd35 of the 35th PMOS, drain electrode Pd36 and connects the drain electrode Nd36, source electrode Ps36 of the 36th NMOS tube and connect power vd D；The grid Pg37 of the 37th PMOS connects the drain electrode Pd36 of the 36th PMOS, drain electrode Pd37 and connects the drain electrode Nd37, source electrode Ps37 of the 37th NMOS tube and connect power vd D；The grid Pg38 of the 38th PMOS connects the drain electrode Pd37 of the 37th PMOS, drain electrode Pd38 and connects the drain electrode Nd38, source electrode Ps38 of the 38th NMOS tube and connect power vd D；The grid Pg39 of the 39th PMOS connects RN, drain electrode Pd39 and connects the source electrode Ps40, source electrode Ps39 of the 40th PMOS and connect VDD；The grid Pg40 of the 40th PMOS connects the drain electrode Pd38 of the 38th PMOS, drain electrode Pd40 and connects the drain electrode Nd39 of the 39th NMOS tube, and the outfan _ RN1_, source electrode Ps40 as reset buffer circuit connects Pd39；The grid Pg41 of the 41st PMOS connects RN, drain electrode Pd41 and connects the source electrode Ps42, source electrode Ps41 of the 42nd PMOS and connect VDD；The grid Pg42 of the 42nd PMOS connects the drain electrode Pd38 of the 38th PMOS, drain electrode Pd42 and connects the drain electrode Nd41 of the 41st NMOS tube, and the outfan _ RN2_, source electrode Ps42 as reset buffer circuit connects Pd41；The grid Ng35 of the 35th NMOS tube connects RN, drain electrode Nd35 and connects the drain electrode Pd35, source electrode Ns35 of the 35th PMOS and connect VSS；The grid Ng36 of the 36th NMOS tube connects the drain electrode Nd35 of the 35th NMOS tube, drain electrode Nd36 and connects the drain electrode Pd36, source electrode Ns36 of the 36th PMOS and connect VSS；The grid Ng37 of the 37th NMOS tube connects the drain electrode Nd36 of the 36th NMOS tube, drain electrode Nd37 and connects the drain electrode Pd37, source electrode Ns37 of the 37th PMOS and connect VSS；The grid Ng38 of the 38th NMOS tube connects the drain electrode Nd37 of the 37th NMOS tube, drain electrode Nd38 and connects the drain electrode Pd38, source electrode Ns38 of the 38th PMOS and connect VSS；The grid Ng39 of the 39th NMOS tube connects the drain electrode Nd40 of drain electrode Nd38, source electrode Ns39 connection the 40th NMOS tube of the 38th NMOS tube, and drain Nd39 connection _ RN1_；The grid Ng40 of the 40th NMOS tube connects RN, drain electrode Nd40 and connects the source electrode Ns39, source electrode Ns40 of the 39th NMOS tube and connect VSS；The grid Ng41 of the 41st NMOS tube connects the drain electrode Nd42 of drain electrode Nd38, source electrode Ns41 connection the 42nd NMOS tube of the 38th NMOS tube, and drain Nd41 connection _ RN2_；The grid Ng42 of the 42nd NMOS tube connects RN, drain electrode Nd42 and connects the source electrode Ns41, source electrode Ns42 of the 41st NMOS tube and connect VSS；
Described main latch has eight inputs and two outfans, input and D, D1, c1, c2, cn1, cn2, and _ RN1_, _ RN2_ are connected；Outfan is m1, m1r；Main latch is made up of 14 PMOS and 14 NMOS, and in main latch, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube；The grid Pg9 of the 9th PMOS connects D, drain electrode Pd9 and connects the source electrode Ps10, source electrode Ps9 of the tenth PMOS and connect VDD；The grid Pg10 of the tenth PMOS connects D1, source electrode Ps10 and connects the drain electrode Pd9 of the 9th PMOS, the source electrode Ps11 of drain electrode Pd10 connection the 11st PMOS；The grid Pg11 of the 11st PMOS connects c1, source electrode Ps11 and connects the drain electrode Pd10 of the tenth PMOS, drain electrode Pd11 connection the 9th NMOS drain electrode Nd9；The source electrode Ps13, source electrode Ps12 of drain electrode connection the 13rd PMOS that the grid Pg12 of the 12nd PMOS connects D, the 12nd PMOS connect VDD；The grid Pg13 of the 13rd PMOS connects D1, source electrode Ps13 and connects the drain electrode Pd12 of the 12nd PMOS, the source electrode Ps14 of drain electrode Pd13 connection the 14th PMOS；The grid Pg14 of the 14th PMOS connects c2, source electrode Ps14 and connects the drain electrode Pd13 of the 13rd PMOS, drain electrode Pd14 connection the 12nd NMOS drain electrode Nd12；The grid Pg15 connection _ RN1_ of the 15th PMOS, drain electrode Pd15 connect the source electrode Ps16, source electrode Ps15 of the 16th PMOS and connect power vd D；The grid Pg16 of the 16th PMOS connects Pd11, and drain electrode Pd16 connects the drain electrode Nd15 of the 15th NMOS tube and the output m1, source electrode Ps16 as main latch connects Pd15；The grid Pg17 connection _ RN2_ of the 17th PMOS, drain electrode Pd17 connect Ps18, source electrode Ps17 and connect power vd D；The grid Pg18 of the 18th PMOS connects Pd14, drain electrode Pd18 and connects the drain electrode Nd17, source electrode Ps18 of the 17th NMOS tube and connect Pd17；The grid Pg19 of the 19th PMOS connects Pd18, drain electrode Pd19 and connects the source electrode Ps20, source electrode Ps19 of the 20th PMOS and connect power vd D；The grid Pg20 of the 20th PMOS connects cn1, drain electrode Pd20 and connects the drain electrode Nd19 and the 16th PMOS grid Pg16 of the 19th NMOS tube, and source electrode Ps20 connects Pd19；The grid Pg21 of the 21st PMOS connects Pd16, drain electrode Pd21 and connects the source electrode Ps22, source electrode Ps21 of the 22nd PMOS and connect power vd D；The grid Pg22 of the 22nd PMOS connects cn2, drain electrode Pd22 and connects the drain electrode Nd21 and the 18th PMOS grid Pg18 of the 21st NMOS tube, and source electrode Ps22 connects Pd21；The grid Ng9 of the 9th NMOS tube connects cn1, source electrode Ns9 and connects the drain electrode Nd10 of the tenth NMOS tube, the drain electrode Pd11 of drain electrode Nd9 connection the 11st PMOS；The grid Ng10 of the tenth NMOS tube connects D1, drain electrode Nd10 and connects the source electrode Ns9, source electrode Ns10 of the 9th NMOS tube and connect Nd11；The grid Ng11 of the 11st NMOS tube connects input D, drain electrode Nd11 and connects Ns10, source electrode Ns11 and connect VSS；The grid Ng12 of the 12nd NMOS tube connects cn2, source electrode Ns12 and connects the drain electrode Nd13 of the 13rd NMOS tube, the drain electrode Pd14 of drain electrode Nd12 connection the 14th PMOS；The grid Ng13 of the 13rd NMOS tube connects D1, drain electrode Nd13 and connects the source electrode Ns12, source electrode Ns13 of the 12nd NMOS tube and connect Nd14；The grid Ng14 of the 14th NMOS tube connects input D, drain electrode Nd14 and connects Ns13, source electrode Ns11 and connect VSS；The grid Ng15 of the 15th NMOS tube connects Pd14, drain electrode Nd15 and connects Pd16, source electrode Ns15 and connect VSS；The grid Ng16 connection _ RN2_ of the 16th NMOS tube, drain electrode Nd16 connect Pd16, source electrode Ns16 and connect VSS；The grid Ng17 of the 17th NMOS tube connects Pd11, drain electrode Nd17 and connects Pd18, source electrode Ns17 ground connection VSS；The grid Ng18 connection _ RN1_ of the 18th NMOS tube, drain electrode Nd18 connect Pd18 and connect VSS as main latch output m1r, source electrode Ns18；The grid Ng19 of the 19th NMOS tube connects c1, drain electrode Nd19 and connects Pd20, source electrode Ns19 and connect the drain electrode Nd20 of the 20th NMOS tube；The grid Ng20 of the 20th NMOS tube connects Pd16, drain electrode Nd20 and connects Ns19, source electrode Ns20 ground connection VSS；The grid Ng21 of the 21st NMOS tube connects c2, drain electrode Nd21 and connects Pd22, source electrode Ns21 and connect the drain electrode Nd22 of the 22nd NMOS tube；The grid Ng22 of the 22nd NMOS tube connects Pd18, drain electrode Nd22 and connects Ns21, source electrode Ns22 ground connection VSS；
Described have eight inputs and two outfans, input and c1, c2, cn1, cn2, m1, m1r from latch, and _ RN1_, _ RN2_ are connected；Outfan is s1, s1r；Being made up of 12 PMOS and 12 NMOS tube from latch, from latch, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube；The grid Pg23 of the 23rd PMOS connects m1r, drain electrode Pd23 and connects the source electrode Ps24, source electrode Ps23 of the 24th PMOS and connect power vd D；The grid Pg24 of the 24th PMOS connects cn1, drain electrode Pd24 and connects the drain electrode Nd23 of the 23rd NMOS tube, and the source electrode of the 24th PMOS connects Pd23；The grid Pg25 of the 25th PMOS connects m1, drain electrode Pd25 and connects the source electrode Ps26, source electrode Ps25 of the 26th PMOS and connect power vd D；The grid Pg26 of the 26th PMOS connects cn2, drain electrode Pd26 and connects the drain electrode Nd25 of the 25th NMOS tube, and the source electrode of the 26th PMOS connects Pd25；The grid Pg27 connection _ RN1_ of the 27th PMOS, drain electrode Pd27 connect the source electrode Ps28, source electrode Ps27 of the 28th PMOS and connect power vd D；The grid Pg28 of the 28th PMOS connects Pd24, and drain electrode Pd28 connects the drain electrode Nd27 of the 27th NMOS tube and the output s1, source electrode Ps28 as main latch connects Pd27；The grid Pg29 connection _ RN2_ of the 29th PMOS, drain electrode Pd29 connect the source electrode Ps30, source electrode Ps29 of the 30th PMOS and connect power vd D；The grid Pg30 of the 30th PMOS connects Pd26, drain electrode Pd30 and connects the drain electrode Nd29 of the 29th NMOS tube and connect Pd29 as from the output s1r of latch, source electrode Ps30；The grid Pg31 of the 31st PMOS connects Pd30, drain electrode Pd31 and connects the source electrode Ps32, source electrode Ps31 of the 32nd PMOS and connect power vd D；The grid Pg32 of the 32nd PMOS connects c1, drain electrode Pd32 and connects the drain electrode Nd31 and the 28th PMOS grid Pg28 of the 31st NMOS tube, and source electrode Ps32 connects Pd31；The grid Pg33 of the 33rd PMOS connects Pd28, drain electrode Pd33 and connects the source electrode Ps34, source electrode Ps33 of the 34th PMOS and connect power vd D；The grid Pg34 of the 34th PMOS connects c2, drain electrode Pd34 and connects the drain electrode Nd33 and the 30th PMOS grid Pg30 of the 33rd NMOS tube, and source electrode Ps34 connects Pd33；The grid Ng23 of the 23rd NMOS tube connects c1, drain electrode Nd23 and connects Pd24, source electrode Ns23 and connect the drain electrode Nd24 of the 24th NMOS tube；The grid Ng24 of the 24th NMOS tube connects m1, drain electrode Nd24 and connects Ns23, source electrode Ns24 ground connection VSS；The grid Ng25 of the 25th NMOS tube connects c2, drain electrode Nd25 and connects Pd26, source electrode Ns25 and connect the drain electrode Nd26 of the 26th NMOS tube；The grid Ng26 of the 26th NMOS tube connects m1r, drain electrode Nd26 and connects Ns25, source electrode Ns26 ground connection VSS；The grid Ng27 of the 27th NMOS tube connects Pd26, drain electrode Nd27 and connects Pd28, source electrode Ns27 and connect VSS；The grid Ng28 connection _ RN2_ of the 28th NMOS tube, drain electrode Nd28 connect Pd28, source electrode Ns28 and connect VSS；The grid Ng29 of the 29th NMOS tube connects Pd24, drain electrode Nd29 and connects Pd30, source electrode Ns29 and connect VSS；The grid Ng30 connection _ RN1_ of the 30th NMOS tube, drain electrode Nd30 connect Pd30, source electrode Ns30 and connect VSS；The grid Ng31 of the 31st NMOS tube connects cn1, drain electrode Nd31 and connects Pd32, source electrode Ns31 and connect the drain electrode Nd32 of the 32nd NMOS tube；The grid Ng32 of the 32nd NMOS tube connects Pd28, drain electrode Nd32 and connects Ns31, source electrode Ns32 ground connection VSS；The grid Ng33 of the 33rd NMOS tube connects cn2, drain electrode Nd33 and connects Pd34, source electrode Ns33 and connect the drain electrode Nd34 of the 34th NMOS tube；The grid Ng34 of the 34th NMOS tube connects Pd30, drain electrode Nd34 and connects Ns33, source electrode Ns34 ground connection VSS；
Described output buffer has two inputs and an outfan, and input connects s1 and s1r, and outfan is Q；Output buffer is made up of two PMOS and two NMOS tube, and in output buffer, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube；The grid Pg55 of the 55th PMOS connects s1r, drain electrode Pd55 and connects the drain electrode Nd57, source electrode Ps55 of the 57th NMOS tube and connect power vd D；The grid Pg56 of the 56th PMOS connects the drain electrode Pd55 of the 55th PMOS, drain electrode Pd56 and connects the drain electrode Nd58 of the 58th NMOS tube, and connect power vd D as the output Q of inverter circuit, source electrode Ps56；The grid Ng57 of the 57th NMOS tube connects s1, drain electrode Nd57 and connects the drain electrode Pd55 of the 55th PMOS；The grid Ng58 of the 58th NMOS tube connects the drain electrode Nd57 of the 57th NMOS tube, drain electrode Nd58 and connects the drain electrode Pd56, source electrode Ns58 of the 56th PMOS and connect VSS.
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