CN102394602A - Single event upset-resisting scanning structure D trigger capable of setting and resetting - Google Patents
Single event upset-resisting scanning structure D trigger capable of setting and resetting Download PDFInfo
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Abstract
The invention discloses a single event upset-resisting scanning structure D trigger capable of setting and resetting, which aims at improving the single event upset-resisting capability of the single event upset-resisting scanning structure D trigger. The trigger comprises a clock circuit, a scanning control buffer circuit, a resetting buffer circuit, a main latch, a slave latch and an output buffer circuit, wherein the main latch comprises twenty PMOS (P-channel metal oxide semiconductor) tubes and twenty NMOS (N-channel metal oxide semiconductor) tubes, the slave latch comprises ten PMOS tubes and ten NMOS tubes, double-die redundant strengthening is carried out on the main latch and the slave latch respectively, and a C2MOS circuit structure in the main latch is improved, namely upper pulling circuits and lower pulling circuits in the C2MOS circuits which are mutually redundant. The single event upset-resisting scanning structure D trigger has strong single event upset-resisting capability, suitable for a standard unit library of a single event upset-resisting strengthening integrated circuit, and applied to the fields of aviation, spaceflight and the like.
Description
Technical field
The present invention relates to a kind of principal and subordinate's d type flip flop that has setable and resetting structure and Scan Architecture, particularly a kind of anti-single particle overturn (signal event upset) setable with the Scan Architecture d type flip flop that resets.
Background technology
In the cosmic space, there are a large amount of high energy particles (proton, electronics, heavy ion) and charged particle.After integrated circuit receives the bombardment of these high energy particles and charged particle, can produce electronic impulse in the integrated circuit, the original level of IC interior node is overturn, this effect is called single-particle inversion (SEU).LET (linear energy transfer) value of single-particle bombardment integrated circuit is high more, and the electronic impulse of generation is strong more.The integrated circuit that uses in the Aeronautics and Astronautics field all can receive the threat of single-particle inversion, makes the integrated circuit job insecurity, even produces fatal mistake, and therefore exploitation advanced person's integrated circuit anti-single particle overturn reinforcement technique is particularly important.
The anti-single particle overturn reinforcement technique of integrated circuit can be divided into system-level reinforcing, circuit stages is reinforced and device level is reinforced.The IC reliability of system-level reinforcing is high, but chip area is big, power consumption is big, the speed of service is slow.The integrated circuit speed of service that device level is reinforced is fast, and chip area is little, low in energy consumption, but the device level reinforcing realizes that difficulty is big, and cost is high.The IC reliability that circuit stages is reinforced is high; Chip area, power consumption and the speed of service are superior to the integrated circuit of system-level reinforcing; And realizing the integrated circuit that difficulty and cost are reinforced less than device level, is crucial integrated circuit anti-single particle overturn reinforcement means.
D type flip flop is to use one of maximum unit in the sequential logical circuit, and its anti-single particle overturn ability has directly determined the anti-single particle overturn ability of integrated circuit.D type flip flop is carried out circuit stages reinforce the anti-single particle overturn ability that can under less chip area, power consumption and cost, improve integrated circuit effectively.
Traditional d type flip flop is principal and subordinate's d type flip flop, generally constitutes by the main latch with from the level series of latches, and it is the effective ways of realizing that the d type flip flop anti-single particle is reinforced that the anti-single particle overturn of latch is reinforced." the Upset Hardened Memory Design for Submicron CMOS Technology " that people such as T.Clain deliver on IEEE Transaction on Nuclear Science (IEEE atomic energy science journal) (memory cell design is reinforced in the upset under sub-micron CMOS technology) (roll up by the 6th phases 43 of December in 1996; The 2874th～2878 page) a kind of redundant latch of reinforcing proposed; This latch has increased an inverter and a feedback loop on the basis of classical latch structure, with original inverter and feedback loop redundant circuit each other.The input of N pipe separates with the input of P pipe in the inverter, connects two feedback loops respectively, C in the feedback loop
2The input that the N of MOS circuit pipe and P manage is respectively from the output of two inverters.The signal input and the signal of this latch are preserved by C
2The control of MOS clock circuit.The latch advantage that this redundancy is reinforced is: the upset level that produces when bombarding a node can return to original state through the correct level of corresponding node in its redundant circuit.The deficiency of the latch that this redundancy is reinforced is: two redundant each other C of input
2Draw PMOS pipe and a pull-down NMOS pipe on shared one of the MOS circuit, make C in the feedback loop
2There is an indirect path between the output node of MOS circuit and the redundant circuit corresponding node, when the single-particle bombardment makes this C
2The level upset of MOS circuit output node; Then this upset level can propagate into the corresponding node of redundant circuit along indirect path; If the LET value of single-particle bombardment is higher, then the level upset all can take place in two redundant each other circuit, and the output of latch is also overturn.The d type flip flop of the redundant reinforcing of forming by the redundant series of latches of reinforcing of two these kinds of tradition; When the LET value of single-particle bombardment higher; Then the level upset also all can take place in two redundant each other circuit, and the output of the redundant d type flip flop of reinforcing of tradition is also overturn." the The DF-DICE Storage Element for Immunity to Soft Errors " that people such as R.Naseer deliver on the 48th IEEE International Midwest Symposium on Circuits and Systems (the 48th IEEE circuit and system's Midwest international conference) (to DF-DICE memory cell of soft error immunity) also proposed the similarly latch of redundant reinforcing of a kind of and above-mentioned latch structure.Two C of this latch input
2The MOS circuit is fully independently, there is not indirect path in corresponding node in two redundant each other circuit, has overcome the weak point of the latch that redundancy that people such as T.Clain propose reinforces.But the latch that the redundancy that people such as R.Naseer propose is reinforced has used passgate structures in feedback loop, and when a node received the single-particle bombardment that upset takes place, its redundant circuit fed back to this node with correct level through transmission gate.Because the noise margin of passgate structures is lower, the signal feedback ability of feedback loop a little less than, when the LET value of single-particle bombardment was higher, feedback loop can not make this node recover correct level, has had a strong impact on this latch anti-single particle overturn ability.The d type flip flop of the redundant reinforcing of forming by the redundant series of latches of reinforcing of two these kinds of tradition; When the LET value of single-particle bombardment is higher; Also can be because of the passgate structures in the feedback loop; Can not make this node recover correct level, having influenced should the redundant d type flip flop anti-single particle overturn ability of reinforcing of tradition.
The patent No. is the d type flip flop that the Chinese patent of CN101499788A discloses a kind of anti-single particle overturn and single-particle transient pulse.This invention is the d type flip flop of a kind of similar in the time sampling structure, comprises two variable connectors, two delay circuits, two shutter circuit and three inverters, has realized that the anti-single particle overturn of d type flip flop is reinforced.Owing to adopt delay circuit and shutter circuit to shield the electronic impulse that bombardment produces; When the LET value of single-particle bombardment is higher; The electronic impulse width can be greater than the time of delay of delay circuit; The output level of shutter circuit is overturn, greatly reduce the anti-single particle overturn ability of this d type flip flop.
Common principal and subordinate's d type flip flop is unfavorable at test phase circuit being detected, and makes test job become very loaded down with trivial details, complicated.On common principal and subordinate's d type flip flop architecture basics, add Scan Architecture, can simplify circuit test work effectively, promptly can control the input of principal and subordinate's d type flip flop through sweep signal at test phase, and then the control circuit state.
Some integrated circuit needs the state of d type flip flop in the control integrated circuit, forces d type flip flop output high level or low level and is changed to logical one or logical zero to latched data wherein.On the original architecture basics of d type flip flop, increase set and reset circuit and asserts signal end and reset signal end, can realize the set and the resetting structure of d type flip flop self, and control the set and the reset function of d type flip flop through set and reset signal.But at present setable all not high with Scan Architecture d type flip flop anti-single particle overturn ability that reset, be unfavorable in the IC chip in fields such as Aeronautics and Astronautics, using.
Summary of the invention
The technical problem that the present invention will solve is; Setable to present anti-single particle overturn and reset the not high problem of Scan Architecture d type flip flop anti-single particle overturn ability; Propose a kind of anti-single particle overturn setable with the Scan Architecture d type flip flop that resets, operate as normal under it can bombard at the single-particle of higher LET value and do not produce single-particle inversion.
A kind of anti-single particle overturn that the present invention proposes setable with the Scan Architecture d type flip flop that resets by clock circuit, scan control buffer circuit, the buffer circuit that resets, main latch, form from latch and output buffer.
A kind of anti-single particle overturn of the present invention is setable to have six inputs and an output with Scan Architecture d type flip flop that reset.Six inputs are respectively that CK is that clock signal input part, D are that data-signal input, SE are that scan control signal input, SI are that scan data input terminal, SN are asserts signal input and RN reset signal input; An output is that Q is the data output signal end.
Clock circuit has an input and two outputs, and input is CK, and output is C, CN.Clock circuit is a two-stage inverter, is made up of first order inverter and second level inverter; First order inverter is made up of PMOS pipe and NMOS pipe, and the grid Pg1 of PMOS pipe connects CK, and the Pd1 that drains connects the drain electrode Nd1 that a NMOS manages, and as an output CN of clock circuit.The grid Ng1 of the one NMOS pipe connects CK, and drain electrode Nd1 connects Pd1; Second level inverter is made up of the 2nd PMOS pipe and the 2nd NMOS pipe, and the grid Pg2 of the 2nd PMOS pipe connects CN, and the Pd2 that drains connects the drain electrode Nd2 that the 2nd NMOS manages, and as another output C of clock circuit.The grid Ng2 of the 2nd NMOS pipe connects CN, and drain electrode Nd2 connects Pd2.The one PMOS pipe is connected power vd D with the substrate of the 2nd PMOS pipe, and source electrode Ps1, Ps2 connect power vd D; The substrate ground connection VSS of the one NMOS pipe and the 2nd NMOS pipe, source electrode Ns1, Ns2 be ground connection VSS also.
The scan control buffer circuit has an input and an output, and input is SE, and output is SEN.The scan control buffer circuit is made up of the 3rd PMOS pipe and the 3rd NMOS pipe.The substrate of the 3rd PMOS pipe all is connected power vd D with source electrode Ps3, the substrate and the equal ground connection VSS of source electrode Ns3 of the 3rd NMOS pipe.The grid Pg3 of the 3rd PMOS pipe connects SE, and drain electrode Pd3 connects the drain electrode Nd3 of the 3rd NMOS pipe, and as the output SEN of scan control circuit; The grid Ng3 of the 3rd NMOS pipe connects SE, and drain electrode Nd3 connects Pd3.
The buffer circuit that resets has an input and an output, and input is RN, and output is R.The buffer circuit that resets is an one-level inverter; Form by the 41 PMOS pipe and the 41 NMOS pipe; The grid Pg41 of the 41 PMOS pipe connects RN; Drain electrode Pd41 connects the drain electrode Nd41 of the 41 NMOS pipe also as the output R of the buffer circuit that resets, and source electrode Ps41 connects power vd D; The 41 NMOS tube grid Ng41 connects RN, and drain electrode Nd41 connects Pd41, source electrode Ns41 ground connection VSS.
Main latch and be the redundant latch of reinforcing from latch, and also comprise Scan Architecture in the main latch.Main latch and series connection before and after the latch, and all be connected with the buffer circuit that resets with clock circuit.Main latch also is connected with the scanning buffer control circuit, is connected with output buffer from latch.
Main latch has eight inputs and an output, and eight inputs are D, C, CN, SE, SEN, SI, SN, R, and an output is MO.Main latch is made up of 20 PMOS pipes and 20 NMOS pipes, and the substrate of all PMOS pipes connects power vd D in the main latch, the substrate ground connection VSS of all NMOS pipes.The grid Pg4 of the 4th PMOS pipe connects SI, and drain electrode Pd4 connects the source electrode Ps5 of the 5th PMOS pipe, and source electrode Ps4 connects power vd D; The grid Pg5 of the 5th PMOS pipe connects SEN, and drain electrode Pd5 connects the source electrode Ps8 of the 8th PMOS pipe, and source electrode Ps5 connects Pd4; The grid Pg6 of the 6th PMOS pipe connects SE, and drain electrode Pd6 connects the source electrode Ps7 of the 7th PMOS pipe, and source electrode Ps6 connects power vd D; The grid Pg7 of the 7th PMOS pipe connects D, and drain electrode Pd7 connects Ps8, and source electrode Ps7 connects Pd6; The grid Pg8 of the 8th PMOS pipe connects C, and drain electrode Pd8 connects the drain electrode Nd4 of the 4th NMOS pipe, and source electrode Ps8 connects Pd5; The grid Pg9 of the 9th PMOS pipe connects SI, and drain electrode Pd9 connects the source electrode Ps10 of the tenth PMOS pipe, and source electrode Ps9 connects power vd D; The grid Pg10 of the tenth PMOS pipe connects SEN, and drain electrode Pd10 connects the source electrode Ps13 of the 13 PMOS pipe, and source electrode Ps10 connects Pd9; The grid Pg11 of the 11 PMOS pipe connects SE, and drain electrode Pd11 connects the source electrode Ps12 of the 12 PMOS pipe, and source electrode Ps11 connects power vd D; The grid Pg12 of the 12 PMOS pipe connects D, and drain electrode Pd12 connects Ps13, and source electrode Ps12 connects Pd11; The grid Pg13 of the 13 PMOS pipe connects C, and drain electrode Pd13 connects the drain electrode Nd9 of the 9th NMOS pipe, and source electrode Ps13 connects Pd10; The grid Pg14 of the 14 PMOS pipe connects R, and drain electrode Pd14 connects the source electrode Ps15 of the 15 PMOS pipe, and source electrode Ps14 connects power vd D; The grid Pg15 of the 15 PMOS pipe connects Pd8, and drain electrode Pd15 connects the drain electrode Nd14 of the 14 NMOS pipe and as the output MO of main latch, source electrode Ps15 connects Pd14; The grid Pg16 of the 16 PMOS pipe connects SN, and drain electrode Pd16 connects Pd15, and source electrode Ps16 connects power vd D; The grid Pg17 of the 17 PMOS pipe connects R, and drain electrode Pd17 connects the source electrode Ps18 of the 18 PMOS pipe, and source electrode Ps17 connects power vd D; The grid Pg18 of the 18 PMOS pipe connects Pd13, and drain electrode Pd18 connects the drain electrode Nd17 of the 17 NMOS pipe, and source electrode Ps18 connects Pd17; The grid Pg19 of the 19 PMOS pipe connects SN, and drain electrode Pd19 connects Pd18, and source electrode Ps19 connects power vd D; The grid Pg20 of the 20 PMOS pipe connects Pd18, and drain electrode Pd20 connects the source electrode Ps21 of the 21 PMOS pipe, and source electrode Ps20 connects power vd D; The grid Pg21 of the 21 PMOS pipe connects CN, and drain electrode Pd21 connects the drain electrode Nd20 of the 20 NMOS pipe, and source electrode Ps21 connects Pd20; The grid Pg22 of the 22 PMOS pipe connects Pd15, and drain electrode Pd22 connects the source electrode Ps23 of the 23 PMOS pipe, and source electrode Ps22 connects power vd D; The grid Pg23 of the 23 PMOS pipe connects CN, and drain electrode Pd23 connects the drain electrode Nd22 of the 22 NMOS pipe, and source electrode Ps23 connects Pd22; The grid Ng4 of the 4th NMOS pipe connects CN, and drain electrode Nd4 connects Pd8, and source electrode Ns4 connects the drain electrode Nd5 of the 5th NMOS pipe; The grid Ng5 of the 5th NMOS pipe connects SE, and drain electrode Nd5 connects Ns4, and source electrode Ns5 connects the drain electrode Nd6 of the 6th NMOS pipe; The grid Ng6 of the 6th NMOS pipe connects SI, and drain electrode Nd6 connects Ns5, source electrode Ns6 ground connection VSS; The grid Ng7 of the 7th NMOS pipe connects D, and drain electrode Nd7 connects Ns4, and source electrode Ns7 connects the drain electrode Nd8 of the 8th NMOS pipe; The grid Ng8 of the 8th NMOS pipe connects SEN, and drain electrode Nd8 connects Ns7, source electrode Ns8 ground connection VSS; The grid Ng9 of the 9th NMOS pipe connects CN, and drain electrode Nd9 connects Pd13, and source electrode Ns9 connects the drain electrode Nd10 of the tenth NMOS pipe; The grid Ng10 of the tenth NMOS pipe connects SE, and drain electrode Nd10 connects Ns9, and source electrode Ns10 connects the drain electrode Nd11 of the 11 NMOS pipe; The grid Ng11 of the 11 NMOS pipe connects SI, and drain electrode Nd11 connects Ns10, source electrode Ns11 ground connection VSS; The grid Ng12 of the 12 NMOS pipe connects D, and drain electrode Nd12 connects Ns9, and source electrode Ns12 connects the drain electrode Nd13 of the 13 NMOS pipe; The grid Ng13 of the 13 NMOS pipe connects SEN, and drain electrode Nd13 connects Ns12, source electrode Ns13 ground connection VSS; The grid Ng14 of the 14 NMOS pipe connects Pd13, and drain electrode Nd14 connects Pd15, and source electrode Ns14 connects the drain electrode Nd16 of the 16 NMOS pipe; The grid Ng15 of the 15 NMOS pipe connects R, and drain electrode Nd15 connects Pd15, and source electrode Ns15 connects Nd16; The grid Ng16 of the 16 NMOS pipe connects SN, and drain electrode Nd16 connects Ns14, source electrode Ns16 ground connection VSS; The grid Ng17 of the 17 NMOS pipe connects Pd8, and drain electrode Nd17 connects Pd18, and source electrode Ns17 connects the drain electrode Nd19 of the 19 NMOS pipe; The grid Ng18 of the 18 NMOS pipe connects R, and drain electrode Nd18 connects Pd18, and source electrode Ns18 connects Nd19; The grid Ng19 of the 19 NMOS pipe connects SN, and drain electrode Nd19 connects Ns17, source electrode Ns19 ground connection VSS; The grid Ng20 of the 20 NMOS pipe connects C, and drain electrode Nd20 connects Pd21, and source electrode Ns20 connects the drain electrode Nd21 of the 21 NMOS pipe; The grid Ng21 of the 21 NMOS pipe connects Pd15, and drain electrode Nd21 connects Ns20, source electrode Ns21 ground connection VSS; The grid Ng22 of the 22 NMOS pipe connects C, and drain electrode Nd22 connects Pd23, and source electrode Ns22 connects the drain electrode Nd23 of the 23 NMOS pipe; The grid Ng23 of the 23 NMOS pipe connects Pd18, and drain electrode Nd23 connects Ns22, source electrode Ns23 ground connection VSS.The 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe and the 5th NMOS pipe, the 6th NMOS pipe, the 8th NMOS pipe are formed the Scan Architecture in the main latch.
From latch five inputs and an output are arranged, five inputs are MO, C, CN, SN, R, and an output is SO.Be made up of 14 PMOS pipes and ten four NMOS pipes from latch, the substrate of all PMOS pipes connects power vd D from latch, the substrate ground connection VSS of all NMOS pipes.The grid Pg24 of the 24 PMOS pipe connects MO, and drain electrode Pd24 connects the source electrode Nd24 of the 24 NMOS pipe, and source electrode Ps24 connects power vd D; The grid Pg25 of the 25 PMOS pipe connects CN, and drain electrode Pd25 connects the source electrode Ns25 of the 25 NMOS pipe, and source electrode Ps25 connects Pd24; The grid Pg26 of the 26 PMOS pipe connects MO, and drain electrode Pd26 connects the drain electrode Nd26 of the 26 NMOS pipe, and source electrode Ps26 connects power vd D; The grid Pg27 of the 27 PMOS pipe connects CN, and drain electrode Pd27 connects the source electrode Ns27 of the 27 NMOS pipe, and source electrode Ps27 connects Pd26; The grid Pg28 of the 28 PMOS pipe connects R, and drain electrode Pd28 connects the source electrode Ps29 of the 29 PMOS pipe, and source electrode Ps28 connects power vd D; The grid Pg29 of the 29 PMOS pipe connects Pd27, and drain electrode Pd29 connects the drain electrode Nd28 of the 28 NMOS pipe and as the output SO from latch, source electrode Ps29 connects Pd28; The grid Pg30 of the 30 PMOS pipe connects SN, and drain electrode Pd30 connects the drain electrode Nd29 of the 29 NMOS pipe, and source electrode Ps30 connects power vd D; The grid Pg31 of the 31 PMOS pipe connects R, and drain electrode Pd31 connects the source electrode Ps32 of the 32 PMOS pipe, and source electrode Ps31 connects power vd D; The grid Pg32 of the 32 PMOS pipe connects Pd25, and drain electrode Pd32 connects the drain electrode Nd31 of the 31 NMOS pipe, and source electrode Ps32 connects Pd31; The grid Pg33 of the 33 PMOS pipe connects SN, and drain electrode Pd33 connects Pd32, and source electrode Ps33 connects power vd D; The grid Pg34 of the 34 PMOS pipe connects Pd32, and drain electrode Pd34 connects the source electrode Ps35 of the 35 PMOS pipe, and source electrode Ps34 connects power vd D; The grid Pg35 of the 35 PMOS pipe connects C, and drain electrode Pd35 connects the drain electrode Nd34 of the 34 NMOS pipe, and source electrode Ps35 connects Pd34; The grid Pg36 of the 36 PMOS pipe connects Pd29, and drain electrode Pd36 connects the source electrode Ps37 of the 37 PMOS pipe, and source electrode Ps36 connects power vd D; The grid Pg37 of the 37 PMOS pipe connects C, and drain electrode Pd37 connects the drain electrode Nd36 of the 36 NMOS pipe, and source electrode Ps37 connects Pd36; The grid Ng24 of the 24 NMOS pipe connects MO, and drain electrode Nd24 connects Pd24, source electrode Ns24 ground connection VSS; The grid Ng25 of the 25 NMOS pipe connects C, and drain electrode Nd25 connects Pd24, and source electrode Ns25 connects Pd25; The grid Ng26 of the 26 NMOS pipe connects MO, and drain electrode Nd26 connects Pd26, source electrode Ns26 ground connection VSS; The grid Ng27 of the 27 NMOS pipe connects C, and drain electrode Nd27 connects Pd26, and source electrode Ns27 connects Pd27; The grid Ng28 of the 28 NMOS pipe connects Pd25, and drain electrode Nd28 connects Pd29, and source electrode Ns28 connects the drain electrode Nd30 of the 30 NMOS pipe; The grid Ng29 of the 29 NMOS pipe connects R, and drain electrode Nd29 connects Pd29, and source electrode Ns29 connects Nd30; The grid Ng30 of the 30 NMOS pipe connects SN, and drain electrode Nd30 connects Ns28, source electrode Ns30 ground connection VSS; The grid Ng31 of the 31 NMOS pipe connects Pd27, and drain electrode Nd31 connects Pd32, and source electrode Ns31 connects the drain electrode Nd33 of the 33 NMOS pipe; The grid Ng32 of the 32 NMOS pipe connects R, and drain electrode Nd32 connects Pd32, and source electrode Ns32 connects Nd33; The grid Ng33 of the 33 NMOS pipe connects SN, and drain electrode Nd33 connects Ns31, source electrode Ns33 ground connection VSS; The grid Ng34 of the 34 NMOS pipe connects CN, and drain electrode Nd34 connects Pd35, and source electrode Ns34 connects the drain electrode Nd35 of the 35 NMOS pipe; The grid Ng35 of the 35 NMOS pipe connects Pd29, and drain electrode Nd35 connects Ns34, source electrode Ns35 ground connection VSS; The grid Ng36 of the 36 NMOS pipe connects CN, and drain electrode Nd36 connects Pd37, and source electrode Ns36 connects the drain electrode Nd37 of the 37 NMOS pipe; The grid Ng37 of the 37 NMOS pipe connects Pd32, and drain electrode Nd37 connects Ns36, source electrode Ns37 ground connection VSS.
Output buffer has three inputs and an output, and three inputs are SO, R, SN, and an output is Q.Output buffer comprises three PMOS pipes and three NMOS pipes, and the substrate of all PMOS pipes connects power vd D in the output buffer, the substrate ground connection VSS of all NMOS pipes.The grid Pg38 of the 38 PMOS pipe connects R, and drain electrode Pd38 connects the source electrode Ps39 of the 39 PMOS pipe, and source electrode Ps38 connects power vd D; The grid Pg39 of the 39 PMOS pipe connects SO, and drain electrode Pd39 connects the drain electrode Nd38 of the 38 NMOS pipe and as buffer circuit output Q, source electrode Ps39 connects Pd38; The grid Pg40 of the 40 PMOS pipe connects SN, and drain electrode Pd40 connects Pd39, and source electrode Ps40 connects power vd D; The grid Ng38 of the 38 NMOS pipe connects SO, and drain electrode Nd38 connects Pd39, and source electrode Ns38 connects the drain electrode Nd40 of the 40 NMOS pipe; The grid Ng39 of the 39 NMOS pipe connects R, and drain electrode Nd39 connects Pd39, and source electrode Ns39 connects Ns38; The grid Ng40 of the 40 NMOS pipe connects SN, and drain electrode Nd40 connects Ns38, source electrode Ns40 ground connection VSS.
A kind of anti-single particle overturn of the present invention is setable following with the Scan Architecture d type flip flop course of work that reset:
A kind of anti-single particle overturn of the present invention is setable also can to get into reset mode and SM set mode with Scan Architecture d type flip flop that reset the time marquis who is in scanning mode.A kind of anti-single particle overturn of the present invention is setable can to carry out set at any time and resets with Scan Architecture d type flip flop that reset, and set and reset function are that asserts signal input and RN are that the reset signal input is controlled jointly by SN.
When SN be low level, RN be any level, when SE is any level; A kind of anti-single particle overturn of the present invention is setable all to get into SM set mode with Scan Architecture d type flip flop that reset; Be main latch and from latch all by latching logic " 1 " by force, the output Q of output buffer is a high level.
When SN be high level, RN be low level, when SE is any level; A kind of anti-single particle overturn of the present invention is setable to get into reset mode with the Scan Architecture d type flip flop that resets; Be main latch and from latch all by latching logic " 0 " by force, the output Q of output buffer is a low level.
When SN be high level, RN be high level, when SE is low level; A kind of anti-single particle overturn of the present invention is setable to be in normal operating conditions with Scan Architecture d type flip flop that reset; Be that the clock circuit receives CK; Produce respectively after CK cushioned with the CN of CK anti-phase and with the C of CK homophase, and CN with C imports main latch into and from latch.At CK is between low period; CN is that high level, C are low level, and main latch is opened, and receives D and it is carried out the MO of output and D homophase after the buffered; Be in preservation state from latch, do not receive the MO of main latch output but preserve the MO that a CK trailing edge samples; At CK is between high period; CN is that low level, C are high level, and main latch is in preservation state, preserves the MO of D that previous CK rising edge samples and output and D homophase; From the output MO of latch unlatching and reception main latch, MO is carried out the SO of buffered and output and MO homophase.Output buffer all will receive the output SO from latch at any time, to the Q of SO buffering and output and SO homophase.
When SN be high level, RN be high level, when SE is high level; A kind of anti-single particle overturn of the present invention is setable to be in the scanning work state with Scan Architecture d type flip flop that reset; Be that the clock circuit receives CK; Produce respectively after CK cushioned with the CN of CK anti-phase and with the C of CK homophase, and CN with C imports main latch into and from latch.At CK is between low period; CN is that high level, C are low level, and main latch is opened, and receives SI and it is carried out the MO of output and SI homophase after the buffered; Be in preservation state from latch, do not receive the MO of main latch output but preserve the MO that a CK trailing edge samples; At CK is between high period; CN is that low level, C are high level, and main latch is in preservation state, preserves the MO of SI that previous CK rising edge samples and output and SI homophase; From the output MO of latch unlatching and reception main latch, MO is carried out the SO of buffered and output and MO homophase.Output buffer all will receive the output SO from latch at any time, to the Q of SO buffering and output and SO homophase.
Adopt the present invention can reach following technique effect:
The setable anti-single particle overturn ability with the Scan Architecture d type flip flop that resets of a kind of anti-single particle overturn of the present invention is superior to tradition unguyed Scan Architecture d type flip flop, time sampling setable and that reset and reinforces Scan Architecture d type flip flop and traditional redundant Scan Architecture d type flip flop setable and that reset of reinforcing setable and that reset.Because the present invention transforms tradition unguyed setable and Scan Architecture d type flip flop structure that reset, all carried out the duplication redundancy reinforcing to main latch with from latch, and to C in the main latch
2The MOS circuit structure improves, and promptly separates redundant each other C
2Pull-up circuit in the MOS circuit and pull-down circuit have further improved the setable anti-single particle overturn ability with the Scan Architecture d type flip flop that resets of the present invention a kind of anti-single particle overturn.A kind of anti-single particle overturn of the present invention is setable to be suitable for the standard cell lib that anti-single particle overturn is reinforced integrated circuit with Scan Architecture d type flip flop that reset, is applied to fields such as Aeronautics and Astronautics.
Description of drawings
Fig. 1 is the Scan Architecture d type flip flop logical construction sketch map that a kind of anti-single particle overturn of the present invention is setable and reset.
Fig. 2 for a kind of anti-single particle overturn of the present invention setable with the Scan Architecture d type flip flop that resets in the clock circuit structural representation.
Fig. 3 for a kind of anti-single particle overturn of the present invention setable with the Scan Architecture d type flip flop that resets in scan control buffer circuit structural representation.
Fig. 4 for a kind of anti-single particle overturn of the present invention setable with the Scan Architecture d type flip flop that resets in the buffer circuit structural representation that resets.
Fig. 5 for a kind of anti-single particle overturn of the present invention setable with the Scan Architecture d type flip flop that resets in the main latch structural representation.
Fig. 6 for a kind of anti-single particle overturn of the present invention setable with the Scan Architecture d type flip flop that resets in from the latch structure sketch map.
Fig. 7 for a kind of anti-single particle overturn of the present invention setable with the Scan Architecture d type flip flop that resets in the output buffer structural representation.
Embodiment
Fig. 1 is the Scan Architecture d type flip flop logical construction sketch map that a kind of anti-single particle overturn of the present invention is setable and reset.The present invention is by clock circuit (as shown in Figure 2), scan control buffer circuit (as shown in Figure 3), the buffer circuit that resets (as shown in Figure 4), main latch (as shown in Figure 5), form from latch (as shown in Figure 6) and output buffer (as shown in Figure 7).The present invention has six inputs and an output.Two inputs are respectively that CK is that clock signal input part, D are that data-signal input, SE are that scan control signal input, SI are that scan data input terminal, SN are asserts signal input and RN reset signal input; An output is that Q is the data output signal end.Clock circuit receives CK, and CK is carried out exporting C and CN respectively after the buffered.The scan control buffer circuit cushions SE, the input and the SEN of SE anti-phase, and import SEN in the main latch into.The buffer circuit that resets cushions RN, the input and the R of RN anti-phase, and import R into main latch and from latch.Main latch receives D, C, CN, SE, SEN, SI, R, SN, and main latch latchs etc. D or SI under the control of C, CN, SE, SEN, R, SN and handles back output MO.Receive MO, C, CN, R and SN from latch, exporting SO respectively after to processing such as MO latch under the control of C, CN, R and SN from latch.Output buffer receives SO, to processing back output Q such as it cushion.SN be high level, RN be high level, when SE is low level, a kind of anti-single particle overturn of the present invention setable with Scan Architecture d type flip flop that reset is in normal operating conditions; SN be high level, RN be high level, when SE is high level, a kind of anti-single particle overturn of the present invention setable with Scan Architecture d type flip flop that reset is in the scanning work state; SN is high level, when RN is low level, a kind of anti-single particle overturn of the present invention is setable to get into reset mode with the Scan Architecture d type flip flop that resets.SN is low level, when RN is high level or low level, a kind of anti-single particle overturn of the present invention is setable all to get into SM set mode with Scan Architecture d type flip flop that reset.
As shown in Figure 2, clock circuit has an input and two outputs, and input is CK, and output is C, CN.Clock circuit is a two-stage inverter, and first order inverter is made up of PMOS pipe and NMOS pipe, and the grid Pg1 of PMOS pipe connects CK, and the Pd1 that drains connects the drain electrode Nd1 that a NMOS manages, and as an output CN of clock circuit.The grid Ng1 of the one NMOS pipe connects CK, and drain electrode Nd1 connects Pd1; Second level inverter is made up of the 2nd PMOS pipe and the 2nd NMOS pipe, and the grid Pg2 of the 2nd PMOS pipe connects CN, and the Pd2 that drains connects the drain electrode Nd2 that the 2nd NMOS manages, and as another output C of clock circuit.The grid Ng2 of the 2nd NMOS pipe connects CN, and drain electrode Nd2 connects Pd2.The one PMOS pipe is connected power vd D with the substrate of the 2nd PMOS pipe, and source electrode Ps1, Ps2 connect power vd D; The substrate ground connection VSS of the one NMOS pipe and the 2nd NMOS pipe, source electrode Ns1, Ns2 be ground connection VSS also.
As shown in Figure 3, the scan control buffer circuit has an input and an output, and input is SE, and output is SEN.The scan control buffer circuit is made up of the 3rd PMOS pipe and the 3rd NMOS pipe.The substrate of the 3rd PMOS pipe all is connected power vd D with source electrode Ps3, the substrate and the equal ground connection VSS of source electrode Ns3 of the 3rd NMOS pipe.The grid Pg3 of the 3rd PMOS pipe connects SE, and drain electrode Pd3 connects the drain electrode Nd3 of the 3rd NMOS pipe, and as the output SEN of scan control circuit; The grid Ng3 of the 3rd NMOS pipe connects SE, and drain electrode Nd3 connects Pd3.
As shown in Figure 4, the buffer circuit that resets has an input and an output, and input is RN, and output is R.The buffer circuit that resets is an one-level inverter; Form by the 41 PMOS pipe and the 41 NMOS pipe; The grid Pg41 of the 41 PMOS pipe connects RN; Drain electrode Pd41 connects the drain electrode Nd41 of the 41 NMOS pipe also as the output R of the buffer circuit that resets, and source electrode Ps41 connects power vd D; The 41 NMOS tube grid Ng41 connects RN, and drain electrode Nd41 connects Pd41, source electrode Ns41 ground connection VSS.
As shown in Figure 5, main latch has eight inputs and an output, and eight inputs are D, C, CN, SE, SEN, SI, SN, R, and an output is MO.Main latch is made up of 20 PMOS pipes and 20 NMOS pipes, and the substrate of all PMOS pipes connects power vd D in the main latch, the substrate ground connection VSS of all NMOS pipes.The grid Pg4 of the 4th PMOS pipe connects SI, and drain electrode Pd4 connects the source electrode Ps5 of the 5th PMOS pipe, and source electrode Ps4 connects power vd D; The grid Pg5 of the 5th PMOS pipe connects SEN, and drain electrode Pd5 connects the source electrode Ps8 of the 8th PMOS pipe, and source electrode Ps5 connects Pd4; The grid Pg6 of the 6th PMOS pipe connects SE, and drain electrode Pd6 connects the source electrode Ps7 of the 7th PMOS pipe, and source electrode Ps6 connects power vd D; The grid Pg7 of the 7th PMOS pipe connects D, and drain electrode Pd7 connects Ps8, and source electrode Ps7 connects Pd6; The grid Pg8 of the 8th PMOS pipe connects C, and drain electrode Pd8 connects the drain electrode Nd4 of the 4th NMOS pipe, and source electrode Ps8 connects Pd5; The grid Pg9 of the 9th PMOS pipe connects SI, and drain electrode Pd9 connects the source electrode Ps10 of the tenth PMOS pipe, and source electrode Ps9 connects power vd D; The grid Pg10 of the tenth PMOS pipe connects SEN, and drain electrode Pd10 connects the source electrode Ps13 of the 13 PMOS pipe, and source electrode Ps10 connects Pd9; The grid Pg11 of the 11 PMOS pipe connects SE, and drain electrode Pd11 connects the source electrode Ps12 of the 12 PMOS pipe, and source electrode Ps11 connects power vd D; The grid Pg12 of the 12 PMOS pipe connects D, and drain electrode Pd12 connects Ps13, and source electrode Ps12 connects Pd11; The grid Pg13 of the 13 PMOS pipe connects C, and drain electrode Pd13 connects the drain electrode Nd9 of the 9th NMOS pipe, and source electrode Ps13 connects Pd10; The grid Pg14 of the 14 PMOS pipe connects R, and drain electrode Pd14 connects the source electrode Ps15 of the 15 PMOS pipe, and source electrode Ps14 connects power vd D; The grid Pg15 of the 15 PMOS pipe connects Pd8, and drain electrode Pd15 connects the drain electrode Nd14 of the 14 NMOS pipe and as the output MO of main latch, source electrode Ps15 connects Pd14; The grid Pg16 of the 16 PMOS pipe connects SN, and drain electrode Pd16 connects Pd15, and source electrode Ps16 connects power vd D; The grid Pg17 of the 17 PMOS pipe connects R, and drain electrode Pd17 connects the source electrode Ps18 of the 18 PMOS pipe, and source electrode Ps17 connects power vd D; The grid Pg18 of the 18 PMOS pipe connects Pd13, and drain electrode Pd18 connects the drain electrode Nd17 of the 17 NMOS pipe, and source electrode Ps18 connects Pd17; The grid Pg19 of the 19 PMOS pipe connects SN, and drain electrode Pd19 connects Pd18, and source electrode Ps19 connects power vd D; The grid Pg20 of the 20 PMOS pipe connects Pd18, and drain electrode Pd20 connects the source electrode Ps21 of the 21 PMOS pipe, and source electrode Ps20 connects power vd D; The grid Pg21 of the 21 PMOS pipe connects CN, and drain electrode Pd21 connects the drain electrode Nd20 of the 20 NMOS pipe, and source electrode Ps21 connects Pd20; The grid Pg22 of the 22 PMOS pipe connects Pd15, and drain electrode Pd22 connects the source electrode Ps23 of the 23 PMOS pipe, and source electrode Ps22 connects power vd D; The grid Pg23 of the 23 PMOS pipe connects CN, and drain electrode Pd23 connects the drain electrode Nd22 of the 22 NMOS pipe, and source electrode Ps23 connects Pd22; The grid Ng4 of the 4th NMOS pipe connects CN, and drain electrode Nd4 connects Pd8, and source electrode Ns4 connects the drain electrode Nd5 of the 5th NMOS pipe; The grid Ng5 of the 5th NMOS pipe connects SE, and drain electrode Nd5 connects Ns4, and source electrode Ns5 connects the drain electrode Nd6 of the 6th NMOS pipe; The grid Ng6 of the 6th NMOS pipe connects SI, and drain electrode Nd6 connects Ns5, source electrode Ns6 ground connection VSS; The grid Ng7 of the 7th NMOS pipe connects D, and drain electrode Nd7 connects Ns4, and source electrode Ns7 connects the drain electrode Nd8 of the 8th NMOS pipe; The grid Ng8 of the 8th NMOS pipe connects SEN, and drain electrode Nd8 connects Ns7, source electrode Ns8 ground connection VSS; The grid Ng9 of the 9th NMOS pipe connects CN, and drain electrode Nd9 connects Pd13, and source electrode Ns9 connects the drain electrode Nd10 of the tenth NMOS pipe; The grid Ng10 of the tenth NMOS pipe connects SE, and drain electrode Nd10 connects Ns9, and source electrode Ns10 connects the drain electrode Nd11 of the 11 NMOS pipe; The grid Ng11 of the 11 NMOS pipe connects SI, and drain electrode Nd11 connects Ns10, source electrode Ns11 ground connection VSS; The grid Ng12 of the 12 NMOS pipe connects D, and drain electrode Nd12 connects Ns9, and source electrode Ns12 connects the drain electrode Nd13 of the 13 NMOS pipe; The grid Ng13 of the 13 NMOS pipe connects SEN, and drain electrode Nd13 connects Ns12, source electrode Ns13 ground connection VSS; The grid Ng14 of the 14 NMOS pipe connects Pd13, and drain electrode Nd14 connects Pd15, and source electrode Ns14 connects the drain electrode Nd16 of the 16 NMOS pipe; The grid Ng15 of the 15 NMOS pipe connects R, and drain electrode Nd15 connects Pd15, and source electrode Ns15 connects Nd16; The grid Ng16 of the 16 NMOS pipe connects SN, and drain electrode Nd16 connects Ns14, source electrode Ns16 ground connection VSS; The grid Ng17 of the 17 NMOS pipe connects Pd8, and drain electrode Nd17 connects Pd18, and source electrode Ns17 connects the drain electrode Nd19 of the 19 NMOS pipe; The grid Ng18 of the 18 NMOS pipe connects R, and drain electrode Nd18 connects Pd18, and source electrode Ns18 connects Nd19; The grid Ng19 of the 19 NMOS pipe connects SN, and drain electrode Nd19 connects Ns17, source electrode Ns19 ground connection VSS; The grid Ng20 of the 20 NMOS pipe connects C, and drain electrode Nd20 connects Pd21, and source electrode Ns20 connects the drain electrode Nd21 of the 21 NMOS pipe; The grid Ng21 of the 21 NMOS pipe connects Pd15, and drain electrode Nd21 connects Ns20, source electrode Ns21 ground connection VSS; The grid Ng22 of the 22 NMOS pipe connects C, and drain electrode Nd22 connects Pd23, and source electrode Ns22 connects the drain electrode Nd23 of the 23 NMOS pipe; The grid Ng23 of the 23 NMOS pipe connects Pd18, and drain electrode Nd23 connects Ns22, source electrode Ns23 ground connection VSS.The 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe and the 5th NMOS pipe, the 6th NMOS pipe, the 8th NMOS pipe are formed the Scan Architecture in the main latch.
As shown in Figure 6, from latch five inputs and an output are arranged, five inputs are MO, C, CN, SN, R, an output is SO.Be made up of 14 PMOS pipes and ten four NMOS pipes from latch, the substrate of all PMOS pipes connects power vd D from latch, the substrate ground connection VSS of all NMOS pipes.The grid Pg24 of the 24 PMOS pipe connects MO, and drain electrode Pd24 connects the source electrode Nd24 of the 24 NMOS pipe, and source electrode Ps24 connects power vd D; The grid Pg25 of the 25 PMOS pipe connects CN, and drain electrode Pd25 connects the source electrode Ns25 of the 25 NMOS pipe, and source electrode Ps25 connects Pd24; The grid Pg26 of the 26 PMOS pipe connects MO, and drain electrode Pd26 connects the drain electrode Nd26 of the 26 NMOS pipe, and source electrode Ps26 connects power vd D; The grid Pg27 of the 27 PMOS pipe connects CN, and drain electrode Pd27 connects the source electrode Ns27 of the 27 NMOS pipe, and source electrode Ps27 connects Pd26; The grid Pg28 of the 28 PMOS pipe connects R, and drain electrode Pd28 connects the source electrode Ps29 of the 29 PMOS pipe, and source electrode Ps28 connects power vd D; The grid Pg29 of the 29 PMOS pipe connects Pd27, and drain electrode Pd29 connects the drain electrode Nd28 of the 28 NMOS pipe and as the output SO from latch, source electrode Ps29 connects Pd28; The grid Pg30 of the 30 PMOS pipe connects SN, and drain electrode Pd30 connects the drain electrode Nd29 of the 29 NMOS pipe, and source electrode Ps30 connects power vd D; The grid Pg31 of the 31 PMOS pipe connects R, and drain electrode Pd31 connects the source electrode Ps32 of the 32 PMOS pipe, and source electrode Ps31 connects power vd D; The grid Pg32 of the 32 PMOS pipe connects Pd25, and drain electrode Pd32 connects the drain electrode Nd31 of the 31 NMOS pipe, and source electrode Ps32 connects Pd31; The grid Pg33 of the 33 PMOS pipe connects SN, and drain electrode Pd33 connects Pd32, and source electrode Ps33 connects power vd D; The grid Pg34 of the 34 PMOS pipe connects Pd32, and drain electrode Pd34 connects the source electrode Ps35 of the 35 PMOS pipe, and source electrode Ps34 connects power vd D; The grid Pg35 of the 35 PMOS pipe connects C, and drain electrode Pd35 connects the drain electrode Nd34 of the 34 NMOS pipe, and source electrode Ps35 connects Pd34; The grid Pg36 of the 36 PMOS pipe connects Pd29, and drain electrode Pd36 connects the source electrode Ps37 of the 37 PMOS pipe, and source electrode Ps36 connects power vd D; The grid Pg37 of the 37 PMOS pipe connects C, and drain electrode Pd37 connects the drain electrode Nd36 of the 36 NMOS pipe, and source electrode Ps37 connects Pd36; The grid Ng24 of the 24 NMOS pipe connects MO, and drain electrode Nd24 connects Pd24, source electrode Ns24 ground connection VSS; The grid Ng25 of the 25 NMOS pipe connects C, and drain electrode Nd25 connects Pd24, and source electrode Ns25 connects Pd25; The grid Ng26 of the 26 NMOS pipe connects MO, and drain electrode Nd26 connects Pd26, source electrode Ns26 ground connection VSS; The grid Ng27 of the 27 NMOS pipe connects C, and drain electrode Nd27 connects Pd26, and source electrode Ns27 connects Pd27; The grid Ng28 of the 28 NMOS pipe connects Pd25, and drain electrode Nd28 connects Pd29, and source electrode Ns28 connects the drain electrode Nd30 of the 30 NMOS pipe; The grid Ng29 of the 29 NMOS pipe connects R, and drain electrode Nd29 connects Pd29, and source electrode Ns29 connects Nd30; The grid Ng30 of the 30 NMOS pipe connects SN, and drain electrode Nd30 connects Ns28, source electrode Ns30 ground connection VSS; The grid Ng31 of the 31 NMOS pipe connects Pd27, and drain electrode Nd31 connects Pd32, and source electrode Ns31 connects the drain electrode Nd33 of the 33 NMOS pipe; The grid Ng32 of the 32 NMOS pipe connects R, and drain electrode Nd32 connects Pd32, and source electrode Ns32 connects Nd33; The grid Ng33 of the 33 NMOS pipe connects SN, and drain electrode Nd33 connects Ns31, source electrode Ns33 ground connection VSS; The grid Ng34 of the 34 NMOS pipe connects CN, and drain electrode Nd34 connects Pd35, and source electrode Ns34 connects the drain electrode Nd35 of the 35 NMOS pipe; The grid Ng35 of the 35 NMOS pipe connects Pd29, and drain electrode Nd35 connects Ns34, source electrode Ns35 ground connection VSS; The grid Ng36 of the 36 NMOS pipe connects CN, and drain electrode Nd36 connects Pd37, and source electrode Ns36 connects the drain electrode Nd37 of the 37 NMOS pipe; The grid Ng37 of the 37 NMOS pipe connects Pd32, and drain electrode Nd37 connects Ns36, source electrode Ns37 ground connection VSS.
As shown in Figure 7, output buffer has three inputs and an output, and three inputs are SO, R, SN, and an output is Q.Output buffer comprises three PMOS pipes and three NMOS pipes, and the substrate of all PMOS pipes connects power vd D in the output buffer, the substrate ground connection VSS of all NMOS pipes.The grid Pg38 of the 38 PMOS pipe connects R, and drain electrode Pd38 connects the source electrode Ps39 of the 39 PMOS pipe, and source electrode Ps38 connects power vd D; The grid Pg39 of the 39 PMOS pipe connects SO, and drain electrode Pd39 connects the drain electrode Nd38 of the 38 NMOS pipe and as buffer circuit output Q, source electrode Ps39 connects Pd38; The grid Pg40 of the 40 PMOS pipe connects SN, and drain electrode Pd40 connects Pd39, and source electrode Ps40 connects power vd D; The grid Ng38 of the 38 NMOS pipe connects SO, and drain electrode Nd38 connects Pd39, and source electrode Ns38 connects the drain electrode Nd40 of the 40 NMOS pipe; The grid Ng39 of the 39 NMOS pipe connects R, and drain electrode Nd39 connects Pd39, and source electrode Ns39 connects Ns38; The grid Ng40 of the 40 NMOS pipe connects SN, and drain electrode Nd40 connects Ns38, source electrode Ns40 ground connection VSS.
The H-13 of Beijing Institute of Atomic Energy tandem accelerator can produce the LET value and be respectively 2.88MeVcm
2/ mg, 8.62MeVcm
2/ mg, 12.6MeVcm
2/ mg and 17.0MeVcm
2Four kinds of ground heavy ion irradiation test environments of/mg.To be in that the traditional unguyed setable of normal operating conditions and the Scan Architecture d type flip flop that resets, tradition are redundant reinforces Scan Architecture d type flip flop, time sampling setable and that reset and reinforce the LET value that setable and that the reset Scan Architecture d type flip flop with a kind of anti-single particle overturn of the present invention of Scan Architecture d type flip flop setable and that reset places the H-13 of Beijing Institute of Atomic Energy tandem accelerator to produce and be respectively 2.88MeVcm
2/ mg, 8.62MeVcm
2/ mg, 12.6MeVcm
2/ mg and 17.0MeVcm
2In the ground heavy ion irradiation test environment of/mg, observe each d type flip flop whether single-particle inversion takes place, obtain the minimum LET Value Data that each d type flip flop generation single-particle inversion needs.The minimum LET Value Data that Scan Architecture d type flip flop setable and that reset Scan Architecture d type flip flop generation single-particle inversion setable with a kind of anti-single particle overturn of the present invention and that reset needs is reinforced in the redundant reinforcing of the traditional unguyed setable and Scan Architecture d type flip flop that resets, tradition that the ground heavy particle irradiation test that table 1 carries out for the use H-13 of Beijing Institute of Atomic Energy tandem accelerator obtains Scan Architecture d type flip flop, time sampling setable and that reset.The unguyed Scan Architecture d type flip flop setable and that reset of tradition is 2.88MeVcm in the LET value
2/ mg, 8.62MeVcm
2/ mg, 12.6MeVcm
2/ mg and 17.0MeVcm
2Single-particle inversion all takes place in the ground heavy ion irradiation test environment of/mg when working, the redundant reinforcing of tradition Scan Architecture d type flip flop setable and that reset is 12.6MeVcm in the LET value
2/ mg and 17.0MeVcm
2Single-particle inversion takes place in the ground heavy ion irradiation test environment of/mg when working, time sampling is reinforced Scan Architecture d type flip flop setable and that reset and is 8.62MeVcm in the LET value
2/ mg, 12.6MeVcm
2/ mg and 17.0MeVcm
2Single-particle inversion takes place in the ground heavy ion irradiation test environment of/mg when working, a kind of anti-single particle overturn of the present invention is setable only to be 17.0MeVcm in the LET value with the Scan Architecture d type flip flop that resets
2Single-particle inversion takes place in the ground heavy ion irradiation test environment of/mg when working.From then on table can be found out; The minimum LET value that generation single-particle inversion of the present invention needs improves 343% than the unguyed Scan Architecture d type flip flop setable and that reset of tradition; Improve 35% than the redundant reinforcing of tradition is setable with the Scan Architecture d type flip flop that resets; Reinforce Scan Architecture d type flip flop setable and that reset than time sampling and improve 97%; So being superior to tradition unguyed Scan Architecture d type flip flop, time sampling setable and that reset, anti-single particle overturn ability of the present invention reinforces Scan Architecture d type flip flop and traditional redundant Scan Architecture d type flip flop setable and that reset of reinforcing setable and that reset; Be suitable for anti-single particle overturn and reinforce the standard cell lib of integrated circuit, be applied to fields such as Aeronautics and Astronautics.
Table 1
Claims (1)
1 An anti-SEU can be set and reset the D flip-flop scan structure, anti-SEU can
A scan set and reset by the clock circuit structure of D flip-flop, the scan control buffer circuit, reset snubber
Way, the master latch, from the latch and output buffer circuit, there are six inputs and an output,
Six inputs are the clock signal input terminal CK, D is the data signal input terminal, SE is the scan control
Built signal input, SI is the scan data input terminal, SN is set signal input terminal and outputs the reset signal RN
Into the end; i.e. the Q output terminal a data output signal terminal; clock circuit having an input terminal and two output
Side, the input terminal of CK, the output terminal of C, CN; clock is a two-stage inverter circuit, the first stage
Inverter and a second inverter stage formed; first-stage inverter of the first PMOS transistor and a first NMOS transistor group
A first PMOS transistor connected to the gate of Pg1 CK, Pd1 a drain connected to the first drain of the NMOS Nd1,
As the clock circuit and an output terminal CN; the gate of the first NMOS transistor Ng1 connection CK, drain
Nd1 connection Pd1; second stage inverter of the second PMOS transistor and a second NMOS transistor, and the second PMOS
Pg2 connecting the gate of the CN, the drain connected to the second NMOS Pd2 drain pipe Nd2, and as the clock
The other output terminal of the circuit C; second NMOS transistor connected to the gate of Ng2 CN, a drain connected Nd2 Pd2;
The first PMOS transistor and a second PMOS transistor substrate connecting the power VDD, source Ps1, Ps2 connect the power
VDD; first NMOS transistor and a second NMOS transistor substrate ground VSS, source Ns1, Ns2 also grounded
VSS; scan control buffer circuit having an input terminal and an output terminal, the input of SE, output is
SEN; scanning control buffer circuit by a third PMOS transistor and the third NMOS tubes; third PMOS transistor
The substrate and source are connected Ps3 supply VDD, the substrate of the third NMOS transistor and the source electrode are grounded Ns3
VSS; third PMOS transistor connected to the gate Pg3 SE, drain Pd3 third NMOS drain pipe connection
Nd3, and as the output of the scan control circuit SEN; Ng3 gate of the third NMOS transistor connected to SE,
Nd3 drain connection Pd3; reset buffer circuit having an input terminal and an output terminal, the input terminal is RN,
Output is R; reset buffer circuit as a level inverter, the PMOS transistor forty and forty-
An NMOS transistor composed of forty-first PMOS transistor connected to the gate Pg41 RN, a drain connected to the first Pd41
Forty-one Nd41 drain of NMOS transistor and an output buffer circuit as the reset R, electrically connected to the source Ps41
Source VDD; forty-first NMOS transistor gate Ng41 connection RN, drain Nd41 connection Pd41, the source
Ns41 ground VSS; output buffer circuit has three inputs and an output, three inputs of SO,
R, SN, an output terminal of Q; output buffer circuit includes three PMOS transistors and three NMOS transistors,
All PMOS output buffer circuit substrate tube connecting the power VDD, all connected to the substrate of the NMOS
To VSS; thirty-eighth PMOS transistor gate Pg38 connection R, connect the thirty-ninth PMOS drain Pd38
Tube source Ps39, Ps38 connect the power source VDD; thirty-ninth PMOS transistor connected to the gate Pg39
SO, drain Pd39 thirty-eighth NMOS transistor connected to the drain Nd38 output buffer circuit as Q, the source
Pole Ps39 connection Pd38; fortieth PMOS transistor gate Pg40 connection SN, drain Pd40 connection Pd39,
Ps40 connect the power source VDD; thirty-eighth NMOS transistor gate Ng38 connection SO, drain Nd38
Connect Pd39, a source connected to the fortieth Ns38 drain of NMOS transistor Nd40; thirty-ninth NMOS transistor
The gate Ng39 connection R, drain Nd39 connection Pd39, source Ns39 connection Ns38; fortieth NMOS
Tube connected to the gate Ng40 SN, drain Nd40 connection Ns38, source Ns40 ground VSS; master latch
And the slave latch are redundant latch reinforcement, and the master latch also includes scanning structure, the main lock
And the slave latch registers in tandem, and are reset to the clock circuit and a buffer circuit, a master latch further
The scan buffer control circuit, the output buffer from the latch circuit; wherein the master latch
Device has eight inputs and one output terminal, eight input is D, C, CN, SE, SEN, SI, SN,
R, one output is MO; master latch from the twenty and twenty NMOS PMOS transistor tubes,
Master latch all the PMOS substrate connecting the power VDD, all NMOS transistor substrate ground VSS;
The fourth PMOS transistor gate Pg4 connection SI, a drain connected to the fifth PMOS transistor Pd4 source Ps5, source
Connect the power pole Ps4 VDD; fifth PMOS transistor connected to the gate Pg5 SEN, a drain connected to the eighth Pd5
PMOS transistor source Ps8, source Ps5 connection Pd4; sixth PMOS transistor connected to the gate Pg6 SE,
Connect seventh PMOS transistor drain Pd6 source Ps7, Ps6 connect the power source VDD; seventh PMOS
Tube connected to the gate Pg7 D, DRAIN Pd7 connection Ps8, source Ps7 connection Pd6; eighth PMOS transistor
Gate Pg8 connection C, drain Pd8 connecting the fourth NMOS transistor drain Nd4, source Ps8 connection Pd5;
Ninth PMOS transistor gate Pg9 connection SI, drain Pd9 connection tenth PMOS transistor source Ps10, source
Connect the power pole Ps9 VDD; tenth PMOS transistor connected to the gate Pg10 SEN, a drain connected to the first Pd10
Thirteen PMOS transistor source Ps13, Ps10 source connected Pd9; eleventh PMOS transistor gate Pg11
Connect SE, drain Pd11 connection twelfth PMOS transistor source Ps12, Ps11 connect the power source VDD;
Twelfth PMOS transistor gate Pg12 connection D, DRAIN Pd12 connection Ps13, Ps12 source connected Pd11;
Thirteenth gate of the PMOS Pg13 connection C, drain Pd13 connection ninth NMOS transistor drain Nd9,
Source Ps13 connection Pd10; fourteenth PMOS transistor gate Pg14 connection R, the drain connected to the first Pd14
Fifteen PMOS transistor source Ps15, Ps14 connect the power source VDD; fifteenth PMOS transistor gate
Pg15 connection Pd8, drain Pd15 connection fourteenth NMOS transistor drain Nd14 and as a master latch
Output terminal MO, a source connected Ps15 Pd14; sixteenth gate of PMOS transistor connection Pg16 SN, drain
Pd16 connection Pd15, Ps16 connect the power source VDD; seventeenth connected PMOS transistor gate Pg17
R, drain Pd17 connection eighteenth PMOS transistor source Ps18, Ps17 connect the power source VDD; Section
Eighteen PMOS transistor gate Pg18 connection Pd13, Pd18 drain NMOS transistors connected to the drain of the seventeenth
Nd17, source Ps18 connection Pd17; nineteenth PMOS transistor gate Pg19 connection SN, drain Pd19
Connect Pd18, Ps19 connect the power source VDD; twentieth PMOS transistor gate Pg20 connection Pd18,
Drain Pd20 connection twenty-first PMOS transistor source Ps21, Ps20 connect the power source VDD; second
Eleven PMOS transistor connected to the gate Pg21 CN, drain Pd21 NMOS transistors connected to the drain of the twenty-
Nd20, source Ps21 connection Pd20; twenty-second PMOS transistor gate Pg22 connection Pd15, drain
Pd22 connection twenty-third PMOS transistor source Ps23, Ps22 connect the power source VDD; twenty-third
PMOS transistor connected to the gate Pg23 CN, drain Pd23-second NMOS transistor connected to the drain Nd22,
Source Ps23 connection Pd22; fourth NMOS transistor connected to the gate Ng4 CN, drain Nd4 connection Pd8,
Source Ns4 fifth NMOS transistor connected to the drain Nd5; fifth NMOS transistor connected to the gate Ng5 SE,
Drain Nd5 connection Ns4, source Ns5 connection sixth NMOS transistor drain Nd6; sixth NMOS transistor
The gate Ng6 connection SI, a drain connected Nd6 Ns5, a source Ns6 ground VSS; seventh NMOS transistor
The gate Ng7 connection D, DRAIN Nd7 connection Ns4, source Ns7 eighth NMOS transistor connected to the drain
Nd8; eighth NMOS transistor connected to the gate Ng8 SEN, drain Nd8 connection Ns7, ground source Ns8
VSS; ninth NMOS transistor connected to the gate Ng9 CN, drain Nd9 connection Pd13, source Ns9 connection
Tenth NMOS transistor drain Nd10; tenth NMOS transistor connected to the gate Ng10 SE, drain Nd10
Connect Ns9, source Ns10 connection eleventh NMOS transistor drain Nd11; eleventh NMOS transistor gate
Ng11 pole connection SI, a drain connected Nd11 Ns10, a source Ns11 ground VSS; twelfth NMOS
Tube connected to the gate Ng12 D, DRAIN Nd12 connection Ns9, a source connected to the thirteenth NMOS transistor Ns12
Drain Nd13; thirteenth NMOS transistor connected to the gate Ng13 SEN, drain Nd13 connection Ns12,
Source Ns13 ground VSS; fourteenth NMOS transistor gate Ng14 connection Pd13, drain Nd14 connection
Pd15, source Ns14 sixteenth NMOS transistor connected to the drain of Nd16; fifteenth NMOS transistor gate
Ng15 connection R, drain Nd15 connection Pd15, source Ns15 connection Nd16; sixteenth NMOS transistor
Ng16 gate connection SN, a drain connected Nd16 Ns14, a source Ns16 ground VSS; seventeenth NMOS
Connecting the gate of the Ng17 Pd8, a drain connected Nd17 Pd18, a source connected to nineteenth NMOS Ns17
The drain pipe Nd19; eighteenth NMOS transistor gate Ng18 connection R, drain Nd18 connection Pd18,
Source Ns18 connection Nd19; nineteenth NMOS transistor gate Ng19 connection SN, drain Nd19 connection
Ns17, source Ns19 ground VSS; twentieth NMOS transistor gate Ng20 connection C, drain Nd20
Connect Pd21, a source connected to the twenty-first NMOS transistor Ns20 drain Nd21; twenty-first NMOS
Connecting the gate of the Ng21 Pd15, a drain connected Nd21 Ns20, a source Ns21 ground VSS; Article
Two NMOS transistor gate Ng22 connection C, drain Nd22 connection Pd23, a source connected to the twentieth Ns22
Three NMOS transistor drain Nd23; twenty-third NMOS transistor gate Ng23 connection Pd18, drain Nd23
Connect Ns22, source Ns23 ground VSS; fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS
Tube and the fifth NMOS transistor, the sixth NMOS transistor, the eighth NMOS transistors comprise the primary latch scan
Structure; the slave latch has five inputs and one output terminal, the input terminal is five MO, C, CN, SN,
R, one output is SO; slave latch by a fourteen PMOS transistors and NMOS transistors composed of fourteen, from
All the PMOS latch substrate connecting the power VDD, all NMOS transistor substrate ground VSS;
Twenty-fourth PMOS transistor connected to the gate Pg24 MO, drain Pd24 connection twenty-fourth NMOS transistor
Source Nd24, Ps24 connect the power source VDD; twenty-fifth PMOS transistor connected to the gate Pg25 CN,
Drain Pd25 connection twenty-fifth NMOS transistor source Ns25, source Ps25 connection Pd24; twentieth
Six PMOS transistor connected to the gate Pg26 MO, drain Pd26 twenty-sixth NMOS transistor connected to the drain
Nd26, Ps26 connect the power source VDD; twenty-seventh PMOS transistor connected to the gate Pg27 CN, leakage
Pole Pd27 twenty-seventh NMOS transistors connected source Ns27, source Ps27 connection Pd26; twenty-eighth
PMOS transistor gate Pg28 connection R, a drain connected to the twenty-ninth PMOS transistor Pd28 source Ps29,
Ps28 connect the power source VDD; twenty-ninth PMOS transistor gate Pg29 connection Pd27, drain Pd29
NMOS transistor connected to the drain of the twenty-eighth Nd28 as the output from the latch SO, the source electrode Ps29
Connect Pd28; thirtieth PMOS transistor gate Pg30 connection SN, a drain connected to the twenty-ninth NMOS Pd30
The drain pipe Nd29, Ps30 connect the power source VDD; thirty first PMOS transistor connected to the gate Pg31
Then R, drain Pd31 connection thirty second source of the PMOS Ps32, Ps31 connect the power source VDD;
Thirty-second PMOS transistor gate Pg32 connection Pd25, Pd32 drain NMOS transistors connected to the thirty-first
Drain Nd31, source Ps32 connection Pd31; thirty-third PMOS transistor gate Pg33 connection SN,
Connect the drain Pd33 Pd32, Ps33 connect the power source VDD; thirty-fourth PMOS transistor gate Pg34
Connect Pd32, Pd34 drain pipe connecting the thirty-fifth PMOS source Ps35, Ps34 connect the power source
VDD; thirty-fifth PMOS transistor gate Pg35 connection C, a drain connected to the thirty-fourth NMOS Pd35
The drain pipe Nd34, source Ps35 connection Pd34; thirty-sixth PMOS transistor gate Pg36 connection Pd29,
Drain Pd36 connection thirty-seventh PMOS transistor source Ps37, Ps36 connect the power source VDD; Third
Seventeen PMOS transistor gate Pg37 connection C, drain Pd37 thirty-sixth NMOS transistor connected to the drain
Nd36, source Ps37 connection Pd36; twenty-fourth NMOS transistor connected to the gate Ng24 MO, drain
Nd24 connection Pd24, source Ns24 ground VSS; twenty-fifth NMOS transistor gate Ng25 connection C,
Nd25 drain connection Pd24, source Ns25 connection Pd25; twenty-sixth NMOS transistor gate Ng26
Connect MO, drain Nd26 connection Pd26, source Ns26 ground VSS; twenty-seventh NMOS transistor
Gate Ng27 connection C, drain Nd27 connection Pd26, source Ns27 connection Pd27; twenty-eighth NMOS
Tube connected to the gate Ng28 Pd25, drain Nd28 connection Pd29, a source connected to the thirtieth NMOS Ns28
The drain pipe Nd30; twenty-ninth NMOS transistor gate Ng29 connection R, drain Nd29 connection Pd29,
Source Ns29 connection Nd30; thirtieth NMOS transistor gate Ng30 connection SN, drain Nd30 connection
Ns28, source Ns30 ground VSS; thirty first NMOS transistor gate Ng31 connection Pd27, drain
Nd31 connection Pd32, a source connected to the thirty-third NMOS transistor Ns31 drain Nd33; thirty second NMOS
Tube connected to the gate Ng32 R, drain Nd32 connection Pd32, source Ns32 connection Nd33; thirty-third
NMOS transistor gate Ng33 connection SN, drain Nd33 connection Ns31, source Ns33 ground VSS;
Thirty-fourth NMOS transistor connected to the gate Ng34 CN, drain Nd34 connection Pd35, even a source Ns34
Then thirty-fifth NMOS transistor drain Nd35; thirty-fifth NMOS transistor gate Ng35 connection Pd29,
Drain Nd35 connection Ns34, source Ns35 ground VSS; thirty-sixth NMOS transistor gate Ng36
Connect CN, drain Nd36 connection Pd37, a source connected to the thirty-seventh NMOS transistor Ns36 drain Nd37;
Thirty-seventh NMOS transistor gate Ng37 connection Pd32, drain Nd37 connection Ns36, source Ns37
Ground VSS.
...
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| CN103825582A (en) * | 2013-12-11 | 2014-05-28 | 中国人民解放军国防科学技术大学 | D trigger resisting single event upset and single event transient |
| CN103825580A (en) * | 2013-12-11 | 2014-05-28 | 中国人民解放军国防科学技术大学 | Settable scanning structure D trigger resisting single event upset and single event transient |
| CN103825577A (en) * | 2013-12-11 | 2014-05-28 | 中国人民解放军国防科学技术大学 | Anti-single event upset and anti-single event transient resettable scanning structure D trigger |
| CN103825586A (en) * | 2013-12-11 | 2014-05-28 | 中国人民解放军国防科学技术大学 | Anti-single event upset and anti-single event transient settable reset scanning structure D trigger |
| CN103825585A (en) * | 2013-12-11 | 2014-05-28 | 中国人民解放军国防科学技术大学 | Synchronously resettable scanning structure D trigger resisting single event upset and single event transient |
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| CN103825577A (en) * | 2013-12-11 | 2014-05-28 | 中国人民解放军国防科学技术大学 | Anti-single event upset and anti-single event transient resettable scanning structure D trigger |
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| CN103856197A (en) * | 2013-12-11 | 2014-06-11 | 中国人民解放军国防科学技术大学 | Scanning structure D flip-flop resistant to single particle upset and single particle transient |
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| CN103825582A (en) * | 2013-12-11 | 2014-05-28 | 中国人民解放军国防科学技术大学 | D trigger resisting single event upset and single event transient |
| CN103825580A (en) * | 2013-12-11 | 2014-05-28 | 中国人民解放军国防科学技术大学 | Settable scanning structure D trigger resisting single event upset and single event transient |
| CN103825586A (en) * | 2013-12-11 | 2014-05-28 | 中国人民解放军国防科学技术大学 | Anti-single event upset and anti-single event transient settable reset scanning structure D trigger |
| CN103825580B (en) * | 2013-12-11 | 2016-10-05 | 中国人民解放军国防科学技术大学 | Anti-single particle upset and the setable Scan Architecture d type flip flop of single-ion transient state |
| CN106330164A (en) * | 2015-06-29 | 2017-01-11 | 复旦大学 | NOR gate or And gate-based preparation method for anti-radiation latch |
| CN106330164B (en) * | 2015-06-29 | 2019-12-20 | 复旦大学 | Preparation method of anti-radiation latch based on NOR gate and AND gate |
| CN105790734B (en) * | 2016-03-31 | 2018-09-07 | 中国人民解放军国防科学技术大学 | Primary particle inversion resistant triplication redundancy d type flip flop of the band from error correction and detection |
| CN105790734A (en) * | 2016-03-31 | 2016-07-20 | 中国人民解放军国防科学技术大学 | Triplication redundancy D trigger capable of realizing self error detection and single event upset prevention |
| CN110311656B (en) * | 2019-07-03 | 2023-01-31 | 西安微电子技术研究所 | Self-adaptive single event upset resistant asynchronous reset and set D trigger |
| CN110311656A (en) * | 2019-07-03 | 2019-10-08 | 西安微电子技术研究所 | A kind of adaptively primary particle inversion resistant asynchronous reset and set d type flip flop |
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