CN103825584B

CN103825584B - Setable and the reset d type flip flop of anti-single particle upset and single-ion transient state

Info

Publication number: CN103825584B
Application number: CN201310674406.3A
Authority: CN
Inventors: 池雅庆; 姚龙; 邱明新; 梁斌; 郭阳; 陈书明; 胡春媚; 刘宗林; 陈建军; 孙永节; 李振涛
Original assignee: National University of Defense Technology
Current assignee: National University of Defense Technology
Priority date: 2013-12-11
Filing date: 2013-12-11
Publication date: 2016-06-15
Anticipated expiration: 2033-12-11
Also published as: CN103825584A

Abstract

The invention discloses the setable and reset d type flip flop of anti-single particle upset and single-ion transient state, it is therefore an objective to solve setable and reset d type flip flop anti-single particle transient state and anti-single particle overturns the problem that ability is not high. The present invention by clock circuit, reset buffer circuit, set buffer circuit, main latch, forms from latch, output buffer and buffer circuits. Main latch and from latch be redundancy reinforce latch. Main latch and from latch tandem, and be all connected with clock circuit, reset buffer circuit, set buffer circuit. Main latch is also connected with buffer circuits, is also connected with output buffer from latch. Separate main latch and the C being mutually redundant from latch²MOS circuit improves primary particle inversion resistant ability. Buffer circuits makes not make a mistake under long-term single event transient pulse, and duplication redundancy path further increases the ability of anti-single particle transient state.

Description

Setable and the reset d type flip flop of anti-single particle upset and single-ion transient state

Technical field

The present invention relates to a kind of D master-slave flip-flop, particularly to the setable and reset d type flip flop of a kind of anti-single particle upset (SingleEventUpset, SEU) and anti-single particle transient state (SingleEventTransient, SET).

Background technology

Cosmic space exists a large amount of high energy particle (proton, electronics, heavy ion etc.), after sequence circuit in integrated circuit is subject to these high-energy particle bombardments, the state of its maintenance is likely to occur upset, this effect is called Single event upset effecf, the LET(linear energy transfer of single-particle bombardment integrated circuit) value is more high, more easily produces Single event upset effecf. After combinational circuit in integrated circuit is subject to these high-energy particle bombardments, likely producing transient electrical pulses, this effect is called single-ion transient state effect, and the LET value of single-particle bombardment integrated circuit is more high, the transient electrical pulses persistent period produced is more long, and electric pulse is more easy to be gathered by sequence circuit. The upset if the state of sequence circuit makes a mistake, or single-ion transient state effect produce transient electrical pulses gathered by sequence circuit mistake, all can cause integrated circuit operation instability even produce fatal mistake, this is particularly acute in space flight, military field. Therefore, integrated circuit is reinforced thus reducing Single event upset effecf and single-ion transient state effect is more and more important.

D type flip flop is one of timing unit of employing up in integrated circuit, the anti-single particle of whole integrated circuit is overturn the ability of the upset of its anti-single particle and single-ion transient state and the ability of single-ion transient state plays a crucial role, and d type flip flop carries out corresponding reinforcing the anti-single particle upset of integrated circuit and single-ion transient state ability can be made to be improved.

Traditional d type flip flop is D master-slave flip-flop, generally constitutes by main latch with from level series of latches. Common lock storage is replaced with DICE(DualInterlockedStorageCell, dual interlocked storage cell) etc. redundancy ruggedized construction can realize primary particle inversion resistant d type flip flop.Transform input/output port on this basis, it is possible to achieve anti-single particle upset simultaneously and single-ion transient state. M.J.Myjak et al. is at The47^thThe 47th IEEE Circuits and Systems Midwest international conference of IEEEInternationalMidwestSymposiumonCircuitsandSystems() on " EnhancedFault-TolerantCMOSMemoryElements " (the strengthening fault-tolerant cmos memory cell) delivered (2004, I-453～I-456 page) on propose the DICE circuit of a kind of improvement, this circuit adopts DICE circuit to carry out anti-single particle upset and reinforces, and bidirectional data line be divide into two write data lines and two read data lines, by the duplication redundancy of data wire, make to propagate the single event transient pulse of DICE circuit by a certain data wire at any time and be difficult to cause the upset of whole circuit state, thus realizing the reinforcing for single-ion transient state. but the duplication redundancy of data wire exists positive feedback loop, producing latch information upset under the single event transient pulse of longer duration, anti-single particle transient state ability is not high.

D.G.Mavis etc. are in the Reliability Physics meeting of the IEEEReliabilityPhysicsSymposium(world) on " Softerrorratemitigationtechniquesformodernmicrocircuits " technology of microcircuit soft error rate (reduce modern) (2002 the 216th page-225 pages) delivered propose time sampling d type flip flop circuit. This circuit introduces delay and voting circuit in the feedback loop of latch data, thus has possessed the upset of certain anti-single particle and single-ion transient state ability. But voting circuit itself does not possess the ability of anti-single particle transient state, meeting output error data under single event transient pulse, anti-single particle transient state ability is not high.

Application number be 200910046337.5 Chinese patent disclose the upset of a kind of anti-single particle and the d type flip flop of single event transient pulse. This invention is a kind of d type flip flop being similar to that time sampling structure, including two variable connectors, two delay circuits, two protection gate circuits and three phase inverters, it is achieved that the anti-single particle upset of d type flip flop and the reinforcing of single-ion transient state. This patent has the ability of anti-single particle transient state, but owing to the outfan Q of the 3rd reverser connects the input VIN0 of second variable connector, defining positive feedback loop, can produce latch information upset under the single event transient pulse of longer duration, anti-single particle transient state ability is not high.

Some integrated circuit needs to control the state of d type flip flop in integrated circuit, forces d type flip flop output high level or low level and the data wherein latched is set to logical one or logical zero. The original architecture basics of d type flip flop increases set and reset circuit and set signal end and reset signal end, it is possible to achieve the set of d type flip flop self and resetting structure, and controlled set and the reset function of d type flip flop by set and reset signal. But setable at present and reset d type flip flop anti-single particle transient state and anti-single particle upset ability are not high, are unfavorable in the IC chip in the fields such as Aeronautics and Astronautics and use.

Application number be 201110322677.3 Chinese patent disclose primary particle inversion resistant setable and can reset d type flip flop, as shown in Figure 1, this invention is by clock circuit, main latch, form from latch, reset buffer circuit, output buffer, it is possible to normal operation under the single-particle of higher LET value bombards and do not produce single-particle inversion.Owing to this invention does not adopt buffer circuits in clock circuit, before main latch, so not possessing the ability of anti-single particle transient state, and internal circuit configuration does not adopt duplication redundancy, when the LET value of single-particle bombardment is higher, some node upset on circuit then can cause that whole circuit overturns.

Application number be 201110323908.2 Chinese patent disclose a kind of primary particle inversion resistant setable and the d type flip flop that can reset, as shown in Figure 2, this invention is by clock circuit, main latch, form from latch, reset buffer circuit, output buffer, with Fig. 1 the difference is that output buffer have also been introduced set and reset signal, it is possible to higher LET value single-particle bombard under normal operation and do not produce single-particle inversion. Owing to this invention does not adopt buffer circuit in clock circuit, before main latch, so not possessing the ability of anti-single particle transient state, and main latch, it is provided without duplication redundancy from latch, when the LET value of single-particle bombardment is higher, some node upset on circuit then can cause that whole circuit overturns.

Summary of the invention

The technical problem to be solved in the present invention is, overturns, for current setable and reset d type flip flop anti-single particle transient state and anti-single particle, the problem that ability is not high, it is proposed to the setable and reset d type flip flop of the upset of a kind of anti-single particle and single-ion transient state.

Concretism of the present invention is: carry out duplication redundancy reinforcing to main latch with from latch, it is possible to anti-single particle overturns; Buffer circuit is added, it is possible to anti-single particle transient state in clock circuit and before main latch; Cut off the positive feedback loop being likely to be caused from latch by single event transient pulse, it is possible to do not overturn under the single event transient pulse of longer duration.

Setable and the reset d type flip flop of anti-single particle of the present invention upset and single-ion transient state by clock circuit, reset buffer circuit, set buffer circuit, main latch, from latch, output buffer and buffer circuits composition. Main latch and from latch be redundancy reinforce latch. Main latch and from latch tandem, and be all connected with clock circuit, reset buffer circuit, set buffer circuit. Main latch is also connected with buffer circuits, is also connected with output buffer from latch.

Setable and the reset d type flip flop of anti-single particle of the present invention upset and anti-single particle transient state has four inputs and an outfan. Four inputs are clock signal input terminal CK, data signal input D, set signal input part SN and reset signal input RN respectively; Outfan is Q.

Clock circuit has an input and four outfans, and input is CK, and outfan is c1, c2, cn1, cn2. Clock circuit is made up of 12 PMOS and 14 NMOS, and in circuit, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube. The grid Pg57 of the 57th PMOS connects CK, and drain electrode Pd57 connects the drain electrode Nd57, source electrode Ps57 of the 57th NMOS tube and connects power vd D; The grid Pg58 of the 58th PMOS connects the drain electrode Pd57 of the 57th PMOS, and drain electrode Pd58 connects the drain electrode Nd58, source electrode Ps58 of the 58th NMOS tube and connects power vd D; The grid Pg59 of the 59th PMOS connects the drain electrode Pd58 of the 58th PMOS, and drain electrode Pd59 connects the drain electrode Nd59, source electrode Ps59 of the 59th NMOS tube and connects power vd D;The grid Pg60 of the 60th PMOS connects the drain electrode Pd59 of the 59th PMOS, and drain electrode Pd60 connects the drain electrode Nd60, source electrode Ps60 of the 60th NMOS tube and connects power vd D; The grid Pg61 of the 61st PMOS connects CK, and drain electrode Pd61 connects the source electrode Ps62, source electrode Ps61 of the 62nd PMOS and connects VDD; The grid Pg62 of the 62nd PMOS connects the drain electrode Pd60 of the 60th PMOS, and drain electrode Pd62 connects the drain electrode Nd61 of the 61st NMOS tube, and the outfan cn1, source electrode Ps62 as clock circuit connects Pd61; The grid Pg63 of the 63rd PMOS connects CK, and drain electrode Pd63 connects the source electrode Ps64, source electrode Ps63 of the 64th PMOS and connects VDD; The grid Pg64 of the 64th PMOS connects the drain electrode Pd60 of the 60th PMOS, and drain electrode Pd64 connects the drain electrode Nd63 of the 63rd NMOS tube, and the outfan cn2, source electrode Ps64 as clock circuit connects Pd63; The grid Pg65 of the 65th PMOS is as an outfan c1 of clock circuit, and drain electrode Pd65 connects the drain electrode Pd62, source electrode Ps65 of the 62nd PMOS and connects VDD; The grid Pg66 of the 66th PMOS connects the grid Ng67 of the 67th NMOS tube and as an outfan c2 of clock circuit, and drain electrode Pd66 connects the drain electrode Nd67 of the 67th NMOS tube and connects outfan cn2, and source electrode Ps66 connects VDD; The grid Pg67 of the 67th PMOS connects outfan cn1, and drain electrode Pd67 connects outfan c1, source electrode Ps67 and connects VDD; The grid Pg68 of the 68th PMOS connects outfan cn2, and drain electrode Pd68 connects outfan c2, source electrode Ps68 and connects VDD; The grid Ng57 of the 57th NMOS tube connects CK, and drain electrode Nd57 connects the drain electrode Pd57 of the 57th PMOS; The grid Ng58 of the 58th NMOS tube connects the drain electrode Nd57 of the 57th NMOS tube, and drain electrode Nd58 connects the drain electrode Pd58, source electrode Ns58 of the 58th PMOS and connects VSS; The grid Ng59 of the 59th NMOS tube connects the drain electrode Nd58 of the 58th NMOS tube, and drain electrode Nd59 connects the drain electrode Pd59, source electrode Ns59 of the 59th PMOS and connects VSS; The grid Ng60 of the 60th NMOS tube connects the drain electrode Nd59 of the 59th NMOS tube, and drain electrode Nd60 connects the drain electrode Pd60, source electrode Ns60 of the 60th PMOS and connects VSS; The grid Ng61 of the 61st NMOS tube connects the drain electrode Nd62 of drain electrode Nd60, source electrode Ns61 connection the 62nd NMOS tube of the 60th NMOS tube, and drain electrode Nd61 connects cn1; The grid Ng62 of the 62nd NMOS tube connects CK, and drain electrode Nd62 connects the source electrode Ns61, source electrode Ns62 of the 61st NMOS tube and connects VSS; The grid Ng63 of the 63rd NMOS tube connects the drain electrode Nd64 of drain electrode Nd60, source electrode Ns63 connection the 64th NMOS tube of the 60th NMOS tube, and drain electrode connects cn2; The grid Ng64 of the 64th NMOS tube connects CK, and drain electrode Nd64 connects the source electrode Ns63, source electrode Ns64 of the 63rd NMOS tube and connects VSS; The grid Ng65 of the 65th NMOS tube connects outfan c1, and drain electrode Nd65 connects outfan cn1, source electrode Ns65 and connects the drain electrode Nd66 of the 66th NMOS tube; The grid Ng66 of the 66th NMOS tube connects outfan c1, and drain electrode Nd66 connects the 65th NMOS tube source electrode Ns65, source electrode Ns66 and connects VSS; The grid Ng67 of the 67th NMOS tube connects outfan c2, drain electrode Nd67 and connects outfan cn2, source electrode Ns67 connection the 68th NMOS tube drain electrode Nd68;The grid Ng68 of the 68th NMOS tube connects outfan c2, and drain electrode Nd68 connects the 67th NMOS tube source electrode Ns67, source electrode Ns68 and connects VSS; The grid Ng69 of the 69th NMOS tube connects outfan cn1, and drain electrode Nd69 connects outfan c1, source electrode Ns69 and connects VSS; The grid Ng70 of the 70th NMOS tube connects outfan cn2, and drain electrode Nd70 connects outfan c2, source electrode Ns70 and connects VSS.

Buffer circuits has an input and an outfan, and input is D, and outfan is D1. Buffer circuit is made up of eight PMOS and eight NMOS tube, and in buffer circuit, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube. The grid Pg1 of the first PMOS connects input D and the grid Ng1 with the first NMOS tube connects, and drain electrode Pd1 connects the drain electrode Ng1, source electrode Ps1 of the first NMOS tube and connects VDD; The grid Pg2 of the second PMOS connects the drain electrode Pd1 of the first PMOS, and drain electrode Pd2 connects the drain electrode Nd2, source electrode Ps2 of the second NMOS tube and connects VDD; The grid Pg3 of the 3rd PMOS connects the drain electrode Pd2 of the second PMOS, and drain electrode Pd3 connects the drain electrode Nd3, source electrode Ps3 of the 3rd NMOS tube and connects VDD; The grid Pg4 of the 4th PMOS connects the drain electrode Pd3 of the 3rd PMOS, and drain electrode Pd4 connects the drain electrode Nd4, source electrode Ps4 of the 4th NMOS tube and connects VDD; The grid Pg5 of the 5th PMOS connects the drain electrode Pd4 of the 4th PMOS, and drain electrode Pd5 connects the drain electrode Nd5, source electrode Ps5 of the 5th NMOS tube and connects VDD; The grid Pg6 of the 6th PMOS connects the drain electrode Pd5 of the 5th PMOS, and drain electrode Pd6 connects the drain electrode Nd6, source electrode Ps6 of the 6th NMOS tube and connects VDD; The grid Pg7 of the 7th PMOS connects the drain electrode Pd6 of the 6th PMOS, and drain electrode Pd7 connects the drain electrode Nd7, source electrode Ps7 of the 7th NMOS tube and connects VDD; The grid Pg8 of the 8th PMOS connects the drain electrode Pd7 of the 7th PMOS, and drain electrode Nd8 the output D1 as buffer, source electrode Ps8 of drain electrode Pd8 connection the 8th NMOS tube connect VDD; The grid Ng1 of the first NMOS tube connects Pg1, and drain electrode Nd1 connects Pd1, source electrode Ns1 and connects VSS; The grid Ng2 of the second NMOS tube connects the drain electrode Nd1 of the first NMOS tube, and drain electrode Nd2 connects Pd2, source electrode Ns2 and connects VSS; The grid Ng3 of the 3rd NMOS tube connects the drain electrode Nd2 of the second NMOS tube, and drain electrode Nd3 connects Pd3, source electrode Ns3 and connects VSS; The grid Ng4 of the 4th NMOS tube connects the drain electrode Nd3 of the 3rd NMOS tube, and drain electrode Nd4 connects Pd4, source electrode Ns4 and connects VSS; The grid Ng5 of the 5th NMOS tube connects the drain electrode Nd4 of the 4th NMOS tube, and drain electrode Nd5 connects Pd5, source electrode Ns5 and connects VSS; The grid Ng6 of the 6th NMOS tube connects the drain electrode Nd5 of the 5th NMOS tube, and drain electrode Nd6 connects Pd6, source electrode Ns6 and connects VSS; The grid Ng7 of the 7th NMOS tube connects the drain electrode Nd6 of the 6th NMOS tube, and drain electrode Nd7 connects Pd7, source electrode Ns7 and connects VSS; The grid Ng8 of the 8th NMOS tube connects the drain electrode Nd7 of the 7th NMOS tube, and drain electrode Nd8 connects Pd8, source electrode Ns8 and connects VSS.

Reset buffer circuit has an input and two outfans, and input is RN, and outfan is _ RN1_, _ RN2_. Reset buffer circuit is made up of 8 NMOS tube and 8 PMOS, and in reset buffer circuit, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube. The grid Pg49 of the 49th PMOS connects RN, and drain electrode Pd49 connects the drain electrode Nd49, source electrode Ps49 of the 49th NMOS tube and connects power vd D;The grid Pg50 of the 50th PMOS connects the drain electrode Pd49 of the 49th PMOS, and drain electrode Pd50 connects the drain electrode Nd50, source electrode Ps50 of the 50th NMOS tube and connects power vd D; The grid Pg51 of the 51st PMOS connects the drain electrode Pd50 of the 50th PMOS, and drain electrode Pd51 connects the drain electrode Nd51, source electrode Ps51 of the 51st NMOS tube and connects power vd D; The grid Pg52 of the 52nd PMOS connects the drain electrode Pd51 of the 51st PMOS, and drain electrode Pd52 connects the drain electrode Nd52, source electrode Ps52 of the 52nd NMOS tube and connects power vd D; The grid Pg53 of the 53rd PMOS connects RN, and drain electrode Pd53 connects the source electrode Ps54, source electrode Ps53 of the 54th PMOS and connects VDD; The grid Pg54 of the 54th PMOS connects the drain electrode Pd52 of the 52nd PMOS, and drain electrode Pd54 connects the drain electrode Nd53 of the 53rd NMOS tube, and as an outfan _ RN1_ of reset buffer circuit; The grid Pg55 of the 55th PMOS connects RN, and drain electrode Pd55 connects the source electrode Ps56, source electrode Ps55 of the 56th PMOS and connects VDD; The grid Pg56 of the 56th PMOS connects the drain electrode Pd52 of the 52nd PMOS, and drain electrode Pd56 connects the drain electrode Nd55 of the 55th NMOS tube, and the outfan _ RN2_, source electrode Ps56 as reset buffer circuit connects Pd55; The grid Ng49 of the 49th NMOS tube connects RN, and drain electrode Nd49 connects the drain electrode Pd49, source electrode Ns49 of the 49th PMOS and connects VSS; The grid Ng50 of the 50th NMOS tube connects the drain electrode Nd49 of the 49th NMOS tube, and drain electrode Nd50 connects the drain electrode Pd50, source electrode Ns50 of the 50th PMOS and connects VSS; The grid Ng51 of the 51st NMOS tube connects the drain electrode Nd50 of the 50th NMOS tube, and drain electrode Nd51 connects the drain electrode Pd51, source electrode Ns51 of the 51st PMOS and connects VSS; The grid Ng52 of the 52nd NMOS tube connects the drain electrode Nd51 of the 51st NMOS tube, and drain electrode Nd52 connects the drain electrode Pd52, source electrode Ns52 of the 52nd PMOS and connects VSS; The grid Ng53 of the 53rd NMOS tube connects the drain electrode Nd54 of drain electrode Nd52, source electrode Ns53 connection the 54th NMOS tube of the 52nd NMOS tube, and drain Nd53 connection _ RN1_; The grid Ng54 of the 54th NMOS tube connects RN, and drain electrode Nd54 connects the source electrode Nd53, source electrode Ns54 of the 53rd NMOS tube and connects VSS; The grid Ng55 of the 55th NMOS tube connects the drain electrode Nd56 of drain electrode Nd52, source electrode Ns55 connection the 56th NMOS tube of the 52nd NMOS tube, and drain Nd55 connection _ RN2_; The grid Ng56 of the 56th NMOS tube connects RN, and drain electrode Nd56 connects the source electrode Nd55, source electrode Ns56 of the 55th NMOS tube and connects VSS.

One input of set buffer circuit and two outfans, input is SN, and outfan is SN01, SN02. Set buffer circuit is made up of 10 NMOS tube and 10 PMOS, and in set buffer circuit, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube. The grid Pg39 of the 39th PMOS connects SN, and drain electrode Pd39 connects the drain electrode Nd39, source electrode Ps39 of the 39th NMOS tube and connects power vd D; The grid Pg40 of the 40th PMOS connects the drain electrode Pd39 of the 39th PMOS, and drain electrode Pd40 connects the drain electrode Nd40, source electrode Ps40 of the 40th NMOS tube and connects power vd D; The grid Pg41 of the 41st PMOS connects the drain electrode Pd40 of the 40th PMOS, and drain electrode Pd41 connects the drain electrode Nd41, source electrode Ps41 of the 41st NMOS tube and connects power vd D;The grid Pg42 of the 42nd PMOS connects the drain electrode Pd41 of the 41st PMOS, and drain electrode Pd42 connects the drain electrode Nd42, source electrode Ps42 of the 42nd NMOS tube and connects power vd D; The grid Pg43 of the 43rd PMOS connects SN, and drain electrode Pd43 connects the source electrode Ps44, source electrode Ps43 of the 44th PMOS and connects VDD; The grid Pg44 of the 44th PMOS connects the drain electrode Pd42 of the 42nd PMOS, and drain electrode Pd44 connects the drain electrode Nd43 of the 43rd NMOS tube; The grid Pg45 of the 45th PMOS connects SN, and drain electrode Pd45 connects the source electrode Ps46, source electrode Ps45 of the 46th PMOS and connects VDD; The grid Pg46 of the 46th PMOS connects the drain electrode Pd42 of the 42nd PMOS, and drain electrode Pd46 connects the drain electrode Nd45 of the 45th NMOS tube; The grid Pg47 of the 47th PMOS connects the drain electrode Pd44 of the 44th PMOS, drain electrode Pd47 and connects the drain electrode Nd47 of the 47th NMOS tube, and output a SN01, source electrode Ps47 as set buffer circuit connects VDD; 48th PMOS grid Pg48 connects the drain electrode Pd46 of the 46th PMOS, drain electrode Pd48 and connects the drain electrode Nd48 of the 48th NMOS tube, and output a SN02, source electrode Ps48 as set buffer circuit connects VDD; The grid Ng39 of the 39th NMOS tube connects SN, and drain electrode Nd39 connects the drain electrode Pd39, source electrode Ns39 of the 39th PMOS and connects VSS; The grid Ng40 of the 40th NMOS tube connects the drain electrode Nd39 of the 39th NMOS tube, and drain electrode Nd40 connects the drain electrode Pd40, source electrode Ns40 of the 40th PMOS and connects VSS; The grid Ng41 of the 41st NMOS tube connects the drain electrode Nd40 of the 40th NMOS tube, and drain electrode Nd41 connects the drain electrode Pd41, source electrode Ns41 of the 41st PMOS and connects VSS; The grid Ng42 of the 42nd NMOS tube connects the drain electrode Nd41 of the 41st NMOS tube, and drain electrode Nd42 connects the drain electrode Pd42, source electrode Ns42 of the 42nd PMOS and connects VSS; The grid Ng43 of the 43rd NMOS tube connects the drain electrode Nd44 of drain electrode Nd42, source electrode Ns43 connection the 44th NMOS tube of the 42nd NMOS tube, and drain electrode Nd43 connects the drain electrode Pd44 of the 44th PMOS; The grid Ng44 of the 44th NMOS tube connects SN, and drain electrode Nd44 connects the source electrode Nd43, source electrode Ns44 of the 43rd NMOS tube and connects VSS; The grid Ng45 of the 45th NMOS tube connects the drain electrode Nd46 of drain electrode Nd42, source electrode Ns45 connection the 46th NMOS tube of the 42nd NMOS tube, and drain electrode Nd45 connects the drain electrode Pd46 of the 46th PMOS; The grid Ng46 of the 46th NMOS tube connects SN, and drain electrode Nd46 connects the source electrode Nd45, source electrode Ns46 of the 45th NMOS tube and connects VSS; The grid Ng47 of the 47th NMOS tube connects the drain electrode Pd44 of the 44th PMOS, and drain electrode Nd47 connects the drain electrode Pd47, source electrode Ns47 of the 47th PMOS and connects VSS; 48th NMOS tube grid Ng48 connects the drain electrode Pd46 of the 46th PMOS, and drain electrode Nd48 connects the drain electrode Pd48, source electrode Ns48 of the 48th PMOS and connects VSS.

Main latch has ten inputs and two outfans, input and D, D1, c1, c2, cn1, cn2, _ RN1_, _ RN2_, SN01, and SN02 is connected; Outfan is m1, m1r. Main latch is made up of 16 PMOS and 16 NMOS, and in main latch, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube.The grid Pg9 of the 9th PMOS connects D, and drain electrode Pd9 connects the source electrode Ps10, source electrode Ps9 of the tenth PMOS and connects VDD; The grid Pg10 of the tenth PMOS connects D1, source electrode Ps10 and connects the drain electrode Pd9 of the 9th PMOS, and drain electrode Pd10 connects the source electrode Ps11 of the 11st PMOS; The grid Pg11 of the 11st PMOS connects c1, source electrode Ps11 and connects the drain electrode Pd10 of the tenth PMOS, drain electrode Pd11 connection the 9th NMOS drain electrode Nd9; The grid Pg12 of the 12nd PMOS connects D, and drain electrode connects the source electrode Ps13, source electrode Ps12 of the 13rd PMOS and connects VDD; The grid Pg13 of the 13rd PMOS connects D1, source electrode Ps13 and connects the drain electrode Pd12 of the 12nd PMOS, and drain electrode Pd13 connects the source electrode Ps14 of the 14th PMOS; The grid Pg14 of the 14th PMOS connects c2, source electrode Ps14 and connects the drain electrode Pd13 of the 13rd PMOS, drain electrode Pd14 connection the 12nd NMOS drain electrode Nd12; The grid Pg15 connection _ RN1_ of the 15th PMOS, drain electrode Pd15 connects the source electrode Ps16, source electrode Ps15 of the 16th PMOS and connects power vd D; The grid Pg16 of the 16th PMOS connects Pd11, and drain electrode Nd15 the output m1 as main latch, source electrode Ps16 of drain electrode Pd16 connection the 15th NMOS tube connect Pd15; The grid Pg17 of the 17th PMOS connects SN01, and drain electrode Pd17 connects Pd16, source electrode Ps17 and connects power vd D; The grid Pg18 connection _ RN2_ of the 18th PMOS, drain electrode Pd18 connects the source electrode Ps19, source electrode Ps18 of the 19th PMOS and connects power vd D; The grid Pg19 of the 19th PMOS connects Pd14, and drain electrode Pd19 connects the drain electrode Nd18, source electrode Ps19 of the 18th NMOS tube and connects Pd18; The grid Pg20 of the 20th PMOS connects SN02, and drain electrode Pd20 connects Pd19 and the output m1r as main latch, source electrode Ps20 connect power vd D; The grid Pg21 of the 21st PMOS connects Pd19, and drain electrode Pd21 connects the source electrode Ps22, source electrode Ps21 of the 22nd PMOS and connects power vd D; The grid Pg22 of the 22nd PMOS connects cn1, and drain electrode Pd22 connects drain electrode Nd21 and the 16 PMOS grid Pg16, source electrode Ps22 of the 21st NMOS tube and connects Pd21; The grid Pg23 of the 23rd PMOS connects Pd16, and drain electrode Pd23 connects the source electrode Ps24, source electrode Ps23 of the 24th PMOS and connects power vd D; The grid Pg24 of the 24th PMOS connects cn2, and drain electrode Pd24 connects drain electrode Nd23 and the 19 PMOS grid Pg19, source electrode Ps24 of the 23rd NMOS tube and connects Pd23; The grid Ng9 of the 9th NMOS tube connects cn1, source electrode Ns9 and connects the drain electrode Nd10 of the tenth NMOS tube, and drain electrode Nd9 connects the drain electrode Pd11 of the 11st PMOS; The grid Ng10 of the tenth NMOS tube connects D1, and drain electrode Nd10 connects the source electrode Ns9, source electrode Ns10 of the 9th NMOS tube and connects Nd11; The grid Ng11 of the 11st NMOS tube connects input D, and drain electrode Nd11 connects Ns10, source electrode Ns11 and connects VSS; The grid Ng12 of the 12nd NMOS tube connects cn2, source electrode Ns12 and connects the drain electrode Nd13 of the 13rd NMOS tube, and drain electrode Nd12 connects the drain electrode Pd14 of the 14th PMOS; The grid Ng13 of the 13rd NMOS tube connects D1, and drain electrode Nd13 connects the source electrode Ns12, source electrode Ns13 of the 12nd NMOS tube and connects Nd14; The grid Ng14 of the 14th NMOS tube connects input D, and drain electrode Nd14 connects Ns13, source electrode Ns11 and connects VSS; The grid Ng15 of the 15th NMOS tube connects Pd14, and drain electrode Nd15 connects Pd16, source electrode Ns15 and connects the drain electrode Nd17 of the 17th NMOS tube;The grid Ng16 connection _ RN2_ of the 16th NMOS tube, drain electrode Nd16 connects Pd16, source electrode Ns16 and connects Nd17; The grid Ng17 of the 17th NMOS tube connects SN02, and drain electrode Nd17 connects Ns15, source electrode Ns17 ground connection VSS; The grid Ng18 of the 18th NMOS tube connects Pd11, and drain electrode Nd18 connects Pd19, source electrode Ns18 and connects the drain electrode Nd20 of the 20th NMOS tube; The grid Ng19 connection _ RN1_ of the 19th NMOS tube, drain electrode Nd19 connects Pd19, source electrode Ns19 and connects Nd20; The grid Ng20 of the 20th NMOS tube connects SN01, and drain electrode Nd20 connects Ns18, source electrode Ns20 ground connection VSS; The grid Ng21 of the 21st NMOS tube connects c1, and drain electrode Nd21 connects Pd22, source electrode Ns21 and connects the drain electrode Nd22 of the 22nd NMOS tube; The grid Ng22 of the 22nd NMOS tube connects Pd16, and drain electrode Nd22 connects Ns21, source electrode Ns22 ground connection VSS; The grid Ng23 of the 23rd NMOS tube connects c2, and drain electrode Nd23 connects Pd24, source electrode Ns23 and connects the drain electrode Nd24 of the 24th NMOS tube; The grid Ng24 of the 24th NMOS tube connects Pd19, and drain electrode Nd24 connects Ns23, source electrode Ns24 ground connection VSS.

There are ten inputs and two outfans, input and c1, c2, cn1, cn2, m1, m1r, _ RN1_, _ RN2_, SN01, SN02 from latch, are connected; Outfan is s1, s1r. Being made up of from latch 14 PMOS and 14 NMOS tube, from latch, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube. The grid Pg25 of the 25th PMOS connects m1r, and drain electrode Pd25 connects the source electrode Ps26, source electrode Ps25 of the 26th PMOS and connects power vd D; The grid Pg26 of the 26th PMOS connects cn1, and drain electrode Pd26 connects the drain electrode Nd25 of the 25th NMOS tube, and source electrode connects Pd25; The grid Pg27 of the 27th PMOS connects m1, and drain electrode Pd27 connects the source electrode Ps28, source electrode Ps27 of the 28th PMOS and connects power vd D; The grid Pg28 of the 28th PMOS connects cn2, and drain electrode Pd28 connects the drain electrode Nd27 of the 27th NMOS tube, and source electrode connects Pd27; The grid Pg29 connection _ RN1_ of the 29th PMOS, drain electrode Pd29 connects the source electrode Ps30, source electrode Ps29 of the 30th PMOS and connects power vd D; The grid Pg30 of the 30th PMOS connects Pd26, and drain electrode Pd30 connects the drain electrode Nd29 of the 29th NMOS tube and connects Pd29 as from the output s1 of latch, source electrode Ps30; The grid Pg31 of the 31st PMOS connects SN01, and drain electrode Pd31 connects Pd30, source electrode Ps31 and connects power vd D; The grid Pg32 connection _ RN2_ of the 32nd PMOS, drain electrode Pd32 connects the source electrode Ps33, source electrode Ps32 of the 33rd PMOS and connects power vd D; The grid Pg33 of the 33rd PMOS connects Pd28, and drain electrode Pd33 connects the drain electrode Nd32 of the 32nd NMOS tube and connects Pd32 as from the outfan s1r of latch, source electrode Ps33; The grid Pg34 of the 34th PMOS connects SN02, and drain electrode Pd34 connects Pd33 and connects outfan s1r, and source electrode Ps34 connects power vd D; The grid Pg35 of the 35th PMOS connects Pd33, and drain electrode Pd35 connects the source electrode Ps36, source electrode Ps35 of the 36th PMOS and connects power vd D; The grid Pg36 of the 36th PMOS connects c1, and drain electrode Pd36 connects drain electrode Nd35 and the 30 PMOS grid Pg30, source electrode Ps36 of the 35th NMOS tube and connects Pd35;The grid Pg37 of the 37th PMOS connects Pd30, and drain electrode Pd37 connects the source electrode Ps38, source electrode Ps37 of the 38th PMOS and connects power vd D; The grid Pg38 of the 38th PMOS connects c2, and drain electrode Pd38 connects drain electrode Nd37 and the 33 PMOS grid Pg33, source electrode Ps38 of the 37th NMOS tube and connects Pd37; The grid Ng25 of the 25th NMOS tube connects c1, and drain electrode Nd25 connects Pd26, source electrode Ns25 and connects the drain electrode Nd26 of the 26th NMOS tube; The grid Ng26 of the 26th NMOS tube connects m1, and drain electrode Nd26 connects Ns25, source electrode Ns26 ground connection VSS; The grid Ng27 of the 27th NMOS tube connects c2, and drain electrode Nd27 connects Pd28, source electrode Ns27 and connects the drain electrode Nd28 of the 28th NMOS tube; The grid Ng28 of the 28th NMOS tube connects m1r, and drain electrode Nd28 connects Ns27, source electrode Ns28 ground connection VSS; The grid Ng29 of the 29th NMOS tube connects Pd28, and drain electrode Nd29 connects Pd30, source electrode Ns29 and connects the drain electrode Nd31 of the 31st NMOS tube; The grid Ng30 connection _ RN2_ of the 30th NMOS tube, drain electrode Nd30 connects Pd30, source electrode Ns30 and connects Nd31; The grid Pg31 of the 31st NMOS tube connects SN02, and drain electrode Nd31 connects Ns29, source electrode Ns31 ground connection VSS; The grid Ng32 of the 32nd NMOS tube connects Pd26, and drain electrode Nd32 connects Pd33, source electrode Ns32 and connects the drain electrode Nd34 of the 34th NMOS tube; The grid Ng33 connection _ RN1_ of the 33rd NMOS tube, drain electrode Nd33 connects Pd33, source electrode Ns33 and connects Nd34; The grid Ng34 of the 34th NMOS tube connects SN01, and drain electrode Nd34 connects Ns32, source electrode Ns32 ground connection VSS; The grid Ng35 of the 35th NMOS tube connects cn1, and drain electrode Nd35 connects Pd34, source electrode Ns35 and connects the drain electrode Nd36 of the 36th NMOS tube; The grid Ng36 of the 36th NMOS tube connects Pd30, and drain electrode Nd36 connects Ns35, source electrode Ns36 ground connection VSS; The grid Ng37 of the 37th NMOS tube connects cn2, and drain electrode Nd37 connects Pd38, source electrode Ns37 and connects the drain electrode Nd38 of the 38th NMOS tube; The grid Ng38 of the 38th NMOS tube connects Pd33, and drain electrode Nd38 connects Ns37, source electrode Ns38 ground connection VSS.

Output buffer has two inputs and an outfan, and input connects s1 and s1r, and outfan is Q. Output buffer is made up of two PMOS and two NMOS tube, and in output buffer, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube. The grid Pg69 of the 69th PMOS connects s1r, and drain electrode Pd69 connects the drain electrode Nd71, source electrode Ps69 of the 71st NMOS tube and connects power vd D; The grid Pg70 of the 70th PMOS connects the drain electrode Pd69 of the 69th PMOS, and drain electrode Pd70 connects the drain electrode Nd72 of the 72nd NMOS tube, and connects power vd D as the output Q of inverter circuit, source electrode Ps70; The grid Ng71 of the 71st NMOS tube connects s1, and drain electrode Nd71 connects the drain electrode Pd69 of the 69th PMOS; The grid Ng72 of the 72nd NMOS tube connects the drain electrode Nd71 of the 71st NMOS tube, and drain electrode Nd72 connects the drain electrode Pd70, source electrode Ns72 of the 70th PMOS and connects VSS.

Setable and the reset d type flip flop work process of anti-single particle of the present invention upset and anti-single particle transient state is as follows:

Setable and the reset d type flip flop of anti-single particle of the present invention upset and single-ion transient state can carry out set and reset, set and reset function at any time by SN and set signal input part and RN and reset signal input co-controlling.

When SN be low level, RN is high level or low level, setable and the reset d type flip flop of anti-single particle of the present invention upset and single-ion transient state enters SM set mode, namely main latch and from latch all by latching logic by force " 1 ", the outfan Q of output buffer is high level.

When SN be high level, RN is low level, setable and the reset d type flip flop of anti-single particle of the present invention upset and single-ion transient state enters reset state, namely main latch and from latch all by latching logic by force " 0 ", the outfan Q of output buffer is low level.

When SN be high level, RN is high level, setable and the reset d type flip flop of anti-single particle of the present invention upset and single-ion transient state is in normal operating conditions, clock circuit receives CK, cn1 and cn2 reverse with CK is produced by the inverter circuit of circuit intermediate formation after it is cushioned, produced and CK c1 and c2 in the same direction by the inverter circuit of circuit end, and cn1, cn2, c1 and c2 are passed to main latch and from latch. Buffer circuits receives D, the D1 of output and D homophase after being postponed by D. It is between low period at CK, cn1 and cn2 is high level, c1 and c2 is low level, main latch is opened, receive D and D1, and to D and D1 is likely to single event transient pulse filter, then pass through latch output and m1 and m1r of D homophase, be in preservation state from latch, do not receive m1, m1r of main latch output, but preserve m1, m1r that a CK trailing edge samples; It is between high period at CK, cn1 and cn2 is low level, c1 and c2 is high level, main latch is in preservation state, preserve D and D1 that previous CK rising edge samples and export and m1 and m1r of D homophase, open and receive output m1 and the m1r of main latch from latch, m1 and m1r is cushioned and exports and s1 and s1r of m1 and m1r homophase. Output buffer will receive output s1 and the s1r from latch at any time, the Q to s1 and s1r buffering output and s1 and s1r homophase.

Reset buffer circuit will input after signal postpones by the C of duplication redundancy²MOS structure filter RN is likely to single event transient pulse, and by output with RN homophase _ RN1_ and _ RN2_ feeding main latch and from latch, carry out the control of reset behavior.

Set buffer circuit will input after signal postpones by the C of duplication redundancy²MOS structure filter SN is likely to single event transient pulse, and output sent into main latch and from latch with SN01 and SN02 of SN homophase, carries out the control of set behavior.

Adopt the present invention can reach techniques below effect:

The d type flip flop that the d type flip flop that anti-single particle upset and anti-single particle transient state ability are better than the unguyed d type flip flop of tradition, time sampling is reinforced of the setable and reset d type flip flop of anti-single particle of the present invention upset and single-ion transient state and tradition duplication redundancy are reinforced. The unguyed d type flip flop structure of tradition is transformed by the present invention, to main latch with all carried out duplication redundancy reinforcing from latch, and for main latch and from latch C²MOS circuit has improved, and namely separates the C being mutually redundant²Pull-up PMOS in MOS circuit and pull-down NMOS pipe, improve the primary particle inversion resistant ability of the present invention. Add buffer circuits in clock circuit and before main latch, make the present invention not make a mistake under long-term single event transient pulse;By well-designed duplication redundancy path, cut off the positive feedback loop being likely to be caused by single event transient pulse from latch, further increase the ability of anti-single particle transient state. Setable and the reset d type flip flop of anti-single particle of the present invention upset and single-ion transient state is suitable for anti-single particle upset and the standard cell lib of anti-single particle transient state reinforcing integrated circuit, is applied to the fields such as Aeronautics and Astronautics.

Accompanying drawing explanation

Fig. 1 is application number is 201110322677.3 primary particle inversion resistant setable and the d type flip flop overall logic structural representation that can reset

Fig. 2 is application number be 201110323908.2 one primary particle inversion resistant setable and can reset d type flip flop overall logic structural representation

Fig. 3 is the setable and reset d type flip flop overall logic structural representation of anti-single particle of the present invention upset and single-ion transient state.

Fig. 4 is the clock circuit structural representation of the setable and reset d type flip flop of anti-single particle of the present invention upset and single-ion transient state.

Fig. 5 is anti-single particle of the present invention upset and buffer circuit configuration schematic diagram in the setable and reset d type flip flop of single-ion transient state.

Fig. 6 is the mid-bit buffering electrical block diagram of setable and reset d type flip flop of anti-single particle of the present invention upset and single-ion transient state

Fig. 7 is anti-single particle of the present invention upset and reset buffer circuit structure schematic diagram in the setable and reset d type flip flop of single-ion transient state

Fig. 8 is anti-single particle of the present invention upset and main latch structural representation in the setable and reset d type flip flop of single-ion transient state.

Fig. 9 is that anti-single particle of the present invention overturns and in the setable and reset d type flip flop of single-ion transient state from latch structure schematic diagram.

Figure 10 is anti-single particle of the present invention upset and output buffer structural representation in the setable and reset d type flip flop of single-ion transient state.

Detailed description of the invention

Fig. 3 is the setable and reset d type flip flop logical structure schematic diagram of anti-single particle of the present invention upset and single-ion transient state. The present invention is by clock circuit (as shown in Figure 4), buffer circuits (as shown in Figure 5), set buffer circuit (as shown in Figure 6), reset buffer circuit (as shown in Figure 7), main latch (as shown in Figure 8), form from latch (as shown in Figure 9) and output buffer (as shown in Figure 10). Setable and the reset d type flip flop of anti-single particle of the present invention upset and single-ion transient state has four inputs and an outfan. Four inputs are CK and clock signal input terminal, D and data signal input, RN and reset signal input and SN and set signal input part respectively; Outfan is Q. Clock circuit receives CK, exports c1, c2 and cn1, cn2 after CK is carried out buffered respectively. Main latch receives D, D1, c1, c2 and cn1, cn2 and _ RN1_, _ RN2_ and SN01, SN02, main latch c1, c2 and cn1, cn2 and _ RN1_, _ RN2_ and SN01, SN02 control under D and D1 is carried out latch process after output m1, m1r. From latch receive m1, m1r and c1, c2 and cn1, cn2, _ RN1_, _ RN2_ and SN01, SN02, from latch c1, c2 and cn1, cn2, _ RN1_, _ RN2_ and SN01, SN02 control m1, m1r are carried out latch process after export s1, s1r respectively. Output buffer receives s1, s1r, exports Q after it is carried out buffered.

As shown in Figure 4, clock circuit has an input and four outfans, and input is CK, and outfan is c1, c2, cn1, cn2.Clock circuit is made up of 12 PMOS and 14 NMOS, and in circuit, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube. The grid Pg57 of the 57th PMOS connects CK, and drain electrode Pd57 connects the drain electrode Nd57, source electrode Ps57 of the 57th NMOS tube and connects power vd D; The grid Pg58 of the 58th PMOS connects the drain electrode Pd57 of the 57th PMOS, and drain electrode Pd58 connects the drain electrode Nd58, source electrode Ps58 of the 58th NMOS tube and connects power vd D; The grid Pg59 of the 59th PMOS connects the drain electrode Pd58 of the 58th PMOS, and drain electrode Pd59 connects the drain electrode Nd59, source electrode Ps59 of the 59th NMOS tube and connects power vd D; The grid Pg60 of the 60th PMOS connects the drain electrode Pd59 of the 59th PMOS, and drain electrode Pd60 connects the drain electrode Nd60, source electrode Ps60 of the 60th NMOS tube and connects power vd D; The grid Pg61 of the 61st PMOS connects CK, and drain electrode Pd61 connects the source electrode Ps62, source electrode Ps61 of the 62nd PMOS and connects VDD; The grid Pg62 of the 62nd PMOS connects the drain electrode Pd60 of the 60th PMOS, and drain electrode Pd62 connects the drain electrode Nd61 of the 61st NMOS tube, and the outfan cn1, source electrode Ps62 as clock circuit connects Pd61; The grid Pg63 of the 63rd PMOS connects CK, and drain electrode Pd63 connects the source electrode Ps64, source electrode Ps63 of the 64th PMOS and connects VDD; The grid Pg64 of the 64th PMOS connects the drain electrode Pd60 of the 60th PMOS, and drain electrode Pd64 connects the drain electrode Nd63 of the 63rd NMOS tube, and the outfan cn2, source electrode Ps64 as clock circuit connects Pd63; The grid Pg65 of the 65th PMOS is as an outfan c1 of clock circuit, and drain electrode Pd65 connects the drain electrode Pd62, source electrode Ps65 of the 62nd PMOS and connects VDD; The grid Pg66 of the 66th PMOS connects the grid Ng67 of the 67th NMOS tube and as an outfan c2 of clock circuit, and drain electrode Pd66 connects the drain electrode Nd67 of the 67th NMOS tube and connects outfan cn2, and source electrode Ps66 connects VDD; The grid Pg67 of the 67th PMOS connects outfan cn1, and drain electrode Pd67 connects outfan c1, source electrode Ps67 and connects VDD; The grid Pg68 of the 68th PMOS connects outfan cn2, and drain electrode Pd68 connects outfan c2, source electrode Ps68 and connects VDD; The grid Ng57 of the 57th NMOS tube connects CK, and drain electrode Nd57 connects the drain electrode Pd57 of the 57th PMOS; The grid Ng58 of the 58th NMOS tube connects the drain electrode Nd57 of the 57th NMOS tube, and drain electrode Nd58 connects the drain electrode Pd58, source electrode Ns58 of the 58th PMOS and connects VSS; The grid Ng59 of the 59th NMOS tube connects the drain electrode Nd58 of the 58th NMOS tube, and drain electrode Nd59 connects the drain electrode Pd59, source electrode Ns59 of the 59th PMOS and connects VSS; The grid Ng60 of the 60th NMOS tube connects the drain electrode Nd59 of the 59th NMOS tube, and drain electrode Nd60 connects the drain electrode Pd60, source electrode Ns60 of the 60th PMOS and connects VSS; The grid Ng61 of the 61st NMOS tube connects the drain electrode Nd62 of drain electrode Nd60, source electrode Ns61 connection the 62nd NMOS tube of the 60th NMOS tube, and drain electrode Nd61 connects cn1; The grid Ng62 of the 62nd NMOS tube connects CK, and drain electrode Nd62 connects the source electrode Ns61, source electrode Ns62 of the 61st NMOS tube and connects VSS; The grid Ng63 of the 63rd NMOS tube connects the drain electrode Nd64 of drain electrode Nd60, source electrode Ns63 connection the 64th NMOS tube of the 60th NMOS tube, and drain electrode connects cn2;The grid Ng64 of the 64th NMOS tube connects CK, and drain electrode Nd64 connects the source electrode Ns63, source electrode Ns64 of the 63rd NMOS tube and connects VSS; The grid Ng65 of the 65th NMOS tube connects outfan c1, and drain electrode Nd65 connects outfan cn1, source electrode Ns65 and connects the drain electrode Nd66 of the 66th NMOS tube; The grid Ng66 of the 66th NMOS tube connects outfan c1, and drain electrode Nd66 connects the 65th NMOS tube source electrode Ns65, source electrode Ns66 and connects VSS; The grid Ng67 of the 67th NMOS tube connects outfan c2, drain electrode Nd67 and connects outfan cn2, source electrode Ns67 connection the 68th NMOS tube drain electrode Nd68; The grid Ng68 of the 68th NMOS tube connects outfan c2, and drain electrode Nd68 connects the 67th NMOS tube source electrode Ns67, source electrode Ns68 and connects VSS; The grid Ng69 of the 69th NMOS tube connects outfan cn1, and drain electrode Nd69 connects outfan c1, source electrode Ns69 and connects VSS; The grid Ng70 of the 70th NMOS tube connects outfan cn2, and drain electrode Nd70 connects outfan c2, source electrode Ns70 and connects VSS.

As it is shown in figure 5, buffer circuits has an input and an outfan, input is D, and outfan is D1. Buffer circuit is made up of eight PMOS and eight NMOS tube, and in buffer circuit, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube. The grid Pg1 of the first PMOS connects input D and the grid Ng1 with the first NMOS tube connects, and drain electrode Pd1 connects the drain electrode Ng1, source electrode Ps1 of the first NMOS tube and connects VDD; The grid Pg2 of the second PMOS connects the drain electrode Pd1 of the first PMOS, and drain electrode Pd2 connects the drain electrode Nd2, source electrode Ps2 of the second NMOS tube and connects VDD; The grid Pg3 of the 3rd PMOS connects the drain electrode Pd2 of the second PMOS, and drain electrode Pd3 connects the drain electrode Nd3, source electrode Ps3 of the 3rd NMOS tube and connects VDD; The grid Pg4 of the 4th PMOS connects the drain electrode Pd3 of the 3rd PMOS, and drain electrode Pd4 connects the drain electrode Nd4, source electrode Ps4 of the 4th NMOS tube and connects VDD; The grid Pg5 of the 5th PMOS connects the drain electrode Pd4 of the 4th PMOS, and drain electrode Pd5 connects the drain electrode Nd5, source electrode Ps5 of the 5th NMOS tube and connects VDD; The grid Pg6 of the 6th PMOS connects the drain electrode Pd5 of the 5th PMOS, and drain electrode Pd6 connects the drain electrode Nd6, source electrode Ps6 of the 6th NMOS tube and connects VDD; The grid Pg7 of the 7th PMOS connects the drain electrode Pd6 of the 6th PMOS, and drain electrode Pd7 connects the drain electrode Nd7, source electrode Ps7 of the 7th NMOS tube and connects VDD; The grid Pg8 of the 8th PMOS connects the drain electrode Pd7 of the 7th PMOS, and drain electrode Nd8 the outfan D1 as buffer, source electrode Ps8 of drain electrode Pd8 connection the 8th NMOS tube connect VDD; The grid Ng1 of the first NMOS tube connects Pg1, and drain electrode Nd1 connects Pd1, source electrode Ns1 and connects VSS; The grid Ng2 of the second NMOS tube connects the drain electrode Nd1 of the first NMOS tube, and drain electrode Nd2 connects Pd2, source electrode Ns2 and connects VSS; The grid Ng3 of the 3rd NMOS tube connects the drain electrode Nd2 of the second NMOS tube, and drain electrode Nd3 connects Pd3, source electrode Ns3 and connects VSS; The grid Ng4 of the 4th NMOS tube connects the drain electrode Nd3 of the 3rd NMOS tube, and drain electrode Nd4 connects Pd4, source electrode Ns4 and connects VSS; The grid Ng5 of the 5th NMOS tube connects the drain electrode Nd4 of the 4th NMOS tube, and drain electrode Nd5 connects Pd5, source electrode Ns5 and connects VSS; The grid Ng6 of the 6th NMOS tube connects the drain electrode Nd5 of the 5th NMOS tube, and drain electrode Nd6 connects Pd6, source electrode Ns6 and connects VSS;The grid Ng7 of the 7th NMOS tube connects the drain electrode Nd6 of the 6th NMOS tube, and drain electrode Nd7 connects Pd7, source electrode Ns7 and connects VSS; The grid Ng8 of the 8th NMOS tube connects the drain electrode Nd7 of the 7th NMOS tube, and drain electrode Nd8 connects Pd8, source electrode Ns8 and connects VSS.

As shown in Figure 6, one input of set buffer circuit and two outfans, input is SN, and outfan is SN01, SN02. Set buffer circuit is made up of 10 NMOS tube and 10 PMOS, and in set buffer circuit, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube. The grid Pg39 of the 39th PMOS connects SN, and drain electrode Pd39 connects the drain electrode Nd39, source electrode Ps39 of the 39th NMOS tube and connects power vd D; The grid Pg40 of the 40th PMOS connects the drain electrode Pd39 of the 39th PMOS, and drain electrode Pd40 connects the drain electrode Nd40, source electrode Ps40 of the 40th NMOS tube and connects power vd D; The grid Pg41 of the 41st PMOS connects the drain electrode Pd40 of the 40th PMOS, and drain electrode Pd41 connects the drain electrode Nd41, source electrode Ps41 of the 41st NMOS tube and connects power vd D; The grid Pg42 of the 42nd PMOS connects the drain electrode Pd41 of the 41st PMOS, and drain electrode Pd42 connects the drain electrode Nd42, source electrode Ps42 of the 42nd NMOS tube and connects power vd D; The grid Pg43 of the 43rd PMOS connects SN, and drain electrode Pd43 connects the source electrode Ps44, source electrode Ps43 of the 44th PMOS and connects VDD; The grid Pg44 of the 44th PMOS connects the drain electrode Pd42 of the 42nd PMOS, and drain electrode Pd44 connects the drain electrode Nd43 of the 43rd NMOS tube; The grid Pg45 of the 45th PMOS connects SN, and drain electrode Pd45 connects the source electrode Ps46, source electrode Ps45 of the 46th PMOS and connects VDD; The grid Pg46 of the 46th PMOS connects the drain electrode Pd42 of the 42nd PMOS, and drain electrode Pd46 connects the drain electrode Nd45 of the 45th NMOS tube; The grid Pg47 of the 47th PMOS connects the drain electrode Pd44 of the 44th PMOS, drain electrode Pd47 and connects the drain electrode Nd47 of the 47th NMOS tube, and output a SN01, source electrode Ps47 as set buffer circuit connects VDD; 48th PMOS grid Pg48 connects the drain electrode Pd46 of the 46th PMOS, drain electrode Pd48 and connects the drain electrode Nd48 of the 48th NMOS tube, and output a SN02, source electrode Ps48 as set buffer circuit connects VDD; The grid Ng39 of the 39th NMOS tube connects SN, and drain electrode Nd39 connects the drain electrode Pd39, source electrode Ns39 of the 39th PMOS and connects VSS; The grid Ng40 of the 40th NMOS tube connects the drain electrode Nd39 of the 39th NMOS tube, and drain electrode Nd40 connects the drain electrode Pd40, source electrode Ns40 of the 40th PMOS and connects VSSVSS; The grid Ng41 of the 41st NMOS tube connects the drain electrode Nd40 of the 40th NMOS tube, and drain electrode Nd41 connects the drain electrode Pd41, source electrode Ns41 of the 41st PMOS and connects VSSVSS; The grid Ng42 of the 42nd NMOS tube connects the drain electrode Nd41 of the 41st NMOS tube, and drain electrode Nd42 connects the drain electrode Pd42, source electrode Ns42 of the 42nd PMOS and connects VSSVSS; The grid Ng43 of the 43rd NMOS tube connects the drain electrode Nd44 of drain electrode Nd42, source electrode Ns43 connection the 44th NMOS tube of the 42nd NMOS tube, and drain electrode Nd43 connects the drain electrode Pd44 of the 44th PMOS; The grid Ng44 of the 44th NMOS tube connects SN, and drain electrode Nd44 connects the source electrode Nd43, source electrode Ns44 of the 43rd NMOS tube and connects VSS;The grid Ng45 of the 45th NMOS tube connects the drain electrode Nd46 of drain electrode Nd42, source electrode Ns45 connection the 46th NMOS tube of the 42nd NMOS tube, and drain electrode Nd45 connects the drain electrode Pd46 of the 46th PMOS; The grid Ng46 of the 46th NMOS tube connects SN, and drain electrode Nd46 connects the source electrode Nd45, source electrode Ns46 of the 45th NMOS tube and connects VSS; The grid Ng47 of the 47th NMOS tube connects the drain electrode Pd44 of the 44th PMOS, and drain electrode Nd47 connects the drain electrode Pd47, source electrode Ns47 of the 47th PMOS and connects VSS; 48th NMOS tube grid Ng48 connects the drain electrode Pd46 of the 46th PMOS, and drain electrode Nd48 connects the drain electrode Pd48, source electrode Ns48 of the 48th PMOS and connects VSS.

As it is shown in fig. 7, reset buffer circuit has an input and two outfans, input is RN, and outfan is _ RN1_, _ RN2_. Reset buffer circuit is made up of 8 NMOS tube and 8 PMOS, and in reset buffer circuit, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube. The grid Pg49 of the 49th PMOS connects RN, and drain electrode Pd49 connects the drain electrode Nd49, source electrode Ps49 of the 49th NMOS tube and connects power vd D; The grid Pg50 of the 50th PMOS connects the drain electrode Pd49 of the 49th PMOS, and drain electrode Pd50 connects the drain electrode Nd50, source electrode Ps50 of the 50th NMOS tube and connects power vd D; The grid Pg51 of the 51st PMOS connects the drain electrode Pd50 of the 50th PMOS, and drain electrode Pd51 connects the drain electrode Nd51, source electrode Ps51 of the 51st NMOS tube and connects power vd D; The grid Pg52 of the 52nd PMOS connects the drain electrode Pd51 of the 51st PMOS, and drain electrode Pd52 connects the drain electrode Nd52, source electrode Ps52 of the 52nd NMOS tube and connects power vd D; The grid Pg53 of the 53rd PMOS connects RN, and drain electrode Pd53 connects the source electrode Ps54, source electrode Ps53 of the 54th PMOS and connects VDD; The grid Pg54 of the 54th PMOS connects the drain electrode Pd52 of the 52nd PMOS, and drain electrode Pd54 connects the drain electrode Nd53 of the 53rd NMOS tube, and as an outfan _ RN1_ of reset buffer circuit; The grid Pg55 of the 55th PMOS connects RN, and drain electrode Pd55 connects the source electrode Ps56, source electrode Ps55 of the 56th PMOS and connects VDD; The grid Pg56 of the 56th PMOS connects the drain electrode Pd52 of the 52nd PMOS, and drain electrode Pd56 connects the drain electrode Nd55 of the 55th NMOS tube, and as an outfan _ RN2_ of reset buffer circuit; The grid Ng49 of the 49th NMOS tube connects RN, and drain electrode Nd49 connects the drain electrode Pd49, source electrode Ns49 of the 49th PMOS and connects VSS; The grid Ng50 of the 50th NMOS tube connects the drain electrode Nd49 of the 49th NMOS tube, and drain electrode Nd50 connects the drain electrode Pd50, source electrode Ns50 of the 50th PMOS and connects VSSVSS; The grid Ng51 of the 51st NMOS tube connects the drain electrode Nd50 of the 50th NMOS tube, and drain electrode Nd51 connects the drain electrode Pd51, source electrode Ns51 of the 51st PMOS and connects VSSVSS; The grid Ng52 of the 52nd NMOS tube connects the drain electrode Nd51 of the 51st NMOS tube, and drain electrode Nd52 connects the drain electrode Pd52, source electrode Ns52 of the 52nd PMOS and connects VSSVSS; The grid Ng53 of the 53rd NMOS tube connects the drain electrode Nd54 of drain electrode Nd52, source electrode Ns53 connection the 54th NMOS tube of the 52nd NMOS tube, and drain Nd53 connection _ RN1_;The grid Ng54 of the 54th NMOS tube connects RN, and drain electrode Nd54 connects the source electrode Nd53, source electrode Ns54 of the 53rd NMOS tube and connects VSS; The grid Ng55 of the 55th NMOS tube connects the drain electrode Nd56 of drain electrode Nd52, source electrode Ns55 connection the 56th NMOS tube of the 52nd NMOS tube, and drain Nd55 connection _ RN2_; The grid Ng56 of the 56th NMOS tube connects RN, and drain electrode Nd56 connects the source electrode Nd55, source electrode Ns56 of the 55th NMOS tube and connects VSS.

As shown in Figure 8, main latch has ten inputs and two outfans, input and D, D1, c1, c2, cn1, cn2, _ RN1_, _ RN2_, SN01, and SN02 is connected; Outfan is m1, m1r. Main latch is made up of 16 PMOS and 16 NMOS, and in main latch, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube. The grid Pg9 of the 9th PMOS connects D, and drain electrode Pd9 connects the source electrode Ps10, source electrode Ps9 of the tenth PMOS and connects VDD; The grid Pg10 of the tenth PMOS connects D1, source electrode Ps10 and connects the drain electrode Pd9 of the 9th PMOS, and drain electrode Pd10 connects the source electrode Ps11 of the 11st PMOS; The grid Pg11 of the 11st PMOS connects c1, source electrode Ps11 and connects the drain electrode Pd10 of the tenth PMOS, drain electrode Pd11 connection the 9th NMOS drain electrode Nd9; The grid Pg12 of the 12nd PMOS connects D, and drain electrode connects the source electrode Ps13, source electrode Ps12 of the 13rd PMOS and connects VDD; The grid Pg13 of the 13rd PMOS connects D1, source electrode Ps13 and connects the drain electrode Pd12 of the 12nd PMOS, and drain electrode Pd13 connects the source electrode Ps14 of the 14th PMOS; The grid Pg14 of the 14th PMOS connects c2, source electrode Ps14 and connects the drain electrode Pd13 of the 13rd PMOS, drain electrode Pd14 connection the 12nd NMOS drain electrode Nd12; The grid Pg15 connection _ RN1_ of the 15th PMOS, drain electrode Pd15 connects the source electrode Ps16, source electrode Ps15 of the 16th PMOS and connects power vd D; The grid Pg16 of the 16th PMOS connects Pd11, and drain electrode Nd15 the output m1 as main latch, source electrode Ps16 of drain electrode Pd16 connection the 15th NMOS tube connect Pd15; The grid Pg17 of the 17th PMOS connects SN01, and drain electrode Pd17 connects Pd16, source electrode Ps17 and connects power vd D; The grid Pg18 connection _ RN2_ of the 18th PMOS, drain electrode Pd18 connects the source electrode Ps19, source electrode Ps18 of the 19th PMOS and connects power vd D; The grid Pg19 of the 19th PMOS connects Pd14, and drain electrode Pd19 connects the drain electrode Nd18, source electrode Ps19 of the 18th NMOS tube and connects Pd18; The grid Pg20 of the 20th PMOS connects SN02, and drain electrode Pd20 connects Pd19 and the output m1r as main latch, source electrode Ps20 connect power vd D; The grid Pg21 of the 21st PMOS connects Pd19, and drain electrode Pd21 connects the source electrode Ps22, source electrode Ps21 of the 22nd PMOS and connects power vd D; The grid Pg22 of the 22nd PMOS connects cn1, and drain electrode Pd22 connects drain electrode Nd21 and the 16 PMOS grid Pg16, source electrode Ps22 of the 21st NMOS tube and connects Pd21; The grid Pg23 of the 23rd PMOS connects Pd16, and drain electrode Pd23 connects the source electrode Ps24, source electrode Ps23 of the 24th PMOS and connects power vd D; The grid Pg24 of the 24th PMOS connects cn2, and drain electrode Pd24 connects drain electrode Nd23 and the 19 PMOS grid Pg19, source electrode Ps24 of the 23rd NMOS tube and connects Pd23; The grid Ng9 of the 9th NMOS tube connects cn1, source electrode Ns9 and connects the drain electrode Nd10 of the tenth NMOS tube, and drain electrode Nd9 connects the drain electrode Pd11 of the 11st PMOS;The grid Ng10 of the tenth NMOS tube connects D1, and drain electrode Nd10 connects the source electrode Ns9, source electrode Ns10 of the 9th NMOS tube and connects Nd11; The grid Ng11 of the 11st NMOS tube connects input D, and drain electrode Nd11 connects Ns10, source electrode Ns11 and connects VSS; The grid Ng12 of the 12nd NMOS tube connects cn2, source electrode Ns12 and connects the drain electrode Nd13 of the 13rd NMOS tube, and drain electrode Nd12 connects the drain electrode Pd14 of the 14th PMOS; The grid Ng13 of the 13rd NMOS tube connects D1, and drain electrode Nd13 connects the source electrode Ns12, source electrode Ns13 of the 12nd NMOS tube and connects Nd14; The grid Ng14 of the 14th NMOS tube connects input D, and drain electrode Nd14 connects Ns13, source electrode Ns11 and connects VSS; The grid Ng15 of the 15th NMOS tube connects Pd14, and drain electrode Nd15 connects Pd16, source electrode Ns15 and connects the drain electrode Nd17 of the 17th NMOS tube; The grid Ng16 connection _ RN2_ of the 16th NMOS tube, drain electrode Nd16 connects Pd16, source electrode Ns16 and connects Nd17; The grid Ng17 of the 17th NMOS tube connects SN02, and drain electrode Nd17 connects Ns15, source electrode Ns17 ground connection VSS; The grid Ng18 of the 18th NMOS tube connects Pd11, and drain electrode Nd18 connects Pd19, source electrode Ns18 and connects the drain electrode Nd20 of the 20th NMOS tube; The grid Ng19 connection _ RN1_ of the 19th NMOS tube, drain electrode Nd19 connects Pd19, source electrode Ns19 and connects Nd20; The grid Ng20 of the 20th NMOS tube connects SN01, and drain electrode Nd20 connects Ns18, source electrode Ns20 ground connection VSS; The grid Ng21 of the 21st NMOS tube connects c1, and drain electrode Nd21 connects Pd22, source electrode Ns21 and connects the drain electrode Nd22 of the 22nd NMOS tube; The grid Ng22 of the 22nd NMOS tube connects Pd16, and drain electrode Nd22 connects Ns21, source electrode Ns22 ground connection VSS; The grid Ng23 of the 23rd NMOS tube connects c2, and drain electrode Nd23 connects Pd24, source electrode Ns23 and connects the drain electrode Nd24 of the 24th NMOS tube; The grid Ng24 of the 24th NMOS tube connects Pd19, and drain electrode Nd24 connects Ns23, source electrode Ns24 ground connection VSS.

As it is shown in figure 9, have ten inputs and two outfans, input and c1, c2, cn1, cn2, m1, m1r from latch, _ RN1_, _ RN2_, SN01, SN02, it is connected; Outfan is s1, s1r. Being made up of from latch 14 PMOS and 14 NMOS tube, from latch, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube. The grid Pg25 of the 25th PMOS connects m1r, and drain electrode Pd25 connects the source electrode Ps26, source electrode Ps25 of the 26th PMOS and connects power vd D; The grid Pg26 of the 26th PMOS connects cn1, and drain electrode Pd26 connects the drain electrode Nd25 of the 25th NMOS tube, and source electrode connects Pd25; The grid Pg27 of the 27th PMOS connects m1, and drain electrode Pd27 connects the source electrode Ps28, source electrode Ps27 of the 28th PMOS and connects power vd D; The grid Pg28 of the 28th PMOS connects cn2, and drain electrode Pd28 connects the drain electrode Nd27 of the 27th NMOS tube, and source electrode connects Pd27; The grid Pg29 connection _ RN1_ of the 29th PMOS, drain electrode Pd29 connects the source electrode Ps30, source electrode Ps29 of the 30th PMOS and connects power vd D; The grid Pg30 of the 30th PMOS connects Pd26, and drain electrode Pd30 connects the drain electrode Nd29 of the 29th NMOS tube and connects Pd29 as from the output s1 of latch, source electrode Ps30; The grid Pg31 of the 31st PMOS connects SN01, and drain electrode Pd31 connects Pd30, source electrode Ps31 and connects power vd D;The grid Pg32 connection _ RN2_ of the 32nd PMOS, drain electrode Pd32 connects the source electrode Ps33, source electrode Ps32 of the 33rd PMOS and connects power vd D; The grid Pg33 of the 33rd PMOS connects Pd28, and drain electrode Pd33 connects the drain electrode Nd32 of the 32nd NMOS tube and connects Pd32 as from the outfan s1r of latch, source electrode Ps33; The grid Pg34 of the 34th PMOS connects SN02, and drain electrode Pd34 connects Pd33 and connects outfan s1r, and source electrode Ps34 connects power vd D; The grid Pg35 of the 35th PMOS connects Pd33, and drain electrode Pd35 connects the source electrode Ps36, source electrode Ps35 of the 36th PMOS and connects power vd D; The grid Pg36 of the 36th PMOS connects c1, and drain electrode Pd36 connects drain electrode Nd35 and the 30 PMOS grid Pg30, source electrode Ps36 of the 35th NMOS tube and connects Pd35; The grid Pg37 of the 37th PMOS connects Pd30, and drain electrode Pd37 connects the source electrode Ps38, source electrode Ps37 of the 38th PMOS and connects power vd D; The grid Pg38 of the 38th PMOS connects c2, and drain electrode Pd38 connects drain electrode Nd37 and the 33 PMOS grid Pg33, source electrode Ps38 of the 37th NMOS tube and connects Pd37; The grid Ng25 of the 25th NMOS tube connects c1, and drain electrode Nd25 connects Pd26, source electrode Ns25 and connects the drain electrode Nd26 of the 26th NMOS tube; The grid Ng26 of the 26th NMOS tube connects m1, and drain electrode Nd26 connects Ns25, source electrode Ns26 ground connection VSS; The grid Ng27 of the 27th NMOS tube connects c2, and drain electrode Nd27 connects Pd28, source electrode Ns27 and connects the drain electrode Nd28 of the 28th NMOS tube; The grid Ng28 of the 28th NMOS tube connects m1r, and drain electrode Nd28 connects Ns27, source electrode Ns28 ground connection VSS; The grid Ng29 of the 29th NMOS tube connects Pd28, and drain electrode Nd29 connects Pd30, source electrode Ns29 and connects the drain electrode Nd31 of the 31st NMOS tube; The grid Ng30 connection _ RN2_ of the 30th NMOS tube, drain electrode Nd30 connects Pd30, source electrode Ns30 and connects Nd31; The grid Pg31 of the 31st NMOS tube connects SN02, and drain electrode Nd31 connects Ns29, source electrode Ns31 ground connection VSS; The grid Ng32 of the 32nd NMOS tube connects Pd26, and drain electrode Nd32 connects Pd33, source electrode Ns32 and connects the drain electrode Nd34 of the 34th NMOS tube; The grid Ng33 connection _ RN1_ of the 33rd NMOS tube, drain electrode Nd33 connects Pd33, source electrode Ns33 and connects Nd34; The grid Ng34 of the 34th NMOS tube connects SN01, and drain electrode Nd34 connects Ns32, source electrode Ns32 ground connection VSS; The grid Ng35 of the 35th NMOS tube connects cn1, and drain electrode Nd35 connects Pd34, source electrode Ns35 and connects the drain electrode Nd36 of the 36th NMOS tube; The grid Ng36 of the 36th NMOS tube connects Pd30, and drain electrode Nd36 connects Ns35, source electrode Ns36 ground connection VSS; The grid Ng37 of the 37th NMOS tube connects cn2, and drain electrode Nd37 connects Pd38, source electrode Ns37 and connects the drain electrode Nd38 of the 38th NMOS tube; The grid Ng38 of the 38th NMOS tube connects Pd33, and drain electrode Nd38 connects Ns37, source electrode Ns38 ground connection VSS.

As shown in Figure 10, output buffer has two inputs and an outfan, and input connects s1 and s1r, and outfan is Q. Output buffer is made up of two PMOS and two NMOS tube, and in output buffer, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube. The grid Pg69 of the 69th PMOS connects s1r, and drain electrode Pd69 connects the drain electrode Nd71, source electrode Ps69 of the 71st NMOS tube and connects power vd D;The grid Pg70 of the 70th PMOS connects the drain electrode Pd69 of the 69th PMOS, and drain electrode Pd70 connects the drain electrode Nd72 of the 72nd NMOS tube, and connects power vd D as the output Q of inverter circuit, source electrode Ps70; The grid Ng71 of the 71st NMOS tube connects s1, and drain electrode Nd71 connects the drain electrode Pd69 of the 69th PMOS; The grid Ng72 of the 72nd NMOS tube connects the drain electrode Nd71 of the 71st NMOS tube, and drain electrode Nd72 connects the drain electrode Pd70, source electrode Ns72 of the 70th PMOS and connects VSS.

Beijing Institute of Atomic Energy's H-13 tandem accelerator can produce LET value respectively 2.88MeV cm²/mg、8.62MeV·cm²/mg、12.6MeV·cm²/ mg and 17.0MeV cm²Four kinds of ground heavy ion irradiation test environments of/mg. by setable and reset d type flip flop unguyed for the tradition being in normal operating conditions, setable and the reset d type flip flop that tradition duplication redundancy is reinforced, setable and the reset d type flip flop that time sampling is reinforced, application number is the primary particle inversion resistant setable and reset d type flip flop of the Chinese patent proposition of 201110322677.3, application number is a kind of primary particle inversion resistant setable and reset d type flip flop that proposes of Chinese patent of 201110323908.2 and the setable and reset d type flip flop of anti-single particle of the present invention upset and single-ion transient state connects the outfan of identical 1000 grade reverser chain respectively and works with the clock frequency of 40MHz, the input of 1000 grades of reverser chains connects low level. foregoing circuit is placed in the LET value respectively 2.88MeV cm that Beijing Institute of Atomic Energy's H-13 tandem accelerator produces²/mg、8.62MeV·cm²/mg、12.6MeV·cm²/ mg and 21.3MeV cm²In the ground heavy ion irradiation test environment of/mg, add up each setable and reset d type flip flop in the heavy ion irradiation process of each LET and make a mistake the number of times of output. The total fluence of heavy ion irradiation of every kind of LET is 10⁷ion/cm². table 1 is that the ground heavy particle irradiation using Beijing Institute of Atomic Energy's H-13 tandem accelerator to carry out tests the setable and reset d type flip flop that the tradition obtained is unguyed, setable and the reset d type flip flop that tradition duplication redundancy is reinforced, setable and the reset d type flip flop that time sampling is reinforced, application number is the primary particle inversion resistant setable and reset d type flip flop of the Chinese patent proposition of 201110322677.3, application number be 201110323908.2 a kind of primary particle inversion resistant setable and reset d type flip flop that proposes of Chinese patent and the setable and reset d type flip flop of anti-single particle of the present invention upset and single-ion transient state at LET value respectively 2.88MeV cm²/mg、8.62MeV·cm²/mg、12.6MeV·cm²/ mg and 21.3MeV cm²Make a mistake in the ground heavy ion irradiation process of/mg the number of times exported. The total fluence of heavy ion irradiation of every kind of LET is 10⁷ion/cm². can be seen that from the statistics of table 1, the anti-single particle upset of the present invention and single-ion transient state ability are better than the setable and reset d type flip flop that tradition is unguyed, setable and the reset d type flip flop that time sampling is reinforced, application number is the primary particle inversion resistant setable and reset d type flip flop of the Chinese patent proposition of 201110322677.3, application number is a kind of primary particle inversion resistant setable and reset the d type flip flop setable and reset d type flip flop with tradition duplication redundancy reinforcing of the Chinese patent proposition of 201110323908.2, it is suitable for anti-single particle upset and the standard cell lib of single-ion transient state reinforcing integrated circuit, it is applied to aviation, the fields such as space flight.

Table 1

Claims

1. the setable and reset d type flip flop of anti-single particle upset and single-ion transient state, including clock circuit, reset buffer circuit, main latch, from latch, output buffer, it is characterised in that the setable and reset d type flip flop of anti-single particle upset and single-ion transient state also includes buffer circuits, set buffer circuit;Main latch and from latch be redundancy reinforce latch; Main latch and from latch tandem, and be all connected with clock circuit, reset buffer circuit, set buffer circuit; Main latch is also connected with buffer circuits, is also connected with output buffer from latch; There are four inputs and an outfan; Four inputs are clock signal input terminal CK, data signal input D, set signal input part SN and reset signal input RN respectively; Outfan is Q;

Described clock circuit has an input and four outfans, and input is CK, and outfan is c1, c2, cn1, cn2; Clock circuit is made up of 12 PMOS and 14 NMOS, and in circuit, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube; The grid Pg57 of the 57th PMOS connects CK, and drain electrode Pd57 connects the drain electrode Nd57, source electrode Ps57 of the 57th NMOS tube and connects power vd D; The grid Pg58 of the 58th PMOS connects the drain electrode Pd57 of the 57th PMOS, and drain electrode Pd58 connects the drain electrode Nd58, source electrode Ps58 of the 58th NMOS tube and connects power vd D; The grid Pg59 of the 59th PMOS connects the drain electrode Pd58 of the 58th PMOS, and drain electrode Pd59 connects the drain electrode Nd59, source electrode Ps59 of the 59th NMOS tube and connects power vd D; The grid Pg60 of the 60th PMOS connects the drain electrode Pd59 of the 59th PMOS, and drain electrode Pd60 connects the drain electrode Nd60, source electrode Ps60 of the 60th NMOS tube and connects power vd D; The grid Pg61 of the 61st PMOS connects CK, and drain electrode Pd61 connects the source electrode Ps62, source electrode Ps61 of the 62nd PMOS and connects VDD; The grid Pg62 of the 62nd PMOS connects the drain electrode Pd60 of the 60th PMOS, and drain electrode Pd62 connects the drain electrode Nd61 of the 61st NMOS tube, and the outfan cn1, source electrode Ps62 as clock circuit connects Pd61; The grid Pg63 of the 63rd PMOS connects CK, and drain electrode Pd63 connects the source electrode Ps64, source electrode Ps63 of the 64th PMOS and connects VDD; The grid Pg64 of the 64th PMOS connects the drain electrode Pd60 of the 60th PMOS, and drain electrode Pd64 connects the drain electrode Nd63 of the 63rd NMOS tube, and the outfan cn2, source electrode Ps64 as clock circuit connects Pd63; The grid Pg65 of the 65th PMOS is as an outfan c1 of clock circuit, and drain electrode Pd65 connects the drain electrode Pd62, source electrode Ps65 of the 62nd PMOS and connects VDD; The grid Pg66 of the 66th PMOS connects the grid Ng67 of the 67th NMOS tube and as an outfan c2 of clock circuit, and drain electrode Pd66 connects the drain electrode Nd67 of the 67th NMOS tube and connects outfan cn2, and source electrode Ps66 connects VDD; The grid Pg67 of the 67th PMOS connects outfan cn1, and drain electrode Pd67 connects outfan c1, source electrode Ps67 and connects VDD; The grid Pg68 of the 68th PMOS connects outfan cn2, and drain electrode Pd68 connects outfan c2, source electrode Ps68 and connects VDD; The grid Ng57 of the 57th NMOS tube connects CK, and drain electrode Nd57 connects the drain electrode Pd57 of the 57th PMOS; The grid Ng58 of the 58th NMOS tube connects the drain electrode Nd57 of the 57th NMOS tube, and drain electrode Nd58 connects the drain electrode Pd58, source electrode Ns58 of the 58th PMOS and connects VSS; The grid Ng59 of the 59th NMOS tube connects the drain electrode Nd58 of the 58th NMOS tube, and drain electrode Nd59 connects the drain electrode Pd59, source electrode Ns59 of the 59th PMOS and connects VSS;The grid Ng60 of the 60th NMOS tube connects the drain electrode Nd59 of the 59th NMOS tube, and drain electrode Nd60 connects the drain electrode Pd60, source electrode Ns60 of the 60th PMOS and connects VSS; The grid Ng61 of the 61st NMOS tube connects the drain electrode Nd62 of drain electrode Nd60, source electrode Ns61 connection the 62nd NMOS tube of the 60th NMOS tube, and drain electrode Nd61 connects cn1; The grid Ng62 of the 62nd NMOS tube connects CK, and drain electrode Nd62 connects the source electrode Ns61, source electrode Ns62 of the 61st NMOS tube and connects VSS; The grid Ng63 of the 63rd NMOS tube connects the drain electrode Nd64 of drain electrode Nd60, source electrode Ns63 connection the 64th NMOS tube of the 60th NMOS tube, and drain electrode connects cn2; The grid Ng64 of the 64th NMOS tube connects CK, and drain electrode Nd64 connects the source electrode Ns63, source electrode Ns64 of the 63rd NMOS tube and connects VSS; The grid Ng65 of the 65th NMOS tube connects outfan c1, and drain electrode Nd65 connects outfan cn1, source electrode Ns65 and connects the drain electrode Nd66 of the 66th NMOS tube; The grid Ng66 of the 66th NMOS tube connects outfan c1, and drain electrode Nd66 connects the 65th NMOS tube source electrode Ns65, source electrode Ns66 and connects VSS; The grid Ng67 of the 67th NMOS tube connects outfan c2, drain electrode Nd67 and connects outfan cn2, source electrode Ns67 connection the 68th NMOS tube drain electrode Nd68; The grid Ng68 of the 68th NMOS tube connects outfan c2, and drain electrode Nd68 connects the 67th NMOS tube source electrode Ns67, source electrode Ns68 and connects VSS; The grid Ng69 of the 69th NMOS tube connects l outfan cn1, and drain electrode Nd69 connects outfan c1, source electrode Ns69 and connects VSS; The grid Ng70 of the 70th NMOS tube connects outfan cn2, and drain electrode Nd70 connects outfan c2, source electrode Ns70 and connects VSS;

Described buffer circuits has an input and an outfan, and input is D, and outfan is D1; Buffer circuit is made up of eight PMOS and eight NMOS tube, and in buffer circuit, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube; The grid Pg1 of the first PMOS connects input D and the grid Ng1 with the first NMOS tube connects, and drain electrode Pd1 connects the drain electrode Ng1, source electrode Ps1 of the first NMOS tube and connects VDD; The grid Pg2 of the second PMOS connects the drain electrode Pd1 of the first PMOS, and drain electrode Pd2 connects the drain electrode Nd2, source electrode Ps2 of the second NMOS tube and connects VDD; The grid Pg3 of the 3rd PMOS connects the drain electrode Pd2 of the second PMOS, and drain electrode Pd3 connects the drain electrode Nd3, source electrode Ps3 of the 3rd NMOS tube and connects VDD; The grid Pg4 of the 4th PMOS connects the drain electrode Pd3 of the 3rd PMOS, and drain electrode Pd4 connects the drain electrode Nd4, source electrode Ps4 of the 4th NMOS tube and connects VDD; The grid Pg5 of the 5th PMOS connects the drain electrode Pd4 of the 4th PMOS, and drain electrode Pd5 connects the drain electrode Nd5, source electrode Ps5 of the 5th NMOS tube and connects VDD; The grid Pg6 of the 6th PMOS connects the drain electrode Pd5 of the 5th PMOS, and drain electrode Pd6 connects the drain electrode Nd6, source electrode Ps6 of the 6th NMOS tube and connects VDD; The grid Pg7 of the 7th PMOS connects the drain electrode Pd6 of the 6th PMOS, and drain electrode Pd7 connects the drain electrode Nd7, source electrode Ps7 of the 7th NMOS tube and connects VDD; The grid Pg8 of the 8th PMOS connects the drain electrode Pd7 of the 7th PMOS, and drain electrode Nd8 the output D1 as buffer, source electrode Ps8 of drain electrode Pd8 connection the 8th NMOS tube connect VDD; The grid Ng1 of the first NMOS tube connects Pg1, and drain electrode Nd1 connects Pd1, source electrode Ns1 and connects VSS;The grid Ng2 of the second NMOS tube connects the drain electrode Nd1 of the first NMOS tube, and drain electrode Nd2 connects Pd2, source electrode Ns2 and connects VSS; The grid Ng3 of the 3rd NMOS tube connects the drain electrode Nd2 of the second NMOS tube, and drain electrode Nd3 connects Pd3, source electrode Ns3 and connects VSS; The grid Ng4 of the 4th NMOS tube connects the drain electrode Nd3 of the 3rd NMOS tube, and drain electrode Nd4 connects Pd4, source electrode Ns4 and connects VSS; The grid Ng5 of the 5th NMOS tube connects the drain electrode Nd4 of the 4th NMOS tube, and drain electrode Nd5 connects Pd5, source electrode Ns5 and connects VSS; The grid Ng6 of the 6th NMOS tube connects the drain electrode Nd5 of the 5th NMOS tube, and drain electrode Nd6 connects Pd6, source electrode Ns6 and connects VSS; The grid Ng7 of the 7th NMOS tube connects the drain electrode Nd6 of the 6th NMOS tube, and drain electrode Nd7 connects Pd7, source electrode Ns7 and connects VSS; The grid Ng8 of the 8th NMOS tube connects the drain electrode Nd7 of the 7th NMOS tube, and drain electrode Nd8 connects Pd8, source electrode Ns8 and connects VSS;

Described reset buffer circuit has an input and two outfans, and input is RN, and outfan is _ RN1_, _ RN2_; Reset buffer circuit is made up of 8 NMOS tube and 8 PMOS, and in reset buffer circuit, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube; The grid Pg49 of the 49th PMOS connects RN, and drain electrode Pd49 connects the drain electrode Nd49, source electrode Ps49 of the 49th NMOS tube and connects power vd D; The grid Pg50 of the 50th PMOS connects the drain electrode Pd49 of the 49th PMOS, and drain electrode Pd50 connects the drain electrode Nd50, source electrode Ps50 of the 50th NMOS tube and connects power vd D; The grid Pg51 of the 51st PMOS connects the drain electrode Pd50 of the 50th PMOS, and drain electrode Pd51 connects the drain electrode Nd51, source electrode Ps51 of the 51st NMOS tube and connects power vd D; The grid Pg52 of the 52nd PMOS connects the drain electrode Pd51 of the 51st PMOS, and drain electrode Pd52 connects the drain electrode Nd52, source electrode Ps52 of the 52nd NMOS tube and connects power vd D; The grid Pg53 of the 53rd PMOS connects RN, and drain electrode Pd53 connects the source electrode Ps54, source electrode Ps53 of the 54th PMOS and connects VDD; The grid Pg54 of the 54th PMOS connects the drain electrode Pd52 of the 52nd PMOS, and drain electrode Pd54 connects the drain electrode Nd53 of the 53rd NMOS tube, and as an outfan _ RN1_ of reset buffer circuit; The grid Pg55 of the 55th PMOS connects RN, and drain electrode Pd55 connects the source electrode Ps56, source electrode Ps55 of the 56th PMOS and connects VDD; The grid Pg56 of the 56th PMOS connects the drain electrode Pd52 of the 52nd PMOS, and drain electrode Pd56 connects the drain electrode Nd55 of the 55th NMOS tube, and the outfan _ RN2_, source electrode Ps56 as reset buffer circuit connects Pd55; The grid Ng49 of the 49th NMOS tube connects RN, and drain electrode Nd49 connects the drain electrode Pd49, source electrode Ns49 of the 49th PMOS and connects VSS; The grid Ng50 of the 50th NMOS tube connects the drain electrode Nd49 of the 49th NMOS tube, and drain electrode Nd50 connects the drain electrode Pd50, source electrode Ns50 of the 50th PMOS and connects VSS; The grid Ng51 of the 51st NMOS tube connects the drain electrode Nd50 of the 50th NMOS tube, and drain electrode Nd51 connects the drain electrode Pd51, source electrode Ns51 of the 51st PMOS and connects VSS; The grid Ng52 of the 52nd NMOS tube connects the drain electrode Nd51 of the 51st NMOS tube, and drain electrode Nd52 connects the drain electrode Pd52, source electrode Ns52 of the 52nd PMOS and connects VSS; The grid Ng53 of the 53rd NMOS tube connects the drain electrode Nd54 of drain electrode Nd52, source electrode Ns53 connection the 54th NMOS tube of the 52nd NMOS tube, and drain Nd53 connection _ RN1_;The grid Ng54 of the 54th NMOS tube connects RN, and drain electrode Nd54 connects the source electrode Nd53, source electrode Ns54 of the 53rd NMOS tube and connects VSS; The grid Ng55 of the 55th NMOS tube connects the drain electrode Nd56 of drain electrode Nd52, source electrode Ns55 connection the 56th NMOS tube of the 52nd NMOS tube, and drain Nd55 connection _ RN2_; The grid Ng56 of the 56th NMOS tube connects RN, and drain electrode Nd56 connects the source electrode Nd55, source electrode Ns56 of the 55th NMOS tube and connects VSS;

One input of described set buffer circuit and two outfans, input is SN, and outfan is SN01, SN02; Set buffer circuit is made up of 10 NMOS tube and 10 PMOS, and in set buffer circuit, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube; The grid Pg39 of the 39th PMOS connects SN, and drain electrode Pd39 connects the drain electrode Nd39, source electrode Ps39 of the 39th NMOS tube and connects power vd D; The grid Pg40 of the 40th PMOS connects the drain electrode Pd39 of the 39th PMOS, and drain electrode Pd40 connects the drain electrode Nd40, source electrode Ps40 of the 40th NMOS tube and connects power vd D; The grid Pg41 of the 41st PMOS connects the drain electrode Pd40 of the 40th PMOS, and drain electrode Pd41 connects the drain electrode Nd41, source electrode Ps41 of the 41st NMOS tube and connects power vd D; The grid Pg42 of the 42nd PMOS connects the drain electrode Pd41 of the 41st PMOS, and drain electrode Pd42 connects the drain electrode Nd42, source electrode Ps42 of the 42nd NMOS tube and connects power vd D; The grid Pg43 of the 43rd PMOS connects SN, and drain electrode Pd43 connects the source electrode Ps44, source electrode Ps43 of the 44th PMOS and connects VDD; The grid Pg44 of the 44th PMOS connects the drain electrode Pd42 of the 42nd PMOS, and drain electrode Pd44 connects the drain electrode Nd43 of the 43rd NMOS tube; The grid Pg45 of the 45th PMOS connects SN, and drain electrode Pd45 connects the source electrode Ps46, source electrode Ps45 of the 46th PMOS and connects VDD; The grid Pg46 of the 46th PMOS connects the drain electrode Pd42 of the 42nd PMOS, and drain electrode Pd46 connects the drain electrode Nd45 of the 45th NMOS tube; The grid Pg47 of the 47th PMOS connects the drain electrode Pd44 of the 44th PMOS, drain electrode Pd47 and connects the drain electrode Nd47 of the 47th NMOS tube, and output a SN01, source electrode Ps47 as set buffer circuit connects VDD; 48th PMOS grid Pg48 connects the drain electrode Pd46 of the 46th PMOS, drain electrode Pd48 and connects the drain electrode Nd48 of the 48th NMOS tube, and output a SN02, source electrode Ps48 as set buffer circuit connects VDD; The grid Ng39 of the 39th NMOS tube connects SN, and drain electrode Nd39 connects the drain electrode Pd39, source electrode Ns39 of the 39th PMOS and connects VSS; The grid Ng40 of the 40th NMOS tube connects the drain electrode Nd39 of the 39th NMOS tube, and drain electrode Nd40 connects the drain electrode Pd40, source electrode Ns40 of the 40th PMOS and connects VSS; The grid Ng41 of the 41st NMOS tube connects the drain electrode Nd40 of the 40th NMOS tube, and drain electrode Nd41 connects the drain electrode Pd41, source electrode Ns41 of the 41st PMOS and connects VSS; The grid Ng42 of the 42nd NMOS tube connects the drain electrode Nd41 of the 41st NMOS tube, and drain electrode Nd42 connects the drain electrode Pd42, source electrode Ns42 of the 42nd PMOS and connects VSS; The grid Ng43 of the 43rd NMOS tube connects the drain electrode Nd44 of drain electrode Nd42, source electrode Ns43 connection the 44th NMOS tube of the 42nd NMOS tube, and drain electrode Nd43 connects the drain electrode Pd44 of the 44th PMOS;The grid Ng44 of the 44th NMOS tube connects SN, and drain electrode Nd44 connects the source electrode Nd43, source electrode Ns44 of the 43rd NMOS tube and connects VSS; The grid Ng45 of the 45th NMOS tube connects the drain electrode Nd46 of drain electrode Nd42, source electrode Ns45 connection the 46th NMOS tube of the 42nd NMOS tube, and drain electrode Nd45 connects the drain electrode Pd46 of the 46th PMOS; The grid Ng46 of the 46th NMOS tube connects SN, and drain electrode Nd46 connects the source electrode Nd45, source electrode Ns46 of the 45th NMOS tube and connects VSS; The grid Ng47 of the 47th NMOS tube connects the drain electrode Pd44 of the 44th PMOS, and drain electrode Nd47 connects the drain electrode Pd47, source electrode Ns47 of the 47th PMOS and connects VSS; 48th NMOS tube grid Ng48 connects the drain electrode Pd46 of the 46th PMOS, and drain electrode Nd48 connects the drain electrode Pd48, source electrode Ns48 of the 48th PMOS and connects VSS;

Described main latch has ten inputs and two outfans, input and D, D1, c1, c2, cn1, cn2, _ RN1_, _ RN2_, SN01, and SN02 is connected; Outfan is m1, m1r; Main latch is made up of 16 PMOS and 16 NMOS, and in main latch, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube; The grid Pg9 of the 9th PMOS connects D, and drain electrode Pd9 connects the source electrode Ps10, source electrode Ps9 of the tenth PMOS and connects VDD; The grid Pg10 of the tenth PMOS connects D1, source electrode Ps10 and connects the drain electrode Pd9 of the 9th PMOS, and drain electrode Pd10 connects the source electrode Ps11 of the 11st PMOS; The grid Pg11 of the 11st PMOS connects c1, source electrode Ps11 and connects the drain electrode Pd10 of the tenth PMOS, drain electrode Pd11 connection the 9th NMOS drain electrode Nd9; The grid Pg12 of the 12nd PMOS connects D, and drain electrode connects the source electrode Ps13, source electrode Ps12 of the 13rd PMOS and connects VDD; The grid Pg13 of the 13rd PMOS connects D1, source electrode Ps13 and connects the drain electrode Pd12 of the 12nd PMOS, and drain electrode Pd13 connects the source electrode Ps14 of the 14th PMOS; The grid Pg14 of the 14th PMOS connects c2, source electrode Ps14 and connects the drain electrode Pd13 of the 13rd PMOS, drain electrode Pd14 connection the 12nd NMOS drain electrode Nd12; The grid Pg15 connection _ RN1_ of the 15th PMOS, drain electrode Pd15 connects the source electrode Ps16, source electrode Ps15 of the 16th PMOS and connects power vd D; The grid Pg16 of the 16th PMOS connects Pd11, and drain electrode Nd15 the output m1 as main latch, source electrode Ps16 of drain electrode Pd16 connection the 15th NMOS tube connect Pd15; The grid Pg17 of the 17th PMOS connects SN01, and drain electrode Pd17 connects Pd16, source electrode Ps17 and connects power vd D; The grid Pg18 connection _ RN2_ of the 18th PMOS, drain electrode Pd18 connects the source electrode Ps19, source electrode Ps18 of the 19th PMOS and connects power vd D; The grid Pg19 of the 19th PMOS connects Pd14, and drain electrode Pd19 connects the drain electrode Nd18, source electrode Ps19 of the 18th NMOS tube and connects Pd18; The grid Pg20 of the 20th PMOS connects SN02, and drain electrode Pd20 connects Pd19 and the output m1r as main latch, source electrode Ps20 connect power vd D; The grid Pg21 of the 21st PMOS connects Pd19, and drain electrode Pd21 connects the source electrode Ps22, source electrode Ps21 of the 22nd PMOS and connects power vd D; The grid Pg22 of the 22nd PMOS connects cn1, and drain electrode Pd22 connects drain electrode Nd21 and the 16 PMOS grid Pg16, source electrode Ps22 of the 21st NMOS tube and connects Pd21;The grid Pg23 of the 23rd PMOS connects Pd16, and drain electrode Pd23 connects the source electrode Ps24, source electrode Ps23 of the 24th PMOS and connects power vd D; The grid Pg24 of the 24th PMOS connects cn2, and drain electrode Pd24 connects drain electrode Nd23 and the 19 PMOS grid Pg19, source electrode Ps24 of the 23rd NMOS tube and connects Pd23; The grid Ng9 of the 9th NMOS tube connects cn1, source electrode Ns9 and connects the drain electrode Nd10 of the tenth NMOS tube, and drain electrode Nd9 connects the drain electrode Pd11 of the 11st PMOS; The grid Ng10 of the tenth NMOS tube connects D1, and drain electrode Nd10 connects the source electrode Ns9, source electrode Ns10 of the 9th NMOS tube and connects Nd11; The grid Ng11 of the 11st NMOS tube connects input D, and drain electrode Nd11 connects Ns10, source electrode Ns11 and connects VSS; The grid Ng12 of the 12nd NMOS tube connects cn2, source electrode Ns12 and connects the drain electrode Nd13 of the 13rd NMOS tube, and drain electrode Nd12 connects the drain electrode Pd14 of the 14th PMOS; The grid Ng13 of the 13rd NMOS tube connects D1, and drain electrode Nd13 connects the source electrode Ns12, source electrode Ns13 of the 12nd NMOS tube and connects Nd14; The grid Ng14 of the 14th NMOS tube connects input D, and drain electrode Nd14 connects Ns13, source electrode Ns11 and connects VSS; The grid Ng15 of the 15th NMOS tube connects Pd14, and drain electrode Nd15 connects Pd16, source electrode Ns15 and connects the drain electrode Nd17 of the 17th NMOS tube; The grid Ng16 connection _ RN2_ of the 16th NMOS tube, drain electrode Nd16 connects Pd16, source electrode Ns16 and connects Nd17; The grid Ng17 of the 17th NMOS tube connects SN02, and drain electrode Nd17 connects Ns15, source electrode Ns17 ground connection VSS; The grid Ng18 of the 18th NMOS tube connects Pd11, and drain electrode Nd18 connects Pd19, source electrode Ns18 and connects the drain electrode Nd20 of the 20th NMOS tube; The grid Ng19 connection _ RN1_ of the 19th NMOS tube, drain electrode Nd19 connects Pd19, source electrode Ns19 and connects Nd20; The grid Ng20 of the 20th NMOS tube connects SN01, and drain electrode Nd20 connects Ns18, source electrode Ns20 ground connection VSS; The grid Ng21 of the 21st NMOS tube connects c1, and drain electrode Nd21 connects Pd22, source electrode Ns21 and connects the drain electrode Nd22 of the 22nd NMOS tube; The grid Ng22 of the 22nd NMOS tube connects Pd16, and drain electrode Nd22 connects Ns21, source electrode Ns22 ground connection VSS; The grid Ng23 of the 23rd NMOS tube connects c2, and drain electrode Nd23 connects Pd24, source electrode Ns23 and connects the drain electrode Nd24 of the 24th NMOS tube; The grid Ng24 of the 24th NMOS tube connects Pd19, and drain electrode Nd24 connects Ns23, source electrode Ns24 ground connection VSS;

Described have ten inputs and two outfans, input and c1, c2, cn1, cn2, m1, m1r, _ RN1_, _ RN2_, SN01, SN02 from latch, is connected; Outfan is s1, s1r; Being made up of from latch 14 PMOS and 14 NMOS tube, from latch, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube; The grid Pg25 of the 25th PMOS connects m1r, and drain electrode Pd25 connects the source electrode Ps26, source electrode Ps25 of the 26th PMOS and connects power vd D; The grid Pg26 of the 26th PMOS connects cn1, and drain electrode Pd26 connects the drain electrode Nd25 of the 25th NMOS tube, and source electrode connects Pd25; The grid Pg27 of the 27th PMOS connects m1, and drain electrode Pd27 connects the source electrode Ps28, source electrode Ps27 of the 28th PMOS and connects power vd D; The grid Pg28 of the 28th PMOS connects cn2, and drain electrode Pd28 connects the drain electrode Nd27 of the 27th NMOS tube, and source electrode connects Pd27;The grid Pg29 connection _ RN1_ of the 29th PMOS, drain electrode Pd29 connects the source electrode Ps30, source electrode Ps29 of the 30th PMOS and connects power vd D; The grid Pg30 of the 30th PMOS connects Pd26, and drain electrode Pd30 connects the drain electrode Nd29 of the 29th NMOS tube and connects Pd29 as from the output s1 of latch, source electrode Ps30; The grid Pg31 of the 31st PMOS connects SN01, and drain electrode Pd31 connects Pd30, source electrode Ps31 and connects power vd D; The grid Pg32 connection _ RN2_ of the 32nd PMOS, drain electrode Pd32 connects the source electrode Ps33, source electrode Ps32 of the 33rd PMOS and connects power vd D; The grid Pg33 of the 33rd PMOS connects Pd28, and drain electrode Pd33 connects the drain electrode Nd32 of the 32nd NMOS tube and connects Pd32 as from the outfan s1r of latch, source electrode Ps33; The grid Pg34 of the 34th PMOS connects SN02, and drain electrode Pd34 connects Pd33 and connects outfan s1r, and source electrode Ps34 connects power vd D; The grid Pg35 of the 35th PMOS connects Pd33, and drain electrode Pd35 connects the source electrode Ps36, source electrode Ps35 of the 36th PMOS and connects power vd D; The grid Pg36 of the 36th PMOS connects c1, and drain electrode Pd36 connects drain electrode Nd35 and the 30 PMOS grid Pg30, source electrode Ps36 of the 35th NMOS tube and connects Pd35; The grid Pg37 of the 37th PMOS connects Pd30, and drain electrode Pd37 connects the source electrode Ps38, source electrode Ps37 of the 38th PMOS and connects power vd D; The grid Pg38 of the 38th PMOS connects c2, and drain electrode Pd38 connects drain electrode Nd37 and the 33 PMOS grid Pg33, source electrode Ps38 of the 37th NMOS tube and connects Pd37; The grid Ng25 of the 25th NMOS tube connects c1, and drain electrode Nd25 connects Pd26, source electrode Ns25 and connects the drain electrode Nd26 of the 26th NMOS tube; The grid Ng26 of the 26th NMOS tube connects m1, and drain electrode Nd26 connects Ns25, source electrode Ns26 ground connection VSS; The grid Ng27 of the 27th NMOS tube connects c2, and drain electrode Nd27 connects Pd28, source electrode Ns27 and connects the drain electrode Nd28 of the 28th NMOS tube; The grid Ng28 of the 28th NMOS tube connects m1r, and drain electrode Nd28 connects Ns27, source electrode Ns28 ground connection VSS; The grid Ng29 of the 29th NMOS tube connects Pd28, and drain electrode Nd29 connects Pd30, source electrode Ns29 and connects the drain electrode Nd31 of the 31st NMOS tube; The grid Ng30 connection _ RN2_ of the 30th NMOS tube, drain electrode Nd30 connects Pd30, source electrode Ns30 and connects Nd31; The grid Pg31 of the 31st NMOS tube connects SN02, and drain electrode Nd31 connects Ns29, source electrode Ns31 ground connection VSS; The grid Ng32 of the 32nd NMOS tube connects Pd26, and drain electrode Nd32 connects Pd33, source electrode Ns32 and connects the drain electrode Nd34 of the 34th NMOS tube; The grid Ng33 connection _ RN1_ of the 33rd NMOS tube, drain electrode Nd33 connects Pd33, source electrode Ns33 and connects Nd34; The grid Ng34 of the 34th NMOS tube connects SN01, and drain electrode Nd34 connects Ns32, source electrode Ns32 ground connection VSS; The grid Ng35 of the 35th NMOS tube connects cn1, and drain electrode Nd35 connects Pd34, source electrode Ns35 and connects the drain electrode Nd36 of the 36th NMOS tube; The grid Ng36 of the 36th NMOS tube connects Pd30, and drain electrode Nd36 connects Ns35, source electrode Ns36 ground connection VSS; The grid Ng37 of the 37th NMOS tube connects cn2, and drain electrode Nd37 connects Pd38, source electrode Ns37 and connects the drain electrode Nd38 of the 38th NMOS tube; The grid Ng38 of the 38th NMOS tube connects Pd33, and drain electrode Nd38 connects Ns37, source electrode Ns38 ground connection VSS;

Described output buffer has two inputs and an outfan, and input connects s1 and s1r, and outfan is Q; Output buffer is made up of two PMOS and two NMOS tube, and in output buffer, the substrate of all PMOS connects power vd D, the Substrate ground VSS of all NMOS tube; The grid Pg69 of the 69th PMOS connects s1r, and drain electrode Pd69 connects the drain electrode Nd71, source electrode Ps69 of the 71st NMOS tube and connects power vd D; The grid Pg70 of the 70th PMOS connects the drain electrode Pd69 of the 69th PMOS, and drain electrode Pd70 connects the drain electrode Nd72 of the 72nd NMOS tube, and connects power vd D as the output Q of inverter circuit, source electrode Ps70; The grid Ng71 of the 71st NMOS tube connects s1, and drain electrode Nd71 connects the drain electrode Pd69 of the 69th PMOS; The grid Ng72 of the 72nd NMOS tube connects the drain electrode Nd71 of the 71st NMOS tube, and drain electrode Nd72 connects the drain electrode Pd70, source electrode Ns72 of the 70th PMOS and connects VSS.