CN1037923C - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN1037923C CN1037923C CN95106329A CN95106329A CN1037923C CN 1037923 C CN1037923 C CN 1037923C CN 95106329 A CN95106329 A CN 95106329A CN 95106329 A CN95106329 A CN 95106329A CN 1037923 C CN1037923 C CN 1037923C
- Authority
- CN
- China
- Prior art keywords
- conduction type
- well region
- semiconductor chip
- type
- deep trouth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000000034 method Methods 0.000 title claims description 13
- 239000012535 impurity Substances 0.000 claims description 15
- 230000005611 electricity Effects 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000003860 storage Methods 0.000 claims description 2
- 238000002513 implantation Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 14
- 230000010354 integration Effects 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 210000003323 beak Anatomy 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000004043 responsiveness Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- -1 phosphonium ion Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007634 remodeling Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
一种半导体器件包括:一P型半导体基片、第一和第二P阱、介于第一和第二P阱之间的N阱、用于使各阱相互电隔离及使第一阱与P型半导体基片电隔离的深槽元件隔离膜、以及在第一P阱之下所形成的介于深槽元件隔离膜的N型隐埋区,它适合于高集成化,并改善运作速度。
Description
本发明一般涉及一种半导体器件,特别涉及半导体器件的动作速度及其高集成化的改进。本发明还涉及制造该半导体器件的方法。
通常采用CMOS(互补MOS)晶体管作为半导体存储器件的***电路,因为其功耗小、动作速度快。
关于CMOS晶体管的结构,首先在P型半导体基片中形成一N阱和一P阱。然后,在N阱的预定部位内形成另一P阱,以分别在N阱和P阱上建成一P型MOSFET和一N型MOSFET。在N阱预定部位内形成P阱容许对P型半导体基片和对P阱施加不同的电压,这是由于N阱使P阱与P型基片电隔离。
为更好地了解本发明的技术背景,下面结合图1介绍制造半导体器件的常规方法。
首先,参照图1A,该图表示利用N阱掩模的离子注入工艺。如该图所示,N型杂质被注入到被覆以N型掩模的P型半导体基片1的预定面积,形成一N阱区域2。
参照图1B,采用P阱掩模,使P型杂质注入到P型基片1的邻近N阱区域2的预定面积和N阱区域内,分别形成比N阱区域浅的第一P阱区域3A和第二P阱区域3B。
参照图1C,在N阱区域2和第一P阱区域3A之间边界及N阱区域2)和第二P阱区3B之间的边界通过LOCOS(硅局部氧化)工艺形成隔离元件用的绝缘膜4,在P型基片的预定表面上形成栅结构,它包括栅氧化膜5和栅电极6,并进行离子注入处理。对N阱区域注入P型杂质,建立源/漏极8,于是获得一P型MOSFET。另一方面,使N型杂质注入到第一P阱区3A及第二P阱区域3B,以建立源/漏极7,于是得到N型MOSFET。
然而,这种常规方法难以获得高集成化的半导体器件,因为用LOCOS工艺所形成的隔离元件的绝缘膜还有鸟嘴产生。此外,在N阱区域内的第二P阱区域,除P型杂质外还含有N型杂质,导致N型MOSFET的迁移率的退化。
所以,本发明的目的在于克服上述已有技术中所遇到的问题,提供宜于高集成化的半导体器件并改进MOSFET的迁移率。
本发明的另一目的在于提供制造该半导体器件的方法。
根据本发明的一个方案,所提供的一种半导体器件包括:一第一导电类型的半导体基片;在所说的半导体基片的预定面积内所形成的第二导电类型的阱区;第一导电类型的第一阱区和第一导电类型的第二阱区,每一所述阱区都形成在除所述半导体基片的第二导电类型的所述阱区的相对侧面 之外的位置上;深槽元件隔离膜,分别形成在所说的第二导电类型的阱区和所说的第一导电类型的第一阱区之间、在所说的第二导电类型的阱区和所说的第一导电类型的的第二阱区之间、及在所说的第一导电类型的第二阱区和所说的第一导电类型的半导体基片之间的边界上;以及在所说的第一导电类型的第二阱区之下所形成的第二导电类型的隐埋区,用来使所说的第二阱区与所说的第一导电类型的半导体基片在电学上隔离。
根据本发明的另一方案,提供一种制造该半导体器件的方法,包括以下各步骤:刻蚀第一导电类型的半导体基片的预定面积,形成用于不同导电类型各阱区间隔离的深槽;用隔离膜填入隔离深槽,形成深槽元件隔离膜;用隔离膜填入隔离深槽,形成深槽元件隔离膜;在所说的半导体基法被所说的深槽割断的第一区段内形成第二导电类型的一个阱区;在所说的半导体基片的第二区段内形成第二导电类型的隐埋区,所说的第二区段邻近第一区段,但与之在电学上是隔离的;以及在所说的半导体基片的第三区段和所说的第二区段的隐埋区之上同时形成第一导电类型的第二阱区,所说的第三区段邻近第一区段,但与之在电学上是隔离的。
参照附图,通过对本发明的优选实施例的详细说明会更加明了本发明的上述目的和其它优点。
图1A~1C是表示制造含有N阱和P阱的常规半导体器件的工艺步骤的示意剖面图;及
图2A~2D是表示根据本发明制造含有N阱和P阱的半导体器件的工艺步骤的示意剖面图。
参照附图,对本发明优选实施例的用途会有更深的了解,图中相同的标号分别用来表示相同的对应部分。
图2表示制造半导体器件的优选工艺步骤。现结合附图2A~2D详细说明这些步骤。
首先,如图2A所示,在P型半导体基片11的预定部位内形成如约2.0~6.0μm深的深槽9,然后填以绝缘体如氧化膜或氮化膜,以建成深槽元件隔离膜10。如下文所述,每个深槽元件隔离膜介于CMOS的N阱和P阱之间,以达到使N阱与其它类型阱的绝缘之目的。采用光刻技术可使元件隔离膜形成得尽可能的窄。
其次,参照图2B,以150Kev的注入能量并经扩散处理使磷离子注入到被第二和第三深槽元件隔离膜10限定的面积,这对应于图1B中的除第二阱区3B以外的N阱区2,使浓度达到1016cm-3,形成深约1.5~5.0μm的N阱区12。然后,以700~3,000KeV的注入能量使N型杂质注入到由第一和第二深槽元件隔离膜10所限定的面积,使浓度达到如1016~1018cm-3,形成距基片表面3~4.5μm深的约1~2μm厚的N型隐埋区12A。这个N型隐埋区使P型半导体基片与后面步骤形成的第二P阱电隔离。第一和第二深槽元件隔离膜10在该剖面图中看来好像是相互分开的,但实际上是相互连接的圆筒结构。
接着,参照图2C,使P型杂质注入到半导体基片11的预定面积,形成第一P阱区13A及N型隐埋区12A上面的第二P阱区13B。该P阱区13A是如此之浅,如1.0~4.5μm,以致不与N型隐埋区12A相接。该P阱区13B的深度与P阱区13A的深度相同。致于第一P阱区13A和第二P阱13B的离子浓度可以相同,或可以相互不同,其浓度可达到约1016~1018cm-3。其结果,使第二P阱区13B的N型杂质只有10/cm3之低,并靠N型隐埋区12A与半导体基片11电隔离,并进一步借助于深槽元件隔离膜10与相邻的N阱区12电隔离。
最后,参照图2D,该图表示一MOSFET结构。对于存储器件的情况,在每一P阱区13A的表面预定部位形成一元件隔离膜14,作为单元区域的元件隔离膜。在每个阱上建立一由栅氧化膜15和栅电极16构成的栅结构。此后,使P型杂质注入到N阱区12形成P型MOSFET的源/漏极18。反之,使N型杂质注入到第一和第二P阱区13A和13B,形成N型MOSFET的各自的源/漏极17。
当然,根据本发明,在N阱的杂质类型与P阱的杂质类型相互交换的条件下,可以用N型半导体基片取代P型半导体基片。
如前文所述,根据本发明的半导体器件在CMOS的N阱和P阱之间的边界具有深槽元件隔离膜,无鸟嘴,有助于高集成化。在已有技术中,一P阱是在N阱内形成的,因而,在P阱内留有大量的N型杂质,降低了N型MOSFET的迁移率。相反,本发明在有深槽元件隔离膜的情况下,使P阱直接形成在P型半导体基片内,使得N型杂质变得尽可能的少,因此,提高了器件的动作速度。
对本领域的技术人员在阅读前文说明之后,会容易明了本文公开的本发明的其它特性、优点以及实施方案。就此而论,虽然非常详细地说明了本发明的具体实施方案,在不脱离说明本所说明和权利要求和所请求保护的本发明的精神和范畴前提下,对本发明可做出各种变化和改型。
Claims (11)
1.一种半导体器件,该器件包括:
一个第一导电类型的半导体基片;
在所说的半导体基片的预定面积内所形成的一个第二导电类型的阱区;
第一导电类型的一个第一阱区和第一导电类型的一个第二阱区,它们形成在除所述半导体基片的所述第二导电类型的所述阱区的相对侧面之外的位置上;以及
分别形成在所说的第二导电类型的阱区和所说的第一导电类型的第一阱区之间、在所说的第二导电类型的阱区和所说的第一导电类型的第二阱区、以及在所说的第一导电类型的第二阱区和所说的第一导电类型的半导体基片之间的各边界上的深槽元件的隔离膜,
其特征在于,在所说的第一导电类型的第二阱区之下所形成的第二导电类型的隐埋区,用于使所说的第二阱区与所说的第一导电类型的半导体基片的电隔离。
2.根据权利要求1的半导体器件,其中所说的第一导电类型是P型,而所说的第二导电类型是N型。
3.根据权利要求1的半导体器件,其中所说的深槽元件隔离膜比所说的第二导电类型的阱区深,以便所说的第二导电类型的阱区与所说的第一导电类型的第一阱区及所说的第一导电类型的第二阱区电隔离,并使所说的第二导电类型的阱区侧表面与邻近的半导体基片电隔离。
4.根据权利要求1的半导体器件,其中所说的第一导电类型的第一和第二阱区处于比所说的第二导电类型的隐埋区浅的位置。
5.根据权利要求1的半导体器件,其中所说的第二导电类型的隐埋区介于所说的深槽元件隔离膜之间且位于所说的第一导电类型的第二阱区之下。
6.一种制造半导体器件的方法,该法包括以下各工艺步骤:
刻蚀第一导电类型的半导体基片的预定面积,形成用于不同导电类型阱区之间隔离的深槽;
用绝缘膜填充所说的各深槽,形成深槽元件隔离膜;
在被所说的深槽分割的半导体基片第一区段内形成第二导电类型的阱区;
在所说的半导体基片的第二区段形成第二导电类型的隐埋区,所说的第二区段与第一区段相邻但在电学上是隔离的;以及
在所说的半导体基片的第三区段内形成第一导电类型的第一阱区,同时在所说的第二区段的隐埋区之上形成第一导电类型的第二阱区,所说的第三区段与所说的第一区段相邻但在电学上是隔离的。
7.根据权利要求6的方法,其中所说的第二区段的阱区深约1.5~5.0μm。
8.根据权利要求6的方法,其中所说的第二导电类型的隐埋区厚约1~2μm,距所说的半导体基片上表面约3~4.5μm,是以700~3000Kev的注入能量注入浓度为1016~1018cm-3第一导电类型的杂质而形成的。
9.根据权利要求6的方法,其中所说的第一导电类型的第一阱区和第一导电类型的第二阱区深约1.0~4.5μm,其杂质浓度为1016~1018cm-3。
10.根据权利要求6的方法,其中所说的深槽约2-6μm。
11.根据权利要求6的方法,其中所说的深槽元件隔离膜只形成在半导体存储器件的***电路内。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR94-12821 | 1994-06-08 | ||
KR1019940012821A KR0131723B1 (ko) | 1994-06-08 | 1994-06-08 | 반도체소자 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1119347A CN1119347A (zh) | 1996-03-27 |
CN1037923C true CN1037923C (zh) | 1998-04-01 |
Family
ID=19384852
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN95106329A Expired - Fee Related CN1037923C (zh) | 1994-06-08 | 1995-06-08 | 半导体器件及其制造方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US5525532A (zh) |
KR (1) | KR0131723B1 (zh) |
CN (1) | CN1037923C (zh) |
DE (1) | DE19520958C2 (zh) |
GB (1) | GB2290165B (zh) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5573963A (en) * | 1995-05-03 | 1996-11-12 | Vanguard International Semiconductor Corporation | Method of forming self-aligned twin tub CMOS devices |
US5573962A (en) * | 1995-12-15 | 1996-11-12 | Vanguard International Semiconductor Corporation | Low cycle time CMOS process |
US5753956A (en) * | 1996-01-11 | 1998-05-19 | Micron Technology, Inc. | Semiconductor processing methods of forming complementary metal oxide semiconductor memory and other circuitry, and memory and other circuitry |
US5612242A (en) * | 1996-03-11 | 1997-03-18 | United Microelectronics Corp. | Trench isolation method for CMOS transistor |
EP0831518B1 (en) * | 1996-09-05 | 2006-03-01 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for producing the same |
KR100239402B1 (ko) * | 1997-04-02 | 2000-02-01 | 김영환 | 반도체 소자의 웰과 그 형성방법 |
GB2327146A (en) * | 1997-07-10 | 1999-01-13 | Ericsson Telefon Ab L M | Thermal insulation of integrated circuit components |
JPH11274418A (ja) * | 1998-03-25 | 1999-10-08 | Nec Corp | 半導体装置 |
JP2000091443A (ja) * | 1998-09-14 | 2000-03-31 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
GB2344689A (en) | 1998-12-07 | 2000-06-14 | Ericsson Telefon Ab L M | Analogue switch |
US6144086A (en) * | 1999-04-30 | 2000-11-07 | International Business Machines Corporation | Structure for improved latch-up using dual depth STI with impurity implant |
DE10225860B4 (de) * | 2001-06-11 | 2006-11-09 | Fuji Electric Co., Ltd., Kawasaki | Halbleiterbauteil |
US6885078B2 (en) * | 2001-11-09 | 2005-04-26 | Lsi Logic Corporation | Circuit isolation utilizing MeV implantation |
KR100864048B1 (ko) | 2002-06-26 | 2008-10-17 | 세미이큅, 인코포레이티드 | 이온 소스 |
US6686595B2 (en) | 2002-06-26 | 2004-02-03 | Semequip Inc. | Electron impact ion source |
US7825488B2 (en) | 2006-05-31 | 2010-11-02 | Advanced Analogic Technologies, Inc. | Isolation structures for integrated circuits and modular methods of forming the same |
JP4755405B2 (ja) * | 2004-10-13 | 2011-08-24 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5375402B2 (ja) * | 2009-07-22 | 2013-12-25 | 富士通セミコンダクター株式会社 | 半導体装置とその製造方法 |
NZ743463A (en) * | 2012-08-28 | 2019-09-27 | Janssen Sciences Ireland Uc | Sulfamoyl-arylamides and the use thereof as medicaments for the treatment of hepatitis b |
CN104282734B (zh) * | 2014-09-24 | 2018-02-06 | 上海华虹宏力半导体制造有限公司 | 与cmos工艺兼容的沟道隔离的原生器件及其制造方法 |
CN104362095B (zh) * | 2014-11-05 | 2017-12-01 | 北京大学 | 一种隧穿场效应晶体管的制备方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5015594A (en) * | 1988-10-24 | 1991-05-14 | International Business Machines Corporation | Process of making BiCMOS devices having closely spaced device regions |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1457139A (en) * | 1973-09-27 | 1976-12-01 | Hitachi Ltd | Method of manufacturing semiconductor device |
JPS5275989A (en) * | 1975-12-22 | 1977-06-25 | Hitachi Ltd | Production of semiconductor device |
US4140558A (en) * | 1978-03-02 | 1979-02-20 | Bell Telephone Laboratories, Incorporated | Isolation of integrated circuits utilizing selective etching and diffusion |
JPS6083346A (ja) * | 1983-10-14 | 1985-05-11 | Hitachi Ltd | 半導体集積回路装置 |
DE3583575D1 (de) * | 1984-10-17 | 1991-08-29 | Hitachi Ltd | Komplementaere halbleiteranordnung. |
GB8426897D0 (en) * | 1984-10-24 | 1984-11-28 | Ferranti Plc | Fabricating semiconductor devices |
US4808548A (en) * | 1985-09-18 | 1989-02-28 | Advanced Micro Devices, Inc. | Method of making bipolar and MOS devices on same integrated circuit substrate |
US4825275A (en) * | 1987-05-28 | 1989-04-25 | Texas Instruments Incorporated | Integrated bipolar-CMOS circuit isolation for providing different backgate and substrate bias |
JP2666384B2 (ja) * | 1988-06-30 | 1997-10-22 | ソニー株式会社 | 半導体装置の製造方法 |
US5006476A (en) * | 1988-09-07 | 1991-04-09 | North American Philips Corp., Signetics Division | Transistor manufacturing process using three-step base doping |
US4960726A (en) * | 1989-10-19 | 1990-10-02 | International Business Machines Corporation | BiCMOS process |
US5250837A (en) * | 1991-05-17 | 1993-10-05 | Delco Electronics Corporation | Method for dielectrically isolating integrated circuits using doped oxide sidewalls |
JP2740087B2 (ja) * | 1992-08-15 | 1998-04-15 | 株式会社東芝 | 半導体集積回路装置の製造方法 |
-
1994
- 1994-06-08 KR KR1019940012821A patent/KR0131723B1/ko not_active IP Right Cessation
-
1995
- 1995-06-06 US US08/468,552 patent/US5525532A/en not_active Expired - Lifetime
- 1995-06-07 GB GB9511563A patent/GB2290165B/en not_active Expired - Fee Related
- 1995-06-08 CN CN95106329A patent/CN1037923C/zh not_active Expired - Fee Related
- 1995-06-08 DE DE19520958A patent/DE19520958C2/de not_active Expired - Fee Related
-
1996
- 1996-02-08 US US08/598,551 patent/US5726476A/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5015594A (en) * | 1988-10-24 | 1991-05-14 | International Business Machines Corporation | Process of making BiCMOS devices having closely spaced device regions |
Also Published As
Publication number | Publication date |
---|---|
DE19520958C2 (de) | 1997-09-11 |
DE19520958A1 (de) | 1995-12-14 |
KR960002556A (ko) | 1996-01-26 |
CN1119347A (zh) | 1996-03-27 |
GB2290165B (en) | 1998-07-29 |
GB2290165A (en) | 1995-12-13 |
GB9511563D0 (en) | 1995-08-02 |
US5726476A (en) | 1998-03-10 |
US5525532A (en) | 1996-06-11 |
KR0131723B1 (ko) | 1998-04-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1037923C (zh) | 半导体器件及其制造方法 | |
JP3513212B2 (ja) | 半導体装置の製法 | |
KR100458410B1 (ko) | 반도체 장치의 제조 방법 | |
US6798037B2 (en) | Isolation trench structure for integrated devices | |
KR100432887B1 (ko) | 다중격리구조를 갖는 반도체 소자 및 그 제조방법 | |
CN1090383C (zh) | 半导体器件及其制造方法 | |
US4845045A (en) | Method of fabricating electrically-programmable element in a semiconductor integrated circuit using a doped plug to extend the depth of a doped region | |
US20040053439A1 (en) | Method for producing low-resistance ohmic contacts between substrates and wells in CMOS integrated circuits | |
CN1112292A (zh) | 半导体器件及其制造方法 | |
KR19990088300A (ko) | Soi-반도체장치및그것의제조방법 | |
CN1199926A (zh) | 一种半导体器件的制造方法 | |
KR100563162B1 (ko) | 반도체장치및그제조방법 | |
CN1574294A (zh) | 半导体记忆元件及其记忆胞编程方法和罩幕式只读存储器 | |
EP0081999A2 (en) | A method of fabricating a MOS transistor on a substrate | |
KR20040076300A (ko) | 반도체 소자의 금속 배선 형성 방법 | |
CN1216866A (zh) | 在阱区间无台阶的半导体器件 | |
JPH0485968A (ja) | Mos型半導体装置およびその製造方法 | |
KR100899533B1 (ko) | 고전압 소자 및 그 제조방법 | |
KR0138310B1 (ko) | 바이폴라 트랜지스터의 제조방법 | |
KR100268866B1 (ko) | 반도체 소자 및 이의 제조방법 | |
KR100260366B1 (ko) | 반도체 소자의 제조 방법 | |
KR100211148B1 (ko) | 바이모오스 반도체 메모리장치의 제조방법 | |
KR100444772B1 (ko) | 상보형 모스 트랜지스터의 제조방법 | |
KR0172619B1 (ko) | 반도체 장치 및 그 성형방법 | |
JP2982421B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 19980401 Termination date: 20130608 |