CN103650335B - 压电装置 - Google Patents

压电装置 Download PDF

Info

Publication number
CN103650335B
CN103650335B CN201280034749.7A CN201280034749A CN103650335B CN 103650335 B CN103650335 B CN 103650335B CN 201280034749 A CN201280034749 A CN 201280034749A CN 103650335 B CN103650335 B CN 103650335B
Authority
CN
China
Prior art keywords
element mounting
region
component
pattern
piezo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201280034749.7A
Other languages
English (en)
Other versions
CN103650335A (zh
Inventor
新山高弘
新德弘伸
笹川亮磨
小村顺平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Crystal Device Corp
Original Assignee
Kyocera Crystal Device Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2011188447A external-priority patent/JP5767061B2/ja
Priority claimed from JP2012102901A external-priority patent/JP5828480B2/ja
Application filed by Kyocera Crystal Device Corp filed Critical Kyocera Crystal Device Corp
Publication of CN103650335A publication Critical patent/CN103650335A/zh
Application granted granted Critical
Publication of CN103650335B publication Critical patent/CN103650335B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0547—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0547—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
    • H03H9/0552—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement the device and the other elements being mounted on opposite sides of a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81439—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0504—Holders; Supports for bulk acoustic wave devices
    • H03H9/0514—Holders; Supports for bulk acoustic wave devices consisting of mounting pads or bumps

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Acoustics & Sound (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本发明所涉及的压电装置（100）包括：元件搭载构件（110）、搭载于元件搭载构件（110）的压电元件（120）、形成于元件搭载构件（110）表面且包含元件搭载区域（118a）及走线区域（118b）的金属图案（118）、利用焊料凸点（132）与金属图案（118）的元件搭载区域（118a）电连接的集成电路元件（130），金属图案（118）具有设置于元件搭载区域（118a）与走线区域（118b）之间的凸部（119），凸部（119）的至少表面部分由金属氧化物构成。

Description

压电装置
技术领域
本发明涉及一种应用于电子设备等的压电装置。
背景技术
以往，在例如便携式的电子设备中使用各种压电装置。现有的压电装置包含：元件搭载构件、收容于元件搭载构件的第1凹部内的压电元件、收容于元件搭载构件的第2凹部内的集成电路元件。
元件搭载构件中设有用于搭载集成电路元件的金属图案。集成电路元件通过焊料凸点来与金属图案相接合。焊料凸点在加热工序中熔融，之后冷却固化。
现有技术文献
专利文献
专利文献1：日本专利申请特开2009-267866号公报
发明内容
发明所要解决的技术问题
然而，现有的压电装置中，例如在利用焊料凸点将集成电路元件与金属图案相接合后，可能在回流等中进行多次250度左右的加热工序，由此，焊料凸点可能再次熔融。其结果是，再次熔融的焊料凸点扩散至金属图案上，使得集成电路元件与金属图案的接合的可靠性下降。
解决技术问题所采用的技术方案
本发明的实施方式1所涉及的压电装置包含：元件搭载构件、搭载于元件搭载构件的压电元件、形成于元件搭载构件表面的金属图案以及利用焊料凸点与金属图案电连接的集成电路元件。金属图案包含元件搭载区域以及走线区域。集成电路元件与金属图案的元件搭载区域电连接。金属图案在元件搭载区域与走线区域之间设有凸部，至少凸部的表面部分由金属氧化物构成。
本发明的实施方式2所涉及的压电装置包含：元件搭载构件、搭载于元件搭载构件的压电元件、设置于元件搭载构件的表面且包含元件搭载区域及布线区域的金属图案、以及集成电路元器件，该集成电路元器件利用焊料凸点与金属图案的元件搭载区域电连接，且包含集成电路元件与设置于集成电路元件下表面的边缘部上的导体图案。金属图案还包含焊料流动防止区域，该焊料流动防止区域设置于元件搭载区域与布线区域之间。焊料流动防止区域设置于俯视时与集成电路元器件的导体图案相重叠的位置或较导体图案更靠内侧的位置。
发明效果
在本发明的实施方式1所涉及的压电装置中，在至少具有由例如镍(Ni)等焊料浸润性较差的金属氧化物构成的表面部分的凸部，熔融的焊料凸点的扩散得到抑制。其结果是，集成电路元件与金属图案的接合的可靠性有所提高。
在本发明的实施方式2所涉及的压电装置中，焊料与导体图案接触的可能性减小，由此，集成电路元件的多个电极衬垫发生短路的可能性减小。
附图说明
图1是表示本发明的实施方式1中的压电装置的一个示例的剖视图。
图2是图1所示的压电装置的元件搭载构件的仰视图。
图3是图2中由标号B所示部分的放大图。
图4是图3的Y-Y线纵向剖视图。
图5是表示本发明的实施方式2中的压电装置的纵向剖视图。
图6(a)是表示图5所示的压电装置中的集成电路元件的俯视图，图6(b)是表示图5所示的压电装置中的集成电路元件的电连接示例的俯视图。
图7是表示图5所示的压电装置的连接部的接合状态的纵向剖视图。
具体实施方式
下面，参照附图对本发明的示例性的实施方式进行说明。
(实施方式1)
如图1所示，本发明的实施方式1中的压电装置100包含：元件搭载构件110、搭载于元件搭载构件110的压电元件120及集成电路元件130、以及盖构件150。此外，图1示出了图2所示的压电装置的A-A线纵向剖视图。
元件搭载构件110包含：基板部111、设置于基板部111的一个主面上的第1框部112以及设置于基板部111的另一个主面上的第2框部113。构成元件搭载构件110的基板部111、第1框部112以及第2框部113例如由玻璃-陶瓷、铝陶瓷等陶瓷材料构成。
另外，基板部111配置有用于在一个主面上搭载压电元件120的压电元件搭载用图案114，还配置有用于在另一个主面上搭载集成电路元件130的金属图案118。此外，在另一个主面上，在压电装置100的制造工序中还设有用于对压电元件120进行检查的监视用端子123。另外，如图2所示，基板部111的另一个主面上例如配置有3行2列6个金属图案118。图1中示出了将金属图案118的1列以横切方式切断的剖视图。配置于元件搭载构件110的金属图案118通过焊料凸点132与后述的集成电路元件130的电极衬垫134相接合。另外，在基板部111的内部设有内层布线(未图示)，压电元件搭载用图案114与金属图案118通过内层布线(未图示)电连接。
另外，元件搭载构件110具有由基板部111及第1框部112包围的第1凹部K1。第1凹部K1中收容有压电元件120。收容压电元件120的第1凹部K1由盖构件150气密密封。
另外，元件搭载构件110具有由基板部111及第2框部113包围的第2凹部K2。第2凹部K2中收容有集成电路元件130。第2框部113的四角设有多个外部连接端子116。多个外部连接端子116分别起到VCC端子、VCON端子、OUT端子、接地端子的作用。
VCC端子上施加电源电压。VCON端子上施加用于控制集成电路元件130的输出状态的信号(即、控制信号)。OUT端子上施加从集成电路元件130输出的信号。接地端子上施加接地电压。
压电元件120在压电原板的两个主面上包括激振用电极(未图示)与连接用电极(未图示)。另外，压电元件120的连接用电极(未图示)与压电元件搭载用图案114相连接，该压电元件搭载用图案114通过导电性粘接剂121配置于元件搭载构件110。另外，在规定的结晶轴上来自外部的变动电压被施加至经过切割的压电原板的情况下，压电元件120激发出规定频率的厚度切变振动。压电原板例如使用水晶。
集成电路元件130至少包括振荡电路。集成电路元件130在形成电路的面上形成电极衬垫134。电极衬垫134通过焊料凸点132与配置于元件搭载构件110的金属图案118相接合。另外，集成电路元件130的电极衬垫134与配置于元件搭载构件110的金属图案118之间填充有树脂140。
焊料凸点132通过丝网印刷形成于形成有集成电路元件130的电路的面上的电极衬垫134上，所形成的焊料凸点尺寸为凸点直径例如为80～100μm左右，高度例如为60～100μm左右。另外，本实施方式所用的焊料凸点132例如使用具有Sn-Cu-Ni类组成的无铅焊料。
盖构件150将由基板部111及第1框部112形成的第1凹部K1气密密封。盖构件150的材质由42合金或可伐合金、磷青铜等构成。
这里，如图1、图2所示，配置于压电装置100的元件搭载构件110上的金属图案118包括元件搭载区域118a及走线区域118b。元件搭载区域118a上电连接有焊料凸点132。
走线区域118b与元件搭载构件110的内层布线(未图示)相连接。此外，例如，6个走线区域118b中的4个通过内层布线(未图示)等与4个外部连接端子116相连，剩下的2个通过内层布线(未图示)等与压电元件搭载用图案114相连。此外，与压电元件搭载用图案114相连的走线区域118b通过内层布线(未图示)等还与监视用端子123相连。
另外，如图3、图4所示，金属图案118具有凸部119，该凸部119设于元件搭载区域118a与走线区域118b之间，至少凸部119的表面部分由金属氧化物构成。由此，由于凸部119形成为坝的物理性作用及其金属氧化物不易浸润的化学性作用，使得本实施方式中的压电装置100能够抑制构成焊料凸点132的焊料发生扩散。
另外，图4示出了本实施方式中的压电装置100的金属图案118的剖面的放大图。本实施方式中的金属图案118包括设置于元件搭载区域118a与走线区域118b之间的凸部119。金属图案118具有3层结构，例如，在下层形成钼(Mo)、例如在中间层形成镍(Ni)，例如在上层形成金(Au)。
由此，本实施方式中的压电装置100的凸部119将激光照射至金属图案118，对金属图案118的中间层例如镍(Ni)及上层例如金(Au)进行切割，从而在金属图案118上设置沟部117。金属图案118的中间层的例如镍(Ni)被激光切割，并通过发热与空气反应，从而生成凸部119的金属氧化物。另外，本实施方式中的凸部119在金属图案118的元件搭载区域118a一侧具有元件搭载区域侧面119a，在走线区域118b一侧具有走线区域侧面119b。
另外，图3示出了本实施方式中的压电装置100的金属图案118的上表面的放大图。本实施方式中的金属图案118包括：设置于元件搭载区域118a与走线区域118b之间的凸部119、以及形成于较凸部119更靠走线区域118b一侧的沟部117。这里，对于本实施方式中的压电装置100的凸部119，形成于元件搭载区域118a一侧的元件搭载区域侧面119a具有多个凹部119c，俯视时，多个凹部119c均以朝向走线区域118b的方向变窄的方式凹陷。另外，沟部117形成为由多个微小的凹凸构成的形态。俯视时，沟部117的多个微小的凹凸具有在假设焊料从元件搭载区域118a向走线区域118b的方向流出的情况下、能阻碍该流动的曲线形态。
本实施方式中的压电装置100的凸部119的高度例如为1～2μm左右，沟部117的深度例如为0.5～1μm左右，沟部117的宽度例如为30～50μm左右。另外，本实施方式中的压电装置100的凸部119在例如通过激光照射来形成的情况下，通过改变激光的光斑直径或输出强度等来调整高度或倾斜度。同样，多个凹部119c的形状、沟部117的宽度或深度也能通过改变激光的光斑直径或输出强度等来调整。这里，激光可以使用例如二氧化碳气体激光、YAG激光、YVO4激光、半导体激光或准分子激光等。
由此，配置于本实施方式中的压电装置100的元件搭载构件110上的金属图案118具有凸部119，该凸部119设于元件搭载区域118a与走线区域118b之间，至少凸部119的表面部分由金属氧化物构成。由此，对于本发明的实施方式中的压电装置100，凸部119的金属氧化物例如由镍(Ni)等焊料浸润性较低且经氧化的金属构成，因此能够抑制熔融的焊料凸点132在凸部19发生扩散。其结果是，本实施方式中的压电装置100能够确保集成电路元件130的电极衬垫134与焊料凸点132的接合部分的面积，并能抑制焊料凸点132的接合强度的下降。
另外，对于本实施方式中的压电装置100的凸部119，具有元件搭载区域侧面119a，在元件搭载区域侧面119a上具有多个凹部119c，俯视时，多个凹部119c均以朝向走线区域118b的方向变窄的方式凹陷。由此，焊料凸点132在加热工序中熔融，从而从元件搭载区域118a发生扩散，此时，通过焊料的表面张力能抑制焊料的扩散。
此外，本实施方式中的压电装置100的凸部119具有元件搭载区域侧面119a及走线区域侧面119b，元件搭载区域侧面119a相较于走线区域侧面119b，倾斜得更急剧。由此，本实施方式中的压电装置100的凸部119能抑制焊料凸点132的扩散。
另外，本实施方式中的压电装置100的金属图案118具有沟部117，沟部117设置于较凸部119更靠近走线区域118b一侧。由此，本发明实施方式中的压电装置100的金属图案118中，即使在凸部119的元件搭载区域侧面119a处形成焊料凸点132的焊料不停止扩散，在沟部117处形成焊料凸点132的焊料停止扩散，由此也能抑制焊料向走线区域118b扩散。
此外，如图3所示，本实施方式中的压电装置100的沟部117通过形成多个微小的凹凸，从而即使焊料凸点132扩散到超过元件搭载区域侧面119a，也能利用沟部117的多个微小凹凸来抑制焊料凸点132发生扩散。另外，本实施方式中的沟部117的多个微小凹凸形成在抑制焊料流动的方向上，使得多个微小凹凸能阻止焊料的流动。
(实施方式2)
图5是表示实施方式2所涉及的压电装置201的与图1相同的剖视图。此外，在实施方式2中，对与实施方式1的结构相同或类似的结构标注与实施方式1相同的标号，并可能省略说明。
压电装置201与实施方式1中的压电装置100的不同之处仅在于具有导体图案124。此外，在压电装置201中未设有树脂140，但也可以在压电装置201设置树脂140。
如图6所示，导体图案124设置于集成电路元件130的下表面(利用焊料凸点132进行接合的一侧的面)的边缘部。此外，下面可能将集成电路元件130及导体图案124的组合称作集成电路元器件131。图6中，多个电极衬垫134与导体图案124利用虚线以透过集成电路元件130的一部分的状态进行表示。例如在集成电路元件130是通过从晶圆中切割出而制成的情况下，导体图案124有助于降低晶圆的弯折。导体图案124接地或处于电游离状态。
这里，参照图6(b)、图7对本实施方式的压电装置201中的集成电路元件130的多个电极衬垫134及导体图案124、与设置于基板部111上表面的金属图案118的凸部119等的位置关系进行说明。此外，下面，可能将凸部119、与焊料的浸润性相对较低的金属氧化物或沟部117或者其组合称作为焊料流动防止区域151。
如图6(b)所示，集成电路元器件131设置于第2凹部K2。另外，集成电路元件130的多个电极衬垫134位于靠近第2凹部K2的长边的区域。设置于集成电路元件130下表面的边缘部的导体图案124被设置成在多个电极衬垫134的外侧包围多个电极衬垫134。
这里，焊料流动防止区域151形成于与导体图案124相重叠的位置或较导体图案124更靠近内侧的位置。例如，至少焊料流动防止区域151的朝向元件搭载构件110内侧的边缘形成于较导体图案124更靠近内侧的位置。
由此，本实施方式的压电装置201在较集成电路元件130的导体图案124更靠近内侧的位置上，通过金属图案118的焊料流动防止区域151来阻止焊料流动，因此，能利用导体图案124来降低集成电路元件130的多个电极衬垫134发生短路的可能性。
在上述实施方式1及实施方式2之外可以在不脱离本发明主旨的范围内进行各种改变或改进等。例如，金属图案118示出了3层结构，但也可以是4层结构的多层结构。另外，金属图案118的3层结构的组成也并不局限于例如下层为钼(Mo)、中间层为镍(Ni)，而上层为金(Au)，也可以是其它金属的组合。例如，金属图案118也可以是下层为钨(W)、中间层为铜(Cu)，而上层为银(Ag)等组合。另外，上述实施方式所示的压电装置100或201的第1凹部K1所搭载的压电元件120在俯视时为呈在矩形的压电原板的两主面上包括激振用电极及连接用电极的结构，但并不局限于此，例如，也可以是在俯视形状为圆形、音叉形的压电原板上设置有各种电极的形态的压电元件，或者也可以不使用压电元件而使用弹性表面波元件。
另外，焊料流动防止区域151除了通过激光照射来形成以外，例如也可以通过在金属图案118上形成绝缘层或金属层，并设置凸部等来构成。
作为绝缘层可以列举出例如陶瓷涂敷层(例如氧化铝涂敷层)或树脂等。陶瓷涂敷层或树脂通过丝网印刷设置于金属图案118上。陶瓷涂敷层或树脂等能通过丝网印刷来同时形成多个绝缘层，因此能实现降低制造成本。此外，绝缘层与金属图案相比，与焊料的浸润性较低，因此能进一步减少焊料的流动。
另外，金属层例如由Al膜或Cr膜等通过溅射法等真空印刷法来形成。由于Al膜或Cr膜等能通过溅射法等同时形成多个金属层，因此，能实现降低制造成本。
此外，在利用激光进行的形成方法中，通过利用激光来切割金属图案118能形成凸部，因此，无需另外准备用于形成凸部的材料，从而可以通过减少构件来提高生产性。另外，在利用激光进行的形成方法中，对形成有金属图案118的元件搭载构件110的后续加工过程中形成凸部，因此，例如能根据集成电路元件130的尺寸来确定焊料流动防止区域151的形成位置等，制造的自由度得到了提高。
标号说明
100、201 压电装置
110 元件搭载构件
111 基板部
112 第1框部
113 第2框部
114 压电元件搭载用图案
116 外部连接端子
117 沟部
118 金属图案
118a 元件搭载区域
118b 走线区域
119 凸部
119a 元件搭载区域侧面
119b 走线区域侧面
119c 凹部
120 压电元件
121 导电性粘接剂
124 导体图案
130 集成电路元件
132 焊料凸点
134 电极衬垫
140 树脂
150 盖构件
151 焊料流动防止区域
K1 第1凹部
K2 第2凹部

Claims (6)

1.一种压电装置，其特征在于，包括：
元件搭载构件；
搭载于所述元件搭载构件上的压电元件；
形成于所述元件搭载构件的表面且包含元件搭载区域及走线区域的金属图案；以及
利用焊料凸点与所述金属图案的所述元件搭载区域电连接的集成电路元件，
所述金属图案具有设置于所述元件搭载区域与所述走线区域之间的凸部，所述凸部的至少表面部分由金属氧化物构成，
所述凸部具有元件搭载区域侧面，俯视时，所述元件搭载区域侧面具有多个凹部，且俯视时，多个凹部均以朝向所述走线区域的方向变窄的方式凹陷。
2.如权利要求1所述的压电装置，其特征在于，
所述金属图案具有设置于较所述凸部更靠近所述走线区域一侧的沟部。
3.如权利要求1所述的压电装置，其特征在于，
所述凸部通过照射激光来形成。
4.一种压电装置，其特征在于，包括：
元件搭载构件；
搭载于所述元件搭载构件上的压电元件；
形成于所述元件搭载构件的表面且包含元件搭载区域及走线区域的金属图案；以及
利用焊料凸点与所述金属图案的所述元件搭载区域电连接的集成电路元件，
所述金属图案具有设置于所述元件搭载区域与所述走线区域之间的凸部，所述凸部的至少表面部分由金属氧化物构成，
所述凸部具有元件搭载区域侧面及走线区域侧面，所述元件搭载区域侧面倾斜得比所述走线区域侧面还急剧。
5.一种压电装置，其特征在于，包括：
元件搭载构件；
搭载于所述元件搭载构件上的压电元件；
形成于所述元件搭载构件的表面且包含元件搭载区域及走线区域的金属图案；以及
利用焊料凸点与所述金属图案的所述元件搭载区域电连接的集成电路元件，
所述金属图案具有设置于所述元件搭载区域与所述走线区域之间的凸部，所述凸部的至少表面部分由金属氧化物构成，
还具有导体图案，该导体图案设置在所述集成电路元件的、通过所述焊料凸点与所述金属图案相连接的一侧的面的边缘部上，
所述凸部设置于与所述导体图案相重叠的位置或较所述导体图案更靠近内侧的位置。
6.一种压电装置，其特征在于，包括：
元件搭载构件；
搭载于所述元件搭载构件的压电元件；
设置于所述元件搭载构件的表面且包含元件搭载区域及走线区域的金属图案；以及
集成电路元器件，该集成电路元器件包含集成电路元件及导体图案，该集成电路元件利用焊料凸点与所述金属图案的所述元件搭载区域电连接，而该导体图案是设置在所述集成电路元件的、通过所述焊料凸点与所述金属图案相连接的一侧的面的边缘部，
所述金属图案还包含焊料流动防止区域，该焊料流动防止区域设置于所述元件搭载区域与所述走线区域之间，
所述焊料流动防止区域设置于俯视时与所述集成电路元器件的所述导体图案相重叠的位置或较所述导体图案更靠内侧的位置。
CN201280034749.7A 2011-08-31 2012-08-31 压电装置 Active CN103650335B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2011-188447 2011-08-31
JP2011188447A JP5767061B2 (ja) 2011-08-31 2011-08-31 圧電装置
JP2012-102901 2012-04-27
JP2012102901A JP5828480B2 (ja) 2012-04-27 2012-04-27 圧電装置
PCT/JP2012/072152 WO2013031944A1 (ja) 2011-08-31 2012-08-31 圧電装置

Publications (2)

Publication Number Publication Date
CN103650335A CN103650335A (zh) 2014-03-19
CN103650335B true CN103650335B (zh) 2016-08-17

Family

ID=47756420

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280034749.7A Active CN103650335B (zh) 2011-08-31 2012-08-31 压电装置

Country Status (5)

Country Link
US (1) US9006958B2 (zh)
KR (1) KR101955955B1 (zh)
CN (1) CN103650335B (zh)
TW (1) TW201320420A (zh)
WO (1) WO2013031944A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102653710B (zh) * 2011-12-14 2013-12-04 赵军 五米液酿制方法及其专用设备
JP6319962B2 (ja) * 2013-07-26 2018-05-09 キヤノン株式会社 プリント基板及び画像形成装置
US9287882B2 (en) 2013-11-07 2016-03-15 Kyocera Crystal Device Corporation Temperature compensated crystal oscillator
JP6468085B2 (ja) * 2015-06-11 2019-02-13 株式会社デンソー 基板、および、その製造方法
JP2020043433A (ja) * 2018-09-07 2020-03-19 京セラ株式会社 水晶デバイス
JP2020043434A (ja) * 2018-09-07 2020-03-19 京セラ株式会社 水晶デバイス
JP7482833B2 (ja) 2021-05-27 2024-05-14 三菱電機株式会社 半導体装置および半導体装置の製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004039988A (ja) * 2002-07-05 2004-02-05 Shinko Electric Ind Co Ltd 素子搭載用回路基板及び電子装置
JP2009038534A (ja) * 2007-07-31 2009-02-19 Kyocera Kinseki Corp 圧電発振器
JP2009038533A (ja) * 2007-07-31 2009-02-19 Kyocera Kinseki Corp 圧電発振器
JP2009077341A (ja) * 2007-09-25 2009-04-09 Epson Toyocom Corp 圧電デバイスおよび圧電振動子
JP2009088974A (ja) * 2007-09-28 2009-04-23 Seiko Epson Corp デバイス及び電子機器

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4852850B2 (ja) * 2005-02-03 2012-01-11 セイコーエプソン株式会社 圧電振動素子、圧電振動子、圧電発振器、周波数安定化方法、及び圧電振動子の製造方法
JP2007158918A (ja) * 2005-12-07 2007-06-21 Nippon Dempa Kogyo Co Ltd 表面実装用の水晶発振器
JP5095319B2 (ja) * 2007-09-06 2012-12-12 日本電波工業株式会社 モニタ電極を備えた水晶デバイス
JP2009267866A (ja) 2008-04-25 2009-11-12 Kyocera Kinseki Corp 圧電発振器
JP5305787B2 (ja) * 2008-08-27 2013-10-02 セイコーインスツル株式会社 電子部品パッケージの製造方法
JP2010232806A (ja) * 2009-03-26 2010-10-14 Seiko Epson Corp 圧電振動子、圧電発振器、電子機器、及び圧電振動子の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004039988A (ja) * 2002-07-05 2004-02-05 Shinko Electric Ind Co Ltd 素子搭載用回路基板及び電子装置
JP2009038534A (ja) * 2007-07-31 2009-02-19 Kyocera Kinseki Corp 圧電発振器
JP2009038533A (ja) * 2007-07-31 2009-02-19 Kyocera Kinseki Corp 圧電発振器
JP2009077341A (ja) * 2007-09-25 2009-04-09 Epson Toyocom Corp 圧電デバイスおよび圧電振動子
JP2009088974A (ja) * 2007-09-28 2009-04-23 Seiko Epson Corp デバイス及び電子機器

Also Published As

Publication number Publication date
KR20140096256A (ko) 2014-08-05
US20130140947A1 (en) 2013-06-06
TW201320420A (zh) 2013-05-16
WO2013031944A1 (ja) 2013-03-07
TWI563699B (zh) 2016-12-21
US9006958B2 (en) 2015-04-14
CN103650335A (zh) 2014-03-19
KR101955955B1 (ko) 2019-06-24

Similar Documents

Publication Publication Date Title
CN103650335B (zh) 压电装置
US9490194B2 (en) Semiconductor device
JP6686691B2 (ja) 電子装置
TW200525666A (en) Bump-on-lead flip chip interconnection
JP2012129336A (ja) 半導体装置およびその製造方法
JP5381753B2 (ja) 半導体装置およびその製造方法
JP5971310B2 (ja) 半導体装置の製造方法および半導体装置
WO2007023747A1 (ja) 半導体チップおよびその製造方法ならびに半導体装置
JP5058714B2 (ja) 半導体装置及びその製造方法
JP2020074379A (ja) 半導体装置
JP5767061B2 (ja) 圧電装置
KR20080109769A (ko) 리드 단자 접착 방법 및 인쇄 회로 기판
JP2000022300A (ja) 配線基板および電子ユニット
JP2015207757A (ja) 半導体装置
JP6423147B2 (ja) 電力用半導体装置およびその製造方法
JP5951073B2 (ja) 圧電装置
TW201225248A (en) TSV chip package and its packaging method
JP2006286666A (ja) 半導体装置の製造方法
JP2017079258A (ja) 電子部品搭載用基板および電子装置
TWI806265B (zh) 封裝體及其製造方法
JP4723312B2 (ja) 半導体チップおよび半導体装置
JP2009200771A (ja) 圧電デバイス
JP4828997B2 (ja) 半導体パッケージおよびその実装方法、ならびにその半導体パッケージに使用する絶縁配線基板およびその製造方法
JP2000208544A (ja) ベアｉｃチップおよび半導体装置
JP2021190454A (ja) 半導体装置、および半導体装置の製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant