CN103187438B - 鳍式bjt - Google Patents
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- CN103187438B CN103187438B CN201210154484.6A CN201210154484A CN103187438B CN 103187438 B CN103187438 B CN 103187438B CN 201210154484 A CN201210154484 A CN 201210154484A CN 103187438 B CN103187438 B CN 103187438B
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- 239000000758 substrate Substances 0.000 claims abstract description 51
- 239000004065 semiconductor Substances 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims description 32
- 238000000407 epitaxy Methods 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 230000005669 field effect Effects 0.000 abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 5
- 150000004706 metal oxides Chemical class 0.000 abstract description 5
- 230000000295 complement effect Effects 0.000 abstract description 4
- 239000012535 impurity Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229960001866 silicon dioxide Drugs 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Abstract
本发明提供了一种使用鳍式场效应晶体管(FinFET)互补金属氧化物半导体(CMOS)工艺流程所形成的双极结型晶体管(BJT)。该BJT包括形成在衬底上方的发射极鳍、基极鳍以及集电极鳍。基极鳍围绕着发射极鳍,并且集电极鳍围绕着发射极鳍。在一些实施例中,当从上方观看时,发射极鳍、基极鳍以及集电极鳍具有正方形的形状并且彼此同心。还提供了一种鳍式BJT。
Description
技术领域
本发明一般地涉及半导体技术领域,更具体地来说,涉及鳍式双极结型晶体管及其形成方法。
背景技术
将半导体器件应用于大量电子器件中,诸如:计算机、手机等。半导体器件包括形成在半导体晶圆上方的集成电路,该集成电路通过在半导体晶圆上方沉积多种材料薄膜,并且图案化这些材料薄膜而形成。集成电路包括场效应晶体管(FET),诸如,金属氧化物半导体(MOS)晶体管。
半导体工业的目标之一在于不断缩小各个FET的尺寸并且提高其速度。为了实现这些目标,在小于32nm(sub32nm)晶体管节点中使用鳍式FET(FinFET)或多栅极晶体管。例如,FinFET不仅改善了平面密度(与传统的平面器件相比,在相同的布局区域中的栅极密度(即,晶体管数量)),还改善了沟槽的栅极控制。也就是说,FinFET提高了各个晶体管的性能并且降低了泄露(功率损耗)。
双极结型晶体管(BJT)和FinFET需要不同的结构。因此,通常使用不同的制造工艺制造这两种晶体管。
发明内容
为了解决现有技术中所存在的缺陷,根据本发明的一方面,提供了一种双极结型晶体管(BJT),包括:发射极鳍,形成在衬底上方;基极鳍,形成在所述衬底上方,所述基极鳍围绕所述发射极鳍;以及集电极鳍,形成在所述衬底上方,所述集电极鳍围绕所述基极鳍,从而形成了所述BJT。
在该BJT中,当从上方观看时,所述发射极鳍、所述基极鳍、以及所述集电极鳍都具有正方形和圆形中的至少一种。
在该BJT中,所述发射极鳍、所述基极鳍、以及所述集电极鳍同心。
在该BJT中,所述发射极鳍、所述基极鳍、以及所述集电极鳍都由半导体和绝缘材料中的一种形成。
在该BJT中,浅沟道隔离(STI)区域设置在所述发射极鳍、所述基极鳍以及所述集电极鳍之间。
在该BJT中,所述发射极鳍由位于p掺杂的半导体材料上方的n+掺杂的半导体材料形成,所述基极鳍由位于p掺杂的半导体材料上方的p+掺杂的半导体材料形成,并且所述集电极鳍由位于n掺杂的半导体材料上方的n+掺杂的半导体材料形成。
在该BJT中,所述衬底是带有p阱和n阱的p掺杂的硅衬底,所述p阱设置在所述发射极鳍和所述基极鳍的每一个的下方,并且所述n阱设置在所述集电极鳍的下方。
在该BJT中,所述发射极鳍与所述基极鳍之间的间距大于所述基极鳍与所述集电极鳍之间的间距。
根据本发明的另一方面,提供了一种双极结型晶体管(BJT),包括:多个同心的发射极鳍,形成在衬底上方;多个同心的基极鳍,形成在所述衬底上方,所述多个基极鳍围绕着所述多个同心的发射极鳍;以及多个同心的集电极鳍,形成在所述衬底上方,所述多个集电极鳍围绕着所述多个同心的基极鳍,从而形成了所述BJT。
在该BJT中,所述多个同心的发射极鳍由十五个间隔开的半导体鳍形成。
在该BJT中,所述多个同心的基极鳍由两个间隔开的半导体鳍形成。
在该BJT中,所述多个同心的集电极鳍由六个间隔开的半导体鳍形成。
在该BJT中,当从上方观看时,所述多个同心的发射极鳍、所述多个同心的基极鳍,以及所述多个同心的集电极鳍具有正方形形状。
在该BJT中,所述多个同心的发射极鳍、所述多个同心的基极鳍,以及所述多个同心的集电极鳍都由半导体材料形成。
在该BJT中,在所述多个同心的发射极鳍、所述多个同心的基极鳍,以及所述多个同心的集电极鳍之间设置有浅沟道隔离(STI)区域。
在该BJT中,所述多个同心的发射极鳍由位于p掺杂的半导体材料上方的n+掺杂的半导体材料形成,所述多个同心的基极鳍由位于所述p掺杂的半导体材料上方的p+掺杂的半导体材料形成,并且所述多个同心的集电极鳍由位于n掺杂的半导体材料上方的n+掺杂的半导体材料形成。
在该BJT中,所述多个同心的发射极鳍电连接在一起,所述多个同心的基极鳍电连接在一起,并且所述多个同心的集电极鳍电连接在一起。
根据本发明的又一方面,提供了一种形成双极结型晶体管(BJT)的方法,包括:在衬底上方形成多个同心的发射极鳍;在所述衬底上方形成多个同心的基极鳍,所述多个同心的基极鳍围绕着所述多个同心的发射极鳍;以及在所述衬底上方形成多个同心的集电极鳍,所述多个同心的集电极鳍围绕着所述多个同心的基极鳍,从而形成了所述BJT。
该方法进一步包括:设置在所述衬底上方的浅沟道隔离(STI)区域中蚀刻多个同心的沟槽,并且在所述多个同心的沟槽中,在所述衬底上方外延生长所述多个同心的发射极鳍,所述多个同心的基极鳍,以及所述多个同心的集电极鳍。
该方法进一步包括:通过在其上外延生长第一接触件来电连接所述多个同心的发射极鳍,通过在其上外延生长第二接触件来电连接所述多个同心的基极鳍,并且通过在其上外延生长第三接触件来电连接所述多个同心的集电极鳍,所述第一接触件、所述第二接触件和所述第三接触件由硅和硅锗中的一种形成。
附图说明
为了更全面地理解本发明及其优势,现将结合附图所进行的以下描述作为参考,其中:
图1是大体上沿着图2中的y-y’所截取的双极结型晶体管(BJT)的截面图,使用鳍式场效应晶体管(FinFET)互补金属氧化物半导体(CMOS)工艺流程来形成该双极结型晶体管;
图1a是图1的BJT的一部分,该图更详细地示出了多个发射极鳍,并且示意性地指出了n-p-n鳍式BJT的杂质掺杂条件;
图1b是图1的BJT的一部分,该图更详细地示出了基极鳍和集电极鳍,并且示意性地指出了n-p-n鳍式BJT的杂质掺杂条件;
图2是通常用于图1的BJT的鳍式BJT结构的透视图,该透视图示意性地指出了鳍和衬底的半导体材料(例如,硅、锗、砷镓)以及用于隔离的绝缘材料(例如,二氧化硅);
图3是鳍式BJT布局的一个实施例或是图2的BJT的部分平面图,该图示出了BJT中的发射极区域、基极区域以及集电极区域,并且示出了发射极鳍、基极鳍以及集电极鳍之间的间隔;
图4是图2的BJT中的集电极鳍和基极鳍的部分的透视图;
图5是图4的BJT部分的透视图,该图示出了集电极鳍的尺寸(例如,鳍高度和鳍宽度);
图6是图1的BJT的立体图,该图示出了流经器件的电流并且示意性地指出了鳍和衬底的半导体材料(例如,硅、锗、镓砷)以及用于隔离的绝缘材料(例如,二氧化硅);
图6a是图6的BJT的部分,该图示出了发射极鳍的尺寸;
图6b是图6的BJT的部分,该图示出了基极鳍和集电极鳍的尺寸;
图7是发射极鳍电连接在一起,基极鳍电连接在一起,并且集电极鳍电连接在一起的BJT的立体图;
图8是图7的BJT的部分俯视图,该图示出了电流的流动;以及
图9是流程图,该图示出了在一些实施例中形成图1的BJT的工艺或流程。
具体实施方式
下面,详细讨论本发明的优选实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的发明概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式,而不用于限制本发明的范围。
将利用具体环境(即,使用鳍式场效应晶体管(FinFET)互补金属氧化物半导体(CMOS)工艺流程形成的双极结型晶体管(BJT)10)中的优选的实施例来描述本发明。该BJT10适用于现有的FinFETCMOS逻辑工艺流程。因此,形成该鳍式的BJT结构时不需要额外的掩模和工艺(也就是说没有增加额外成本)。然而,本发明也可以应用于其他类型的半导体器件结构或电路(例如,二极管、电阻器、阱拾取件(wellpickup)等)。
现在,参考图1,示出了使用鳍式场效应晶体管(FinFET)互补金属氧化物半导体(CMOS)工艺流程所形成的BJT10。在一些实施例中,BJT10包括:p型掺杂的半导体衬底12、浅沟道隔离(STI)区域18、发射极鳍20、基极鳍22,以及集电极鳍24,该半导体衬底带有p阱16和n阱14,将n阱14设置在p阱16的相对两侧。图2清楚地示出,n阱14可以是围绕着p阱16的单个环形区域。虽然在图1中示出了n-p-nBJT10,但也可以形成p-n-pBJT或其他半导体结构。
在一些实施例中,衬底12、发射极鳍20、基极鳍22以及集电极鳍24由绝缘材料形成,从而适应绝缘体上硅(SOI)FinFET工艺,该绝缘体上硅工艺与体FinFET工艺相反,在该体FinFET工艺中衬底通常由硅材料形成。
在图1中,所描述的衬底12的部分具有大约6微米的长度以及大约1015/cm3的杂质浓度。另外,n阱14具有大约100nm至大约400nm的深度或厚度(大体上完全围绕了集电极区域),并且具有大约1018/cm3的杂质浓度。p阱16具有大约100nm至大约400nm的深度或厚度(大体上完全围绕了基极和发射极区域),并且具有大约1018/cm3的杂质浓度。然而,本领域的技术人员会意识到,整个说明书中所描述的尺寸和数值仅仅是实例,并且如果使用了不同的形成技术,则该尺寸和数量也会改变。通常,N+区域和P+区域(例如,鳍20、22、24的上部)的掺杂水平高于n阱14和p阱16的掺杂水平。n阱14和p阱16的掺杂水平还高于衬底12的掺杂水平。
现参考图1、图1a和图1b,STI区域18形成在衬底12上方以及形成在单独发射极鳍20、基极鳍22和集电极鳍24中的每一个之间。可以通过蚀刻衬底12以形成沟槽并且然后利用介电材料(诸如,高密度等离子体(HDP)氧化物、TEOS氧化物等)填充该沟槽来形成STI区域18。在一些实施例中,STI区域18的深度26为大约100nm至300nm。在一些实施例中,STI区域18的深度比有效的鳍高度深得多,该有效的鳍高度是鳍在STI区域18的顶面上方突出的部分。在一些实施例中,有效的鳍高度约为15nm至100nm。然而,也可以通过调节有效的鳍高度来减少泄露,更好地提高器件的整体性能等。在一些实施例中,在发射极鳍20、基极鳍22以及集电极鳍24之间的STI区域18所具有的间隔28的大小在大约30nm至大约100nm之间。在一些实施例中,蚀刻覆盖着衬底的STI层以形成沟槽,然后,该沟槽填充有外延生长的半导体材料,从而形成了发射极鳍20、基极鳍22以及集电极鳍24。
参考图1a,在一些实施例中,实施n型杂质注入,从而在发射极鳍20和集电极鳍24的上部中形成重掺杂的n型区域30。在整个说明书中,术语“重掺杂”指的是杂质浓度大于大约1020/cm3。然而,可以认识到,术语“重掺杂”是技术术语,并且涉及的是用于形成实施例的集成电路的具体技术时代。在一些实施例中,实施p型掺杂注入,从而在基极鳍22的上部中形成重掺杂的p型区域32。在一些实施例中,在形成相应的鳍的过程中可以实施原位掺杂来引入杂质。
参考图2,当从上方观看时,发射极鳍20、基极鳍22以及集电极鳍24中的每一个均具有正方形外形。在一些实施例中,发射极鳍20、基极鳍22和集电极鳍24可以形成或表现为其他几何形状(例如,矩形、圆形等)。发射极鳍20、基极鳍22和集电极鳍24也可以形成或表现为不规则的几何形状。如图2所示,每个发射极鳍20均与其他发射极鳍同心,每个基极鳍22均与其他基极鳍同心,并且每个集电极鳍24均与其他集电极鳍同心。同样地,发射极鳍20的组、基极鳍22的组以及集电极鳍24的组也都彼此同心。在图2中,基极鳍22围绕发射极鳍20,并且集电极鳍24围绕基极鳍22和发射极鳍20。
仍参考图2,示出了十五个发射极鳍20、两个基极鳍22、以及六个集电极鳍24。在一些实施例中,可以在BJT10上形成更多或更少的发射极鳍20、基极鳍22和集电极鳍24。当然,在一些实施例中,BJT10仅包括单个发射极鳍20、单个基极鳍22、和/或单个集电极鳍24。
参考图3,示出了如上所示的BJT10的一部分。在一些实施例中,最里面的集电极鳍24和最外面的基极鳍22之间的距离34(即,集电极和基极之间的距离)为大约200nm至大约500nm。在一些实施例中,最里面的基极鳍22和最外面的发射极鳍20之间的距离36(即,基极和发射极之间的距离)约为500nm。此外,根据所使用的光刻技术,最小的发射极鳍20的相对内壁之间的距离38约为200nm。
现参考图4,放大了BJT10的部分来进一步示出基极鳍22和集电极鳍24。图5中进一步放大了集电极鳍24,从而示出:集电极鳍24的高度40在大约20nm和大约100nm之间,并且集电极鳍24的宽度42在大约10nm和大约15nm之间。在一些实施例中,“鳍式”FET器件的鳍宽度为约10nm,而“三栅极”FET器件的鳍宽度为约100nm。
现在参考图6,示出了所指示的流经BJT10的电流。尤其是电流44从基极鳍22流向发射极鳍20,而与电流44相比,更大的电流46从集电极鳍24流向发射极鳍20。如图6a至图6b所示,发射极鳍20的高度48在大约20nm和大约100nm之间,以及发射极鳍20的宽度50在大约10nm和大约100nm之间。同样地,基极鳍22的高度52在大约20nm至大约100nm之间,以及基极鳍22的宽度54在大约10nm至大约15nm之间。如图6a至图6b所示,根据光刻工艺限制以及器件结构设计,相邻的集电极鳍24的鳍间隙56(例如,一个鳍的宽度加上相邻的鳍之间的间隔)在大约40nm至大约200nm之间。在一些实施例中,相邻的基极鳍22和相邻的集电极鳍24之间的鳍间隙56也在大约40nm至大约65nm之间。在一些实施例中,BJT10的鳍20-24可以由晶圆形成,例如,该晶圆具有晶体定向100、111或110。
参考图6a至图6b,BJT10上的有效的鳍结点的面积58(effectivefinjunctionarea)(等于鳍的宽度乘以在页面中延伸的鳍长度的乘积)与平面结点的面积(planarjunctionarea)60(等于鳍和STI材料的总宽度乘以在页面中延伸的相同鳍长度的乘积)之间的比例约为Wfin*#鳍*长度/[(#鳍-1)*P鳍+W鳍]*长度(Wfin*#fin*Length/[(#fin-1)*Pfin+Wfin]*Length),其中,Wfin是鳍宽度(例如,宽度42),#鳍是布局区域中的鳍的总数,而Pfin是鳍之间的间隙(例如,鳍间隙56)。本领域的技术人员将意识到,同样在相同的布局区域内,BJT10的有效结点的面积小于其平面BJT的平面结点的面积。
现在,参考图7,在该图中示出了BJT10的一部分,发射极鳍20通过接触件60电连接在一起,基极鳍22通过接触件62电连接在一起,并且集电极鳍24通过接触件64电连接在一起。在一些实施例中,接触件60、62、64是外延形成的硅或硅锗。在一些实施例中,接触件60、62、64是金属零(metalzero,M0)塞、铜塞或钨塞。如图8所示,与其他公知的BJT器件相比,发射极、基极以及集电极鳍24的“环状”的结构提供了改进的对称性和电流分布。
现在,参考图9,示出了图7所示的形成BJT10的工艺66。在框68中,将杂质引入到p掺杂的半导体衬底12中,从而形成n阱14和p阱。在框70中,在衬底上以同心的正方形图案形成发射极鳍20、基极鳍22以及集电极鳍24。如上所述,既可以通过蚀刻衬底12并且利用STI氧化物18填充沟槽,也可以通过蚀刻STI氧化物18的层并且在沟槽中外延生长鳍来形成鳍20、22、24。在框72中,将杂质引入到发射极鳍20、基极鳍22以及集电极鳍24中。可以通过注入工艺或原位掺杂工艺完成这种掺杂。然后,在框74中,发射极鳍20电连接在一起,基极鳍22电连接在一起,并且集电极鳍24电连接在一起。
一种双极结型晶体管(BJT)包括:形成在衬底上方的发射极鳍;形成在衬底上方的基极鳍,该基极鳍围绕发射极鳍;以及形成在衬底上方的集电极鳍,该集电极鳍围绕基极鳍,从而形成了BJT。
一种双极结型晶体管(BJT)包括:多个形成在衬底上方的同心的发射极鳍;多个形成在衬底上方的同心的基极鳍,该多个基极鳍围绕着多个同心的发射极鳍;以及多个形成在衬底上方的同心的集电极鳍,该多个同心的集电极鳍围绕着多个同心的基极鳍,从而形成了BJT。
一种形成双极结型晶体管(BJT)的方法包括:在衬底上方形成多个同心的发射极鳍;在衬底上方形成多个同心的基极鳍,该多个基极鳍围绕着多个同心的发射极鳍;以及在衬底上形成多个同心的集电极鳍,该多个集电极鳍围绕着多个同心的基极鳍,从而形成了BJT。
虽然已经参考说明性的实施例描述了本发明,但不应将该描述理解为限制意义。对于本领域的技术人员而言,参考该描述应该理解说明性的实施例的各个变更和组合以及本发明的其他实施例。因此,旨在所附的权利要求包括任何这种更改或实施例。
Claims (20)
1.一种双极结型晶体管(BJT),包括:
发射极鳍,形成在衬底上方,所述发射极鳍环绕所述衬底的内部区域;
基极鳍,形成在所述衬底上方,所述基极鳍围绕所述发射极鳍;以及
集电极鳍,形成在所述衬底上方,所述集电极鳍围绕所述基极鳍,从而形成了所述双极结型晶体管,其中,所述内部区域的整个区域完全被浅沟道隔离区域覆盖。
2.根据权利要求1所述的双极结型晶体管,其中,当从上方观看时,所述发射极鳍、所述基极鳍、以及所述集电极鳍都具有正方形和圆形中的至少一种。
3.根据权利要求1所述的双极结型晶体管,其中,所述发射极鳍、所述基极鳍、以及所述集电极鳍同心。
4.根据权利要求1所述的双极结型晶体管,其中,所述发射极鳍、所述基极鳍、以及所述集电极鳍都由半导体和绝缘材料中的一种形成。
5.根据权利要求1所述的双极结型晶体管,其中,浅沟道隔离(STI)区域设置在所述发射极鳍、所述基极鳍以及所述集电极鳍之间。
6.根据权利要求1所述的双极结型晶体管,其中,所述发射极鳍由位于p掺杂的半导体材料上方的n+掺杂的半导体材料形成,所述基极鳍由位于p掺杂的半导体材料上方的p+掺杂的半导体材料形成,并且所述集电极鳍由位于n掺杂的半导体材料上方的n+掺杂的半导体材料形成。
7.根据权利要求1所述的双极结型晶体管,其中,所述衬底是带有p阱和n阱的p掺杂的硅衬底,所述p阱设置在所述发射极鳍和所述基极鳍的每一个的下方,并且所述n阱设置在所述集电极鳍的下方。
8.根据权利要求1所述的双极结型晶体管,其中,所述发射极鳍与所述基极鳍之间的间距大于所述基极鳍与所述集电极鳍之间的间距。
9.一种双极结型晶体管(BJT),包括:
多个同心的发射极鳍,形成在衬底上方;
多个同心的基极鳍,形成在所述衬底上方,所述多个基极鳍围绕着所述多个同心的发射极鳍,其中,所有的同心的发射极鳍均被所述多个同心的基极鳍中最里面的同心的基极鳍围绕;以及
多个同心的集电极鳍,形成在所述衬底上方,所述多个集电极鳍围绕着所述多个同心的基极鳍,从而形成了所述双极结型晶体管。
10.根据权利要求9所述的双极结型晶体管,其中,所述多个同心的发射极鳍由十五个间隔开的半导体鳍形成。
11.根据权利要求9所述的双极结型晶体管,其中,所述多个同心的基极鳍由两个间隔开的半导体鳍形成。
12.根据权利要求9所述的双极结型晶体管,其中,所述多个同心的集电极鳍由六个间隔开的半导体鳍形成。
13.根据权利要求9所述的双极结型晶体管,其中,当从上方观看时,所述多个同心的发射极鳍、所述多个同心的基极鳍,以及所述多个同心的集电极鳍具有正方形形状。
14.根据权利要求9所述的双极结型晶体管,其中,所述多个同心的发射极鳍、所述多个同心的基极鳍,以及所述多个同心的集电极鳍都由半导体材料形成。
15.根据权利要求9所述的双极结型晶体管,其中,在所述多个同心的发射极鳍、所述多个同心的基极鳍,以及所述多个同心的集电极鳍之间设置有浅沟道隔离(STI)区域。
16.根据权利要求9所述的双极结型晶体管,其中,所述多个同心的发射极鳍由位于p掺杂的半导体材料上方的n+掺杂的半导体材料形成,所述多个同心的基极鳍由位于所述p掺杂的半导体材料上方的p+掺杂的半导体材料形成,并且所述多个同心的集电极鳍由位于n掺杂的半导体材料上方的n+掺杂的半导体材料形成。
17.根据权利要求9所述的双极结型晶体管,其中,所述多个同心的发射极鳍电连接在一起,所述多个同心的基极鳍电连接在一起,并且所述多个同心的集电极鳍电连接在一起。
18.一种形成双极结型晶体管(BJT)的方法,包括:
在衬底上方形成多个同心的发射极鳍;
在所述衬底上方形成多个同心的基极鳍,所述多个同心的基极鳍围绕着所述多个同心的发射极鳍;以及
在所述衬底上方形成多个同心的集电极鳍,所述多个同心的集电极鳍围绕着所述多个同心的基极鳍,从而形成了所述双极结型晶体管,其中,所有的同心的发射极鳍均被所述多个同心的基极鳍中最里面的同心的基极鳍围绕。
19.根据权利要求18所述的形成双极结型晶体管方法,进一步包括:设置在所述衬底上方的浅沟道隔离(STI)区域中蚀刻多个同心的沟槽,并且在所述多个同心的沟槽中,在所述衬底上方外延生长所述多个同心的发射极鳍,所述多个同心的基极鳍,以及所述多个同心的集电极鳍。
20.根据权利要求18所述的形成双极结型晶体管方法,进一步包括:通过在其上外延生长第一接触件来电连接所述多个同心的发射极鳍,通过在其上外延生长第二接触件来电连接所述多个同心的基极鳍,并且通过在其上外延生长第三接触件来电连接所述多个同心的集电极鳍,所述第一接触件、所述第二接触件和所述第三接触件由硅和硅锗中的一种形成。
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CN104022032B (zh) * | 2014-05-22 | 2017-04-05 | 武汉新芯集成电路制造有限公司 | FinFET制程中形成垂直双极型晶体管的方法 |
CN105185828A (zh) * | 2015-06-12 | 2015-12-23 | 宁波时代全芯科技有限公司 | 鳍式场效晶体管与其制备方法 |
CN106409890B (zh) * | 2015-07-28 | 2019-07-30 | 中芯国际集成电路制造(上海)有限公司 | 鳍式双极结型晶体管的形成方法 |
CN106486535A (zh) * | 2015-09-01 | 2017-03-08 | 中芯国际集成电路制造(上海)有限公司 | 鳍片式双极型半导体器件及其制造方法 |
KR102323943B1 (ko) | 2015-10-21 | 2021-11-08 | 삼성전자주식회사 | 반도체 장치 제조 방법 |
JP6794706B2 (ja) * | 2015-10-23 | 2020-12-02 | 株式会社リコー | 電界効果型トランジスタ、表示素子、画像表示装置、及びシステム |
US9960273B2 (en) * | 2015-11-16 | 2018-05-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure with substrate isolation and un-doped channel |
CN107180861B (zh) * | 2016-03-09 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
TWI677073B (zh) * | 2016-04-27 | 2019-11-11 | 聯華電子股份有限公司 | 雙載子接面電晶體佈局結構 |
CN108321190B (zh) * | 2017-01-16 | 2020-11-27 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
CN108695374B (zh) * | 2017-04-10 | 2021-07-13 | 中芯国际集成电路制造(上海)有限公司 | 双极型晶体管及其形成方法 |
CN114784094A (zh) * | 2017-05-05 | 2022-07-22 | 联华电子股份有限公司 | 双极性晶体管 |
US10236367B2 (en) * | 2017-07-06 | 2019-03-19 | Globalfoundries Inc. | Bipolar semiconductor device with silicon alloy region in silicon well and method for making |
TWI777971B (zh) | 2017-08-28 | 2022-09-21 | 聯華電子股份有限公司 | 雙極性電晶體及其製作方法 |
TWI726155B (zh) * | 2017-09-14 | 2021-05-01 | 聯華電子股份有限公司 | 雙載子接面電晶體 |
US10665702B2 (en) | 2017-12-27 | 2020-05-26 | Samsung Electronics Co., Ltd. | Vertical bipolar transistors |
TWI784064B (zh) | 2018-10-01 | 2022-11-21 | 聯華電子股份有限公司 | 閘極控制雙載子接面電晶體及其操作方法 |
US20210064074A1 (en) | 2019-09-03 | 2021-03-04 | Renesas Electronics America Inc. | Low-voltage collector-free bandgap voltage generator device |
US11239330B2 (en) * | 2020-02-07 | 2022-02-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bipolar junction transistor with gate over terminals |
US11289471B2 (en) * | 2020-08-24 | 2022-03-29 | Globalfoundries U.S. Inc. | Electrostatic discharge device |
US11289591B1 (en) | 2020-09-30 | 2022-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bipolar junction device |
US11804481B2 (en) * | 2021-02-25 | 2023-10-31 | Globalfoundries U.S. Inc. | Fin-based and bipolar electrostatic discharge devices |
US11967637B2 (en) | 2021-08-26 | 2024-04-23 | Globalfoundries U.S. Inc. | Fin-based lateral bipolar junction transistor with reduced base resistance and method |
US20240030320A1 (en) * | 2022-07-25 | 2024-01-25 | Globalfoundries U.S. Inc. | Lateral bipolar transistors |
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US20060202306A1 (en) * | 2005-03-11 | 2006-09-14 | Moshe Agam | Bipolar junction transistor with high beta |
JP2007242722A (ja) * | 2006-03-06 | 2007-09-20 | Renesas Technology Corp | 横型バイポーラトランジスタ |
US7439608B2 (en) * | 2006-09-22 | 2008-10-21 | Intel Corporation | Symmetric bipolar junction transistor design for deep sub-micron fabrication processes |
US8258602B2 (en) * | 2009-01-28 | 2012-09-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bipolar junction transistors having a fin |
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