TWI777971B - 雙極性電晶體及其製作方法 - Google Patents

雙極性電晶體及其製作方法 Download PDF

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TWI777971B
TWI777971B TW106129133A TW106129133A TWI777971B TW I777971 B TWI777971 B TW I777971B TW 106129133 A TW106129133 A TW 106129133A TW 106129133 A TW106129133 A TW 106129133A TW I777971 B TWI777971 B TW I777971B
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ion implantation
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TW201913818A (zh
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潘貞維
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聯華電子股份有限公司
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Priority to US15/717,975 priority patent/US10217853B1/en
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Abstract

本發明揭露一種製作雙極性電晶體的方法。首先提供一基底，該基底具有一射極區、一基極區以及一集極區，然後進行一第一離子佈植製程以形成一第一井區於基極區內，之後再進行一第二離子佈植製程以形成一第二井區於射極區內，其中該第一井區以及該第二井區包含不同濃度。

Description

雙極性電晶體及其製作方法
本發明是關於一種製作雙極性電晶體的方法，尤指一種於雙極性電晶體之射極區以及基極區內分別形成不同濃度之井區的方法。
雙極性電晶體主要由三部分摻雜程度不同的半導體材料所組成，其中電晶體中的電荷流動主要是由於載子在PN接面處的擴散作用和漂移運動。以NPN電晶體為例，按照設計，高摻雜的射極區域的電子，通過擴散作用運動到基極。在基極區域，電洞為多數載子，而電子少數載子。由於基極區域很薄，這些電子又通過漂移運動到達集極，從而形成集極電流，因此雙極性電晶體被歸到少數載子設備。雙極性電晶體能夠放大訊號，並且具有較好的功率控制、高速工作以及耐久能力，所以它常被用來構成放大器電路，或驅動揚聲器、電動機等設備，並被廣泛地應用於航空航天工程、醫療器械和機器人等應用 產品中。
然而至今雙極性電晶體的設計均仍不盡理想，特別是射極區與基極區時常因摻雜濃度過高而影響元件效能。因此如何改良現今之雙極性電晶體結構極為現今一重要課題。
本發明一實施例揭露一種製作雙極性電晶體的方法。首先提供一基底，該基底具有一射極區、一基極區以及一集極區，然後進行一第一離子佈植製程以形成一第一井區於基極區內，之後再進行一第二離子佈植製程以形成一第二井區於射極區內，其中該第一井區以及該第二井區包含不同濃度。
本發明另一實施例揭露一種雙極性電晶體，其主要包含：一基底，該基底具有一射極區、一基極區以及一集極區；一第一井區設於該基極區內；以及一第二井區設於該射極區內，其中該第一井區以及該第二井區包含不同濃度。
12:基底
14:鰭狀結構
16:射極區
18:基極區
20:集極區
22:離子佈植製程
24:深N井
26:離子佈植製程
28:P井
30:離子佈植製程
32:N井
34:閘極介電層
36:離子佈植製程
38:第一區域
40:第二區域
42:P井
44:虛置閘極
46:閘極材料層
48:側壁子
50:源極/汲極區域
52:層間介電層
54:高介電常數介電層
56:功函數金屬層
58:低阻抗金屬層
60:金屬閘極
62:淺溝隔離
第1圖至第7圖為本發明一實施例製作一雙極性電晶體之方法示意圖。
請參照第1圖至第7圖，第1圖至第7圖為本發明一實施例製作一雙極性電晶體之方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，然後形成複數個鰭狀結構14於基底12上，並於基底12上定義一射極區16、一基極區18以及一集極區20。在本實施例中，射極區16較佳設於約略中間的鰭狀結構14內，基極區18較佳設於射極區16兩側的鰭狀結構14內，而集極區20則設於基極區18兩側的鰭狀結構14內。
另外需注意的是，本實施例雖以製作非平面型(non-planar)場效電晶體例如鰭狀結構場效電晶體為例，但不侷限於此，本發明又可應用至一般平面型(planar)場效電晶體，此實施例也屬本發明所涵蓋的範圍。
依據本發明一實施例，鰭狀結構14較佳透過側壁圖案轉移(sidewall image transfer,SIT)技術製得，其程序大致包括：提供一佈局圖案至電腦系統，並經過適當地運算以將相對應之圖案定義於光罩中。後續可透過光微影及蝕刻製程，以形成多個等距且等寬之圖案化犧牲層於基底上，使其個別外觀呈現條狀。之後依序施行沉積及蝕刻製程，以於圖案化犧牲層之各側壁形成側壁子。繼以去除圖案化犧牲層，並在側壁子的覆蓋下施行蝕刻製程，使得側壁子所構成之圖案被轉移至基底內，再伴隨鰭狀結構切割製程(fin cut)而獲得所需的圖案化結構，例如條狀圖案化鰭狀結構。
除此之外，鰭狀結構14之形成方式又可包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中以形成鰭狀結構。另外，鰭狀結構之形成方式也可以先形成一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出例如包含矽鍺的半導體層，而此半導體層即可作為相對應的鰭狀結構。這些形成鰭狀結構的實施例均屬本發明所涵蓋的範圍。
接著進行一離子佈植製程22，將具有第二導電型式例如N型的摻質全面性植入射極區16、基極區18以及集極區20之鰭狀結構14下方的基底12內以形成一深N井24。
如第2圖所示，然後再進行一離子佈植製程26，將具有第一導電型式例如P型的摻質植入基極區18的鰭狀結構14以及鰭狀結構14下方的部分基底12內以形成P井28。值得注意的是，本實施例在形成P井28的時候較佳先形成圖案化遮罩(圖未示)覆蓋射極區16以及集極區20，藉由圖案化遮罩的遮蔽，本實施例在進行前述離子佈植製程26時P型的摻質或離子便只會被植入基極區18的鰭狀結構14與部分基底12內而不會被植入射極區16以及集極區20的鰭狀結構14內。
隨後如第3圖所示，再進行一離子佈植製程30，將具有第二導電型式例如N型的摻質植入集極區20的鰭狀結構14以及鰭狀結構14下方的部分基底12內以形成N井32。如同前述形成P井28的方式，本實施例在形成N井32的時候可選擇先形成一圖案化遮罩(圖未示)覆蓋射 極區16以及基極區18，且藉由圖案化遮罩的遮蔽，本實施例在進行前述離子佈植製程30時N型的摻質或離子便只會被植入集極區20的鰭狀結構14與部分基底12內而不會被植入射極區16以及基極區18的鰭狀結構14內。然後可進行一熱處理製程活化各井區，包括之前所形成深N井24、P井28以及N井32內的摻質。至此，射極區16內的鰭狀結構14仍為一無摻雜區。
如第4圖所示，可先選擇性形成由氧化矽所構成的淺溝隔離62於鰭狀結構14周圍，接著形成一閘極介電層34於各區域的鰭狀結構14上，再進行離子佈植製程36，將具有第一導電型式例如P型的摻質植入射極區16的鰭狀結構14內以形成一第一區域38以及一第二區域40於第一區域38下方，其中離子佈植製程36的佈植能量、摻雜劑量都小於離子佈植製程26，因此第一區域38較佳為一植入P型摻質之摻雜區而第二區域40則為無摻雜區，且第一區域38的深度小於基極區18內P井28的深度。
然後進行一熱處理製程將摻質由第一區域38向下擴散並同時將設於兩側P井28內的摻質擴散至第二區域40以形成另一P井42。更具體而言，本階段於射極區16所形成的P井42較佳由兩種路徑的摻質一同構成，其中一者為第一區域38內沿著下箭頭方向向下擴散的P型摻質，另一者則為兩側基極區18之P井28內分別經由鰭狀結構14下的部分基底12沿著左右箭頭方向擴散至射極區16第二區域40內的P型摻質。
在本實施例中，經上述熱處理製程射極區16內所形成的P井 42濃度較佳小於基極區18內所形成的P井28濃度，例如P井42內的濃度較佳介於3x1013至4x1013離子/平方公分，而P井28內的濃度則介於1x1014至1.21x1014離子/平方公分。相較於習知雙極性電晶體中射極區16與基極區18內的P井通常具有相同濃度，本發明較佳於不同階段或時間點利用離子佈植製程將不同濃度的摻植分別植入射極區16與基極區18，並藉此於基極區18內形成較高濃度的P井28且於射極區16內形成較低濃度的P井42來提升雙極性電晶體的整體效能。
如第5圖所示，接著可於各射極區16、基極區18以及集極區20上形成至少一閘極結構或虛置閘極44。在本實施例中，虛置閘極44之製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先高介電常數介電層(high-k first)製程以及後閘極製程之後高介電常數介電層(high-k last)製程等方式製作完成。以本實施例之後高介電常數介電層製程為例，可先依序形成一由多晶矽所構成之閘極材料層46以及一選擇性硬遮罩於基底12上，並利用一圖案化光阻(圖未示)當作遮罩進行一圖案轉移製程，以單次蝕刻或逐次蝕刻步驟，去除部分閘極材料層46與部分閘極介電層34，然後剝除圖案化光阻，以於基底12上形成由圖案化之閘極介電層46與圖案化之閘極介電層34所構成的虛置閘極44或閘極結構。
然後在各虛置閘極44側壁形成至少一側壁子48，於側壁子48兩側的鰭狀結構14以及/或基底12中形成一源極/汲極區域50及/或磊晶層(圖未示)，並選擇性於源極/汲極區域50及/或磊晶層的表面形成一金屬矽化物(圖未示)。在本實施例中，側壁子48可為單一側壁子或複合 式側壁子，例如可細部包含一偏位側壁子(圖未示)以及一主側壁子(圖未示)。其中本實施例的側壁子較佳由氮化矽所構成，但側壁子48又可選自由氧化矽、氮氧化矽以及氮碳化矽所構成的群組。
另外在本實施例中，射極區16以及集極區20的源極/汲極區域50較佳包含相同導電型式，例如均由N型摻質所構成且設於射極區16以及集極區20的磊晶層較佳包含磷化矽，基極區18的源極/汲極區域50則較佳由P型摻質所構成且設於基極區18的磊晶層較佳包含鍺化矽。
然後如第6圖所示，可選擇性形成一由氮化矽所構成的接觸洞蝕刻停止層(contact etch stop layer,CESL)(圖未示)於基底12上並覆蓋虛置閘極44，並形成一層間介電層52於接觸洞蝕刻停止層上。接著進行一平坦化製程，例如利用化學機械研磨(chemical mechanical polishing,CMP)去除部分層間介電層52與部分接觸洞蝕刻停止層並暴露出由多晶矽材料所構成的閘極材料層46，使各閘極材料層46上表面與層間介電層52上表面齊平。
隨後進行一金屬閘極置換製程將虛置閘極44轉換為金屬閘極60。例如第7圖所示，可先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide,NH4OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide,TMAH)等蝕刻溶液來去除虛置閘極44中的閘極材料層46，以於層間介電層52中形成凹槽(圖未示)。之後依序形成一高介電常數介電層54、一功函數金屬層56以及一低阻抗金屬層58於各凹槽內，然後進行一平坦化製程，例如利用CMP去除部分 低阻抗金屬層58、部分功函數金屬層56與部分高介電常數介電層54以形成金屬閘極60。以本實施例利用後高介電常數介電層製程所製作的閘極結構為例，各金屬閘極60較佳包含一介質層或閘極介電層34、一U型高介電常數介電層54、一U型功函數金屬層56以及一低阻抗金屬層58。
在本實施例中，高介電常數介電層54包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide，HfO2)、矽酸鉿氧化合物(hafnium silicon oxide,HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化鋁(aluminum oxide,Al2O3)、氧化鑭(lanthanum oxide,La2O3)、氧化鉭(tantalum oxide,Ta2O5)、氧化釔(yttrium oxide,Y2O3)、氧化鋯(zirconium oxide,ZrO2)、鈦酸鍶(strontium titanate oxide,SrTiO3)、矽酸鋯氧化合物(zirconium silicon oxide,ZrSiO4)、鋯酸鉿(hafnium zirconium oxide,HfZrO4)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)、鈦酸鋇鍶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其組合所組成之群組。
功函數金屬層56較佳用以調整形成金屬閘極60之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層56可選用功函數為3.9電子伏特(eV)~4.3eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC(碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層56可選用功函數為4.8eV~5.2eV的金屬材料， 如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層56與低阻抗金屬層58之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層58則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底
16:射極區
18:基極區
20:集極區
24:深N井
28:P井
32:N井
34:閘極介電層
38:第一區域
40:第二區域
42:P井
48:側壁子
50:源極/汲極區域
52:層間介電層
54:高介電常數介電層
56:功函數金屬層
58:低阻抗金屬層
60:金屬閘極
62:淺溝隔離

Claims (16)

  1. 一種製作雙極性電晶體的方法，包含：提供一基底，該基底具有一射極區、一基極區以及一集極區；進行一第一離子佈植製程以形成一第一井區於該基極區內；進行一第二離子佈植製程以形成一第二井區於該射極區內，其中該第二井區由上而下包含一第一區域及一第二區域；進行一熱處理製程將摻質由該第一區域向下擴散以及摻質由該第一井區擴散至該第二區域，其中該第一區域及該第二區域包含相同導電型式，且該第一井區以及該第二井區包含不同濃度；以及形成一淺溝隔離於該射極區以及該基極區之間並接觸該第一井區及該第二井區，其中部分該第二井區係設於該淺溝隔離正下方且該第一井區底表面切齊該第二井區底表面。
  2. 如申請專利範圍第1項所述之方法，另包含：形成複數個鰭狀結構於該基底上；進行一第三離子佈植製程以形成一深井區於該等鰭狀結構下方之該基底內；以及進行該第一離子佈植製程。
  3. 如申請專利範圍第2項所述之方法，另包含於進行該第一離子佈植製程以及該第二離子佈植之間進行一第四離子佈植製程以形成一第三井區於該集極區。
  4. 如申請專利範圍第3項所述之方法，其中該第一井區及該第二井區包含第一導電型式且該深井區及該第三井區包含第二導電型式。
  5. 如申請專利範圍第4項所述之方法，其中該第一導電型式包含P型且該第二導電型式包含N型。
  6. 如申請專利範圍第2項所述之方法，另包含：進行該第二離子佈植製程以形成該第一區域於該等鰭狀結構之一者內以及該第二區域於該第一區域下方；以及進行該熱處理製程將摻質由該第一區域向下擴散以及摻質由該第一井區擴散至第二區域以形成該第二井區。
  7. 如申請專利範圍第6項所述之方法，其中在進行該熱處理製程前，該第一區域係為一摻雜區且該第二區域係為一無摻雜區。
  8. 如申請專利範圍第1項所述之方法，另包含：形成一閘極介電層於該等鰭狀結構上；進行該第二離子佈植製程；以及形成一閘極結構於各該射極區、該基極區以及該集極區上。
  9. 如申請專利範圍第1項所述之方法，其中該第二井區之濃度低於該第一井區之濃度。
  10. 一種雙極性電晶體，包含：一基底，該基底具有一射極區、一基極區以及一集極區；一淺溝隔離設於該射極區以及該基極區之間；一第一井區設於該基極區內；以及一第二井區設於該射極區內，其中該第二井區由上而下包含一第一區域及一第二區域，該第一區域及該第二區域包含相同導電型式，且該第一井區以及該第二井區包含不同濃度，該淺溝隔離接觸該第一井區及該第二井區，部分該第二井區係設於該淺溝隔離正下方且該第一井區底表面切齊該第二井區底表面。
  11. 如申請專利範圍第10項所述之雙極性電晶體，另包含一深井區設於該射極區、該基極區以及該集極區下方。
  12. 如申請專利範圍第11項所述之雙極性電晶體，另包含一第三井區設於該集極區內。
  13. 如申請專利範圍第12項所述之雙極性電晶體，其中該第一井區及該第二井區包含第一導電型式且該深井區及該第三井區包含第二導電型式。
  14. 如申請專利範圍第13項所述之雙極性電晶體，其中該第一導電型式包含P型且該第二導電型式包含N型。
  15. 如申請專利範圍第10項所述之雙極性電晶體，另包含複數 個鰭狀結構於該基底上，其中該第一井區及該第二井區係設於該等鰭狀結構內。
  16. 如申請專利範圍第15項所述之雙極性電晶體，另包含：一閘極介電層設於該等鰭狀結構上；以及一閘極結構於各該射極區、該基極區以及該集極區上。
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