CN103137500A - 制造半导体器件的方法 - Google Patents
制造半导体器件的方法 Download PDFInfo
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- CN103137500A CN103137500A CN2012104955991A CN201210495599A CN103137500A CN 103137500 A CN103137500 A CN 103137500A CN 2012104955991 A CN2012104955991 A CN 2012104955991A CN 201210495599 A CN201210495599 A CN 201210495599A CN 103137500 A CN103137500 A CN 103137500A
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Abstract
本文公开一种制造半导体器件的方法,包括:堆叠多个半导体芯片以形成第一芯片层叠体,提供底部填料以填充半导体芯片之间的间隙,使得在第一芯片层叠体周围形成填角部分,以及修整填角部分以形成第二芯片层叠体。
Description
技术领域
本发明涉及一种制造半导体器件的方法,且更具体地涉及一种制造具有多个彼此堆叠的半导体芯片的半导体器件的方法。
背景技术
近年来,半导体芯片的集成密度逐年提高,这致使芯片尺寸增大并促进布线的小型化和多层结构。同时,为了实现高密度安装,需要将半导体器件制造成具有更小尺寸并更薄。
为了契合上述需求,已经研发出一种被称为MCP(多芯片封装)的技术,该技术以高密度方式将多个半导体芯片安装到一个封装衬底上。
特别地,被称为CoC(芯片上芯片)型的半导体器件已经得到关注。CoC型半导体器件包括由多个彼此堆叠的半导体芯片构成的堆叠体。在CoC型半导体器件中,各个半导体芯片都例如具有约50μm或更小的厚度并具有被称为TSV(硅通孔)的贯穿电极。
日本专利申请特开No.2010-251347公开了一种制造CoC型半导体器件的方法,该方法通过堆叠多个半导体芯片,同时连接半导体芯片的贯穿电极,形成第一密封树脂层(底部填料),以覆盖多个堆叠的半导体芯片(以下称为“芯片层叠体”)的***并填充半导体芯片之间的间隙,以及在其上形成了预定布线的封装衬底上连接并固定其上形成了第一密封树脂层的芯片层叠体。
但是,根据日本专利申请特开No.2010-251347中公开的制造半导体器件的方法,在填充了底部填料(第一密封树脂层)的芯片堆叠体周围,由于底部填料导致会形成填角(fillet)。取决于填角的扩展程度,其上已经形成了底部填料的芯片层叠体(即,换言之,由底部填料和芯片层叠体构成的结构)的外部尺寸变得不规则,这致使不能管理外部尺寸。
如果上述填角较大,则担心每次在将其上形成了底部填料的芯片层叠体安装到封装衬底的处理以及后续处理中加热芯片层叠体时,由于填角部分膨胀和收缩,应力会施加至构成芯片层叠体的薄半导体芯片。
如果应力施加至芯片层叠体,则担心会在芯片中出现裂纹,或者在半导体芯片被连接在一起的凸块接合区域可能破裂。
发明内容
在本发明的一个方面中,提供一种制造半导体器件的方法,该方法包括:堆叠多个半导体芯片以形成第一芯片层叠体;提供底部填料以填充半导体芯片之间的间隙,从而在第一芯片层叠体周围形成填角部分;以及修整填角部分以形成第二芯片层叠体。
在本发明的另一方面中,提供一种制造半导体器件的方法,该方法包括:堆叠多个半导体芯片以在相邻的半导体芯片之间形成间隙;向相邻的半导体芯片之间的间隙提供密封树脂,从而使一部分密封树脂从至少一个半导体芯片的一侧表面突出;以及修整密封树脂的突出部分以形成平坦表面。
根据本发明的上述方面,能避免第二芯片层叠体的外形的差异,因为填角部分已经被修整。因此能管理第二芯片层叠体的外部尺寸。
因为第二芯片层叠体的外部尺寸变得稳定,因此能改善第二芯片层叠体由处理时的外力造成的应力。
此外,因为修整了填角部分,因此能在加热具有底部填料的第二芯片层叠体时降低底部填料的应力。
因此能避免制造得较薄的半导体芯片(例如具有50μm或更小厚度的半导体芯片)破裂或芯片裂纹,以及半导体芯片之间的连接部(接合区域)的破裂。
此外,第二芯片层叠体在尺寸上可更小,因为填角部分被修整。因此,采用第二芯片层叠体的半导体器件在尺寸上可更小。
附图说明
图1是根据本发明第一实施例的半导体器件的截面图;
图2至5、6A、6B、7A、7B、8、9、10A、10B以及11至16是示出制造根据本发明第一实施例的半导体器件的工艺的示意图;
图17是根据本发明第二实施例的半导体器件的截面图;
图18是根据本发明第三实施例的半导体器件的截面图;
图19是根据本发明第四实施例的半导体器件的截面图;以及
图20至24是示出制造根据本发明第四实施例的半导体器件的工艺的示意图。
具体实施方式
以下,将参考附图详细说明本发明的实施例。顺便提及,以下说明书中采用的附图用于说明本发明实施例的构造。附图中所示的各个部分的大小、厚度、尺寸以及其他因素可与实际半导体器件的尺寸关系不同。
(第一实施例)
现在参考图1,第一实施例的半导体器件10是CoC(芯片上芯片)型半导体器件。半导体器件10包括布线衬底11、布线凸块12、具有底部填料的芯片层叠体13、第一密封树脂14、第二密封树脂15以及外部连接端子17。
布线衬底11包括布线衬底本体21、连接盘22、布线24、第一阻焊剂25、外部连接盘26、贯穿电极28以及第二阻焊剂29。
布线衬底本体21是矩形的绝缘衬底,并具有平坦表面21a(布线衬底11的主表面)以及背表面21b。对于布线衬底本体21来说,例如可采用玻璃环氧树脂板。
连接盘22提供在布线衬底本体21的表面21a的中心部。连接盘22布置为面对构成具有底部填料的芯片层叠体13的第二半导体芯片39的表面凸块电极56。
各个连接盘22都包括凸块安装表面22a,其面对第二半导体芯片39的相关联的一个表面凸块电极56。
布线24是重布线导线(rewired line),并连接至连接盘22。第一阻焊剂25提供在布线衬底本体21的表面21a上以覆盖布线24。第一阻焊剂25允许暴露连接盘22的凸块安装表面22a。
外部连接盘26提供在布线衬底本体21的背表面21b上。各个外部连接盘26都包括端子安装表面26a。
贯穿电极28贯穿布线衬底本体21,各个贯穿电极28都位于相关联的一个布线24和相关联的一个外部连接盘26之间。各个贯穿电极28的一端连接至相关联的一个布线24,且另一端连接至相关联的一个外部连接盘26。
第二阻焊剂29提供在布线衬底本体21的背表面21b上使得外部连接盘26的端子安装表面26a暴露。
布线凸块12布置在连接盘22的凸块安装表面22a上。对于布线凸块12来说,例如可采用Au凸块。
具有底部填料的芯片层叠体13包括芯片层叠体33和底部填料34。
芯片层叠体33形成为具有第一半导体芯片35和第二半导体芯片36至39,它们是多个半导体芯片。
第一半导体芯片35是具有底部填料的芯片层叠体13安装在布线衬底11上的情况(即如图1中所示情况)下布置在顶层的半导体芯片。
例如,对于第一半导体芯片35来说,可采用半导体存储芯片。在这种情况下,作为第一半导体芯片35,例如可采用DRAM(动态随机存取存储器)。
以下说明采用DRAM作为第一半导体芯片35的示例。
第一半导体芯片35包括:第一芯片本体43,其具有一个平坦表面43a以及另一表面43b;以及多个表面凸块电极45(第一凸块电极)。第一芯片本体43呈矩形,并包括半导体衬底47和电路元件层48。
半导体衬底47是制造得较薄(例如50μm或更小的厚度)的衬底。对于半导体衬底47来说,例如可采用单晶硅衬底。半导体衬底47具有为平坦平面的表面47a以及背表面47b。
电路元件层48形成在半导体衬底47的表面47a上。电路元件层48包括示意图中未示出的晶体管、多个堆叠的层间绝缘膜以及形成在多个层间绝缘膜上的布线图案(通孔和布线)。在电路元件层48上,形成DRAM元件(未示出)。
表面凸块电极45提供在电路元件层48的表面48a上(或形成在第一芯片本体43的另一表面43b上)。表面凸块电极45电连接到形成在电路元件层48上的DRAM元件。
在将具有底部填料的芯片层叠体13安装到布线衬底11上之后,表面凸块电极45面对布线衬底本体21的表面21a。
对于表面凸块电极45来说,例如可采用Cu/Ni/Au叠层膜,Cu/Ni/Au叠层膜是通过在电路元件层48的表面48a上顺序堆叠Cu膜、Ni膜以及Au膜而制成的。Cu/Ni/Au叠层膜可通过镀敷制成。
第一半导体芯片35是在下文参考图4说明的工艺(或形成芯片叠层图33的工艺)中布置在底层上的半导体芯片。
第二半导体芯片36布置在第一半导体芯片35的正下方。对于第二半导体芯片36来说,例如可采用半导体存储芯片。在这种情况下,作为第二半导体芯片36,例如也可采用DRAM(动态随机存取存储器)。
以下说明采用DRAM作为第二半导体芯片36的示例。
第二半导体芯片36包括第二芯片本体52、多个贯穿电极54、多个背表面凸块电极55(一部分第二凸块电极)以及多个表面凸块电极56(从底部填料34中暴露的另一部分第二凸块电极)。
第二芯片本体52具有与在第一半导体芯片35上提供的第一芯片本体43相同的构造。即,第二芯片本体52包括半导体衬底47以及电路元件层48。此外,第二芯片本体52的外形在大小上与矩形的第一芯片本体43相同。
贯穿电极54被提供为穿过位于表面凸块电极45下方的第二芯片本体52的一部分。贯穿电极54电连接到在第二芯片本体52的电路元件层48上提供的DRAM元件。
背表面凸块电极55提供在贯穿电极54的一端。背表面凸块电极55连接(结合)至第一半导体芯片35的表面凸块电极45。即,第一半导体芯片35和第二半导体芯片36是倒装芯片安装的。
对于背表面凸块电极55来说,例如可采用Cu/SnAg叠层膜,Cu/SnAg叠层膜是通过在贯穿电极54的一端上顺序堆叠Cu膜和SnAg焊料膜而制成的。Cu/SnAg叠层膜可通过镀敷形成。
表面凸块电极56提供在贯穿电极54的另一端上(或电路元件层48的表面48a上)。因此,表面凸块电极56电连接到形成在电路元件层48上的DRAM元件,并且经由贯穿电极54电连接到背表面凸块电极55。
在将具有底部填料的层叠体13安装在布线衬底11上之后,表面凸块电极56面对布线衬底本体21的表面21a。
对于表面凸块电极56来说,例如可采用Cu/Ni/Au叠层膜,Cu/Ni/Au叠层膜是通过在电路元件层48的表面48a上顺序堆叠Cu膜、Ni膜以及Au膜而制成的。Cu/Ni/Au叠层膜可通过镀敷制成。
第二半导体芯片37布置在第二半导体芯片36的正下方。第二半导体芯片37具有与第二半导体芯片36相同的构造。
第二半导体芯片37的背表面凸块电极55连接(结合)到第二半导体芯片36的表面凸块电极56。即,第二半导体芯片36和37是倒装芯片安装的。
因此,第二半导体芯片37电连接到第一半导体芯片35和第二半导体芯片36。
在具有底部填料的芯片层叠体13被安装到布线衬底11上之后,第二半导体芯片37的表面凸块电极56面对布线衬底本体21的表面21a。
第二半导体芯片38布置在第二半导体芯片37的正下方。第二半导体芯片38与第二半导体芯片36的构造相同。
第二半导体芯片38的背表面凸块电极55连接(结合)到第二半导体芯片37的表面凸块电极56。即,第二半导体芯片37和38是倒装芯片安装的。
因此,第二半导体芯片38电连接到第一和第二半导体芯片35、36和37。
在具有底部填料的芯片层叠体13被安装到布线衬底11上之后,第二半导体芯片38的表面凸块电极56面对布线衬底本体21的表面21a。
第二半导体芯片39布置在第二半导体芯片38的正下方。第二半导体芯片39是在具有底部填料的芯片层叠体13被安装到布线衬底11上的情况(即,如图1中所示的情况)下布置在底层上的半导体芯片。
对于第二半导体芯片39来说,例如可采用具有在半导体存储芯片和外部之间的接口功能的半导体芯片。以下说明采用半导体接口芯片作为第二半导体芯片39的示例。
第二半导体芯片39以与第二半导体芯片36相同的方式形成,不同之处在于提供第二芯片本体58替代在第二半导体芯片36上提供的第二芯片本体52。
第二芯片本体58呈矩形。第二芯片本体58的外形在大小上小于第二芯片本体52。第二芯片本体58包括半导体衬底61和电路元件层62。
半导体衬底61是形成得较薄(例如具有50μm或更小的厚度)的衬底。对于半导体衬底61来说,例如可采用单晶硅衬底。半导体衬底61具有为平坦平面的表面61a以及背表面61b。
电路元件层62形成在半导体衬底61的表面61a上。电路元件层62包括在示意图中未示出的晶体管、多个堆叠的层间绝缘膜以及形成在多个层间绝缘膜上的布线图案(通孔和布线)。电路元件层62包括接口元件(未示出)。
第二半导体芯片39的背表面凸块电极55提供在位于半导体衬底61的背表面侧上的贯穿电极54的一端。第二半导体芯片39的背表面凸块电极55连接(结合)到第二半导体芯片38的表面凸块电极56。即,第二半导体芯片38和39是倒装芯片安装的。
第二半导体芯片39的表面凸块电极56提供在位于电路元件层62的表面62a侧上的贯穿电极54的另一端。第二半导体芯片39的表面凸块电极56电连接到形成在电路元件层62上的接口元件。
第二半导体芯片39的表面凸块电极56布置为面对连接盘22的凸块安装表面22a。
第二半导体芯片39的表面凸块电极56是用作具有底部填料的芯片层叠体13的外部连接端子的电极。表面凸块电极56经由布线凸块12电连接到布线衬底11的连接盘22。
因此,具有底部填料的芯片层叠体13倒装芯片安装在布线衬底11上。
第二半导体芯片39是作为在堆叠并安装在第二半导体芯片39上的半导体存储芯片35至38与布线衬底11之间的信息交互的媒介的半导体芯片。
第二半导体芯片39是布置在下文参考图4的工艺(或形成芯片层叠体33的工艺)中的顶层上的半导体芯片。
构成芯片层叠体33的第一和第二半导体芯片35至38的侧表面35a、36a、37a和38a与平面A平齐,该平面A垂直于布线衬底本体21的表面21a。
换言之,第一和第二半导体芯片35至38的侧表面35a、36a、37a和38a布置在同一平面A上。
在堆叠并安装的第一和第二半导体芯片35至38之间形成窄的间隙。在构成芯片层叠体33的第二半导体芯片39和布线衬底11之间形成间隙。
底部填料34填充构成芯片层叠体33的第一和第二半导体芯片35至39之间的间隙。此外,底部填料34布置为覆盖第一和第二半导体芯片35至38的侧表面35a、36a、37a和38a。
底部填料34允许构成第二半导体芯片39的电路元件层62的表面62a和表面凸块电极56暴露。
通过毛细现象形成底部填料34。修整布置在芯片层叠体33的四个侧壁上的填角部分34-1。修整的填角部分34-1在宽度上比没有修整的填角部分窄。修整的填角部分34-1还具有平面34a,其平行于第一和第二半导体芯片35至39的侧表面35a、36a、37a、38a以及39a延伸。
提供围绕芯片层叠体33的四个平面34a以面对芯片层叠体33的各个侧壁(四个侧壁)。
底部填料34的平面34a布置在第一和第二半导体芯片35至38的侧表面35a、36a、37a以及38a的附近。
第一和第二半导体芯片35至38的侧表面35a、36a、37a以及38a(平面A)与底部填料34的平面34a之间的距离B例如是50μm。
以此方式修整填角部分34-1。还提供具有四个平面34a的底部填料34:该四个平面34a平行于第一和第二半导体芯片35至39的侧表面35a、36a、37a、38a和39a延伸并布置在第一和第二半导体芯片35至38的侧表面35a、36a、37a和38a附近。因此能避免填角部分34-1的形状差异。因此能避免可能由于填角部分34-1的形状差异而导致的具有底部填料的芯片层叠体13的外形的差异。
因此,变得能管理具有底部填料的芯片层叠体13的外部尺寸。
因为具有底部填料的芯片层叠体13的外部尺寸变得稳定,因此可改善具有底部填料的芯片层叠体13在处理时的外力造成的应力。
此外,修整填角部分34-1。因此能在加热具有底部填料的芯片层叠体13时降低底部填料34的应力。
因此能避免制造得较薄(例如具有50μm或更小厚度的半导体芯片)的第一和第二半导体芯片35至39的破裂(芯片裂纹)以及在第一和第二半导体芯片35至39之间的连接部分(接合区域)的破裂。
对于底部填料34来说,例如可采用热固性树脂(或更具体地,热固性环氧树脂)。
第一密封树脂14填充具有底部填料的芯片层叠体13(或更具体地,第二半导体芯片39)和布线衬底11之间的间隙。第一密封树脂14布置为覆盖从底部填料34暴露的第二半导体芯片39。
以此方式,第一密封树脂14加固具有底部填料的芯片层叠体13和布线衬底11之间的连接部分(接合区域)。
对于第一密封树脂14来说,例如可采用NCP(非导电浆体)。
第二密封树脂15提供在构成布线衬底11的第一阻焊剂25的上表面25a(布线衬底11的主表面)上,以便覆盖具有底部填料的芯片层叠体13和第一密封树脂14。第二密封树脂15的上表面15a是平面。
对于第二密封树脂15来说,例如可采用模制树脂。
外部连接端子17提供在外部连接盘26的端子安装表面26a上。外部连接端子17是在半导体器件10安装在诸如主板的电路板上时,连接到板的焊盘的端子。
对于外部连接端子来说,例如可采用焊球。
根据第一实施例的半导体器件,提供具有底部填料的芯片层叠体13,其包括:芯片层叠体33,其上堆叠并安装第一和第二半导体芯片35至38;以及底部填料34,其填角部分34-1被修整,且包括平行于第一和第二半导体芯片35至39的侧表面35a、36a、37a、38a、39a延伸并布置在第一和第二半导体芯片35至38的侧表面35a、36a、37a和38a的附近的四个平面34a。因此能抑制填角部分34-1的形状差异。因此能避免由于填角部分34-1的形状差异而导致的具有底部填料的芯片层叠体13的外形的差异。
因此能管理具有底部填料的芯片层叠体13的外部尺寸。
因为具有底部填料的芯片层叠体13的外部尺寸变得稳定,因此可改善具有底部填料的芯片层叠体13的处理时的外力导致的应力。
此外,修整填角部分34-1。因此能在加热具有底部填料的芯片层叠体13时降低底部填料34的应力。
因此能避免制造得较薄(例如具有50μm或更小厚度的半导体芯片)的第一和第二半导体芯片35至39的破裂(芯片裂纹)以及第一和第二半导体芯片35至39之间的连接部分(接合区域)的破裂。
因为修整了填角部分34-1,因此具有底部填料的芯片层叠体13可制造成具有更小的大小。因此,其上安装了具有底部填料的芯片层叠体13的布线衬底11可制造成具有更小的大小。
此外,因为布线衬底11的大小变得更小,因此具有布线衬底11和具有底部填料的芯片层叠体13的半导体器件10的大小也可以变得更小。
将参考图2至5、6A、6B、7A、7B、8、9、10A、10B以及11至16说明根据本发明第一实施例的制造半导体器件10的工艺。
图2至5、6A、8、9以及11至15是制造过程中的半导体器件10的截面图。图6B是图6A中所示的制造过程中的半导体器件10的平面图。
图7A是制造过程中的半导体器件10的平面图。图7B是图7A中所示的结构沿线E-E截取的截面图。
图10A是制造过程中的图10B中所示的半导体器件沿线C-C截取的截面图。图10B是制造过程中的半导体器件10的平面图。图17是多个制成的半导体器件10的截面图。
在图2至5、6A、6B、7A、7B、8、9、10A、10B以及11至16中,与第一实施例的半导体器件10相同的部件由相同的附图标记表示。
参考图2至5、6A、6B、7A、7B、8、9、10A、10B以及11至16,将说明制造第一实施例的半导体器件10的方法。
首先在图2中所示的工艺中,作为多个半导体芯片来说,制备以下芯片:第一半导体芯片35,包括第一芯片本体43和表面凸块电极45,第一芯片本体43的一个表面43a(半导体衬底47的背表面47b)是平坦平面,表面凸块电极45布置在第一芯片本体43的另一表面43b(电路元件层48的表面48a)上;第二半导体芯片36至38,其每一个包括第二芯片本体52、穿过第二芯片本体52的贯穿电极54、布置在贯穿电极54的一端的背表面凸块电极55以及布置在贯穿电极54的另一端的表面凸块电极56;以及第二半导体芯片39,其包括第二芯片本体58、穿过第二芯片本体58的贯穿电极54、布置在贯穿电极54的一端的背表面凸块电极55以及布置在贯穿电极54的另一端的表面凸块电极56。
此时,对于第一和第二半导体芯片35至38来说,采用矩形半导体存储芯片(或更具体地,例如DRAM)。对于第二半导体芯片39来说,采用用于接口功能的矩形半导体芯片。
在说明图3中所示的工艺之前,将说明在图3中所示的工艺中采用的结合装置66的示意性构造。
如图3中所示,结合装置66包括载物台67和结合工具68。载物台67包括衬底安装表面67a和第一吸附孔71。
衬底安装表面67a是其上放置半导体芯片或布线衬底的平面,且为平坦平面。
第一吸附孔71从衬底安装表面67a暴露并设计为拉住放置在衬底安装表面67a上的诸如半导体芯片或布线衬底的衬底。
顺便提及,虽然在图中未示出,但是载物台67包括加热朝向衬底安装表面67a被拉住的衬底的加热器。
结合工具68包括吸附表面68a、第二吸附孔73以及加热器74。吸附表面68a是与结合工具68拉住的半导体芯片接触的平面。第二吸附孔73从吸附表面68a暴露,并被设计成拉住半导体芯片。加热器74加热已被拉住的半导体芯片。
下文说明图3中所示的工艺。
在图3中所示的工艺中,以致结合装置66的载物台67的衬底安装表面67a与第一芯片本体43的一个表面43a(半导体衬底47的背表面47b)接触这样的方式,将第一半导体芯片35拉住在载物台67上。
随后,以致电路元件层48的表面48a面对吸附表面68a的方式,结合工具68用于拉住第二半导体芯片36。随后,随着移动结合工具68,第二半导体芯片36的背表面凸块电极55以及第一半导体芯片35的表面凸块电极45被布置为彼此面对。
随后,在高温(例如约300摄氏度)下加热第一半导体芯片35和第二半导体芯片36。在构成背表面凸块电极55的SnAg焊料膜熔化之后,向下移动结合工具68。结果,背表面凸块电极55接触表面凸块电极45,并向其施加负载。以此方式,执行背表面凸块电极55和表面凸块电极45的热压结合。
结果,在第一半导体芯片35上倒装芯片安装了第二半导体芯片36。此外,在第一半导体芯片35和第二半导体芯片36之间形成间隙。
在图4中所示的工艺中,以类似于在第一半导体芯片35上倒装芯片安装第二半导体芯片36的工艺的方式,执行第二半导体芯片36的表面凸块电极56和第二半导体芯片37的背表面凸块电极55的热压结合。以此方式,在第二半导体芯片36上倒装芯片安装了第二半导体芯片37。此时,在第二半导体芯片36和37之间形成间隙。
接下来,以类似于在第一半导体芯片35上倒装芯片安装第二半导体芯片36的工艺的方式,执行第二半导体芯片37的表面凸块电极56和第二半导体芯片38的背表面凸块电极55的热压结合。以此方式,在第二半导体芯片37上倒装芯片安装了第二半导体芯片38。此时,在第二半导体芯片37和38之间形成间隙。
随后,以类似于在第一半导体芯片35上倒装芯片安装第二半导体芯片36的工艺的方式,执行第二半导体芯片38的表面凸块电极56和第二半导体芯片39的背表面凸块电极55的热压结合。以此方式,在第二半导体芯片38上倒装芯片安装了第二半导体芯片39。此时,在第二半导体芯片38和39之间形成间隙。
以此方式,通过贯穿电极54、背表面凸块电极55以及表面凸块电极56,在第一半导体芯片35上堆叠并安装第二半导体芯片36至39。因此形成了由堆叠并安装的第一和第二半导体芯片35至39构成的芯片层叠体33。
当第二半导体芯片36至39安装在第一半导体芯片35上时,其外形大小相同的第一和第二半导体芯片35至38的侧表面面35a、36a、37a和38a被布置为与平面A平齐,该平面A垂直于载物台67的衬底安装表面67a。
顺便提及,当第二半导体芯片36至39倒装芯片安装时,也可以与负载一起施加超声波。
在图5中所示的工艺中,以在芯片层叠体33周围形成填角部分34-1的方式,形成填充构成芯片层叠体33的第一和第二半导体芯片35至39之间间隙的底部填料34(例如热固性树脂)。
以此方式,形成了包含芯片层叠体33和具有填角部分34-1的底部填料34的结构82(即,具有底部填料的芯片层叠体13,底部填料的填角部分34-1还未被修整)。
更具体而言,当热固性树脂用作底部填料34时,底部填料34以如下方式形成。
首先,芯片层叠体33布置为使附接至载物台77的平坦表面77a的片材78接触第一芯片本体43的一个表面43a。
随后,通过分配器79将液态底部填料34的液滴置于芯片层叠体33的四个侧壁中的一个上。因此,第一和第二半导体芯片35至39之间的间隙通过毛细现象被密封。
此时,在图5中所示的情况下,布置在顶层的第二半导体芯片39的电路元件层62的上表面62a以及表面凸块电极56从液态底部填料34中暴露。
此外,因为芯片层叠体33布置为使片材78接触第一芯片本体43的一个表面43a(半导体衬底47的背表面47b),因此底部填料34并未形成在半导体衬底47的背表面47b上。
随后,以预定温度(例如140摄氏度)固化液态底部填充树脂34。结果,形成了具有填角部分34-1的底部填料34。
在图6A和6B中所示的工艺中,如图5中所示的具有填角部分34-1的结构82从片材78上拾取下来。
在此阶段,如图6A中所示,在芯片层叠体33周围的四个侧壁上形成了没有被修整的填角部分34-1。
此外,在图5中所示的工艺中,液态底部填充树脂34的液滴从位于图6A中所示的芯片层叠体33的右侧上的一侧(侧壁)放置。因此,液态底部填充树脂34沿图6B中所示的“D”方向流动。
因此,形成在图6A中所示的芯片层叠体33的右侧上的填角部分34-1比形成在芯片层叠体33的左侧上的填角部分34-1更宽。
顺便提及,随着执行图1至5、6A和6B中所示的工艺,形成多个结构82。
在图7A和7B中所示的工艺中,切割带86附接到环形夹具85的内部。在切割带86的上表面86a上,以预定间隔(或更具体地,使得能够在后续参考图8和9说明的工艺中利用切割刀片89适当执行填角部分34-1的修整的间隔)附接多个结构82。
此时,以切割带86的上表面86a接触第一芯片本体43的一个表面43a(半导体衬底47的背表面47b)的方式,多个结构82附接到切割带86的上表面86a。
在图8中所示的工艺中,切割刀片89用于修整形成在芯片层叠体33的四个侧壁上的四个填角部分34-1中的一个。结果,形成平面34a:平面34a布置在第一和第二半导体芯片35至38的侧表面35a、36a、37a和38a附近并平行于第一和第二半导体芯片35至39的侧表面35a、36a、37a、38a和39a延伸。
此时,第一和第二半导体芯片35至38的侧表面35a、36a、37a和38a(即平面34A)与底部填料34的平面34a之间的距离例如是50μm。
在图9中所示的步骤中,以与图8中所示工艺相同的方式,顺序地修整还未被修整的其余三个填角部分34-1,由此形成三个平面34a。
以此方式,具有底部填料的芯片层叠体13形成为包括:芯片层叠体33,其由堆叠并安装的第一和第二半导体芯片35至39构成;以及底部填料34,其密封第一和第二半导体芯片35至39之间的间隙并且对于四个修整了填角部分34-1具有平面34a。
以此方式,修整在芯片层叠体33的四个侧壁上形成的填角部分34-1以形成平行于第一和第二半导体芯片35至38的侧表面35a、36a、37a以及38a延伸的平面34a。结果,能抑制具有底部填料的芯片层叠体13的外部尺寸的差异。
因此,变得能够管理具有底部填料的芯片层叠体13的外部尺寸。
因为具有底部填料的芯片层叠体13的外部尺寸变得稳定,因此可改善具有底部填料的芯片层叠体13在处理时由外力造成的应力。
此外,修整填角部分34-1。因此能在加热具有底部填料的芯片层叠体13时降低底部填料34的应力。
因此能避免制造得较薄(例如具有50μm或更小厚度的半导体芯片)的第一和第二半导体芯片35至39的破裂(芯片裂纹)以及第一和第二半导体芯片35至39之间的连接部分(接合区域)的破裂。
因为修整了填角部分34-1,因此可以使得具有底部填料的芯片层叠体13在大小上更小。结果,可以使得其上安装了具有底部填料的芯片层叠体13的布线衬底11在大小上更小。
此外,因为布线衬底11在大小上变得更小,因此具有布线衬底11和具有底部填料的芯片层叠体13的半导体器件10(参见图1)也可以在大小上更小。
顺便提及,在图8和9中所示的工艺中,作为通过切削操作修整填角部分34-1的示例,已经说明了采用切割装置(切割刀片89)的示例。但是,除了切割装置之外的切削装置也可用于修整填角部分34-1。
抛光装置可用于抛光并修整填角部分34-1。切割操作和抛光操作可组合使用以修整填角部分34-1。
在图10A和10B中所示的工艺中,其上已经形成了图9中所示的四个平面34a的具有底部填料的芯片层叠体13从切割带86上拾取下来。
在图11中所示的工艺中,制备具有多个布线衬底形成区域F以及切割线G的绝缘衬底92:切割线G划分出多个布线衬底形成区域F。
随后,采用公知方法在绝缘衬底92上形成连接盘22、布线24、第一阻焊剂25、外部连接盘26、贯穿电极28以及第二阻焊剂29。
结果,形成了布线主板衬底93,在布线主板衬底93上在多个布线衬底形成区域F中形成了布线衬底11。在这个阶段,多个布线衬底11仍然连接在一起,而没有分成单独的片。
随后,在连接盘22的凸块安装表面22a上形成作为布线凸块12的Au凸块。
更具体而言,Au布线的顶端通过放电而熔化,从而形成球。随后采用超声波将球结合到连接盘22的凸块安装表面22a。随后切削Au布线。以此方式形成球。顺便提及,必要时可执行整平以便Au凸块的高度变得一致。
随后,在对应于具有底部填料的芯片层叠体13的安装区域的第一阻焊剂25的上表面25a上,通过分配器95提供液态第一密封树脂14(例如NCP(非导电浆体))。
结果,形成在布线衬底11上的多个连接盘22和布线凸块12被液态第一密封树脂14覆盖。
液态第一密封树脂14形成在构成布线主板衬底93的所有布线衬底11上。
随后,在图12中所示的工艺中,将其上形成了布线凸块12和液态第一密封树脂14的布线主板衬底93放置在载物台67的衬底安装表面67a上。此时,布线主板衬底93放置为使绝缘衬底92的背表面92b面对载物台67的衬底安装表面67a。
随后,采用结合工具68拉住构成图10A中所示的具有底部填料的芯片层叠体13的半导体衬底47的背表面47b。以此方式,拾取具有底部填料的芯片层叠体13。
随后,移动结合工具68,且布线凸块12以及具有底部填料的芯片层叠体13的表面凸块电极56布置为彼此面对。
随后,在高温下(例如300摄氏度)采用结合工具68加热具有底部填料的芯片层叠体13,同时对具有底部填料的芯片层叠体13施加负载。以此方式,将具有底部填料的芯片层叠体13压到液态第一密封树脂14上。
以此方式,执行表面凸块电极56和布线凸块12的热压结合。因此,在布线衬底11上倒装芯片安装了具有底部填料的芯片层叠体13。此外,布线衬底11和具有底部填料的芯片层叠体13之间的间隙由固化的第一密封树脂14密封。
顺便提及,在图12中所示的工艺中,在构成布线主板衬底93的所有布线衬底11上都倒装芯片安装具有底部填料的芯片层叠体13。
在图13中所示的步骤中,从图12中所示的结合装置66上取下布线主板衬底93,在布线主板衬底93上形成了多个具有底部填料的芯片层叠体13和第一密封树脂14。
随后,在构成布线主板衬底93的第一阻焊剂25的上表面25a上密封多个具有底部填料的芯片层叠体13和第一密封树脂14。此外,形成其上表面15a是平坦平面的第二密封树脂15。
对于第二密封树脂15来说,例如可采用模制树脂。在这种情况下,第二密封树脂15例如可由传递模制方法形成。
如果采用传递模制方法,则在上部模具和下部模具之间形成的空间中,放置图12中所示的结构(除结合装置66之外)。随后,将受热并熔化的树脂(或用于第二密封树脂15的基材)注入该空间中。
随后,在预定温度下(例如约180摄氏度)加热(或固化)熔化的树脂。随后在预定温度下烘烤该树脂。以此方式,完全固化模制树脂。结果,形成第二密封树脂15。作为用于第二密封树脂15的基材的树脂可以是热固性树脂,例如环氧树脂。
在图14中所示的工艺中,上下颠倒图13中所示的结构。随后,在形成在多个布线衬底11(即布线主板衬底93)上的多个外部连接盘26上形成外部连接端子17。对于外部连接端子17来说,例如采用焊球。
如果焊球用作外部连接端子17,则采用以下方法在多个外部连接盘26上形成外部连接端子17。
首先,采用球安装器的安装工具98拉住并保持多个焊球,同时将焊剂转移并形成在多个焊球上。
随后,在形成在布线主板衬底93上的多个外部连接盘26上放置焊球。此后,对其上形成了焊球的布线主板衬底93进行热处理(回流处理)。以此方式,用作外部连接端子17的焊球形成在外部连接盘26上。
结果,形成多个半导体器件10:半导体器件10包括布线衬底11、具有底部填料的芯片层叠体13、第一密封树脂14、第二密封树脂15以及外部连接端子17,并且连接在一起。
在图15中所示的工艺中,在构成图14中所示的结构(除安装工具98之外)的第二密封树脂15的上表面15a上附接切割带99。
随后,采用切割刀片89沿切割线G切削图14中所示的结构。结果,多个半导体器件10变成单独的片。此时,多个布线衬底11也变成单独的片。
在图16中所示的工艺中,上下颠倒图15中所示的结构(除切割刀片89之外)。随后,从图15中所示的结构上分离切割带99。以此方式,制成多个CoC型半导体器件10。
根据第一实施例的半导体器件的制造方法,因为第一和第二半导体芯片35至39通过贯穿电极54堆叠并安装,因此形成了由堆叠的第一和第二半导体芯片35至39构成的芯片层叠体33。随后,填充第一和第二半导体芯片35至39之间的间隙的底部填料34被形成为使得填角部分34-1形成在芯片层叠体33的周围。随后,修整形成在芯片层叠体33的周围的填角部分34-1以形成具有底部填料的芯片层叠体13,其由芯片层叠体33和底部填料34构成。因此能抑制填角部分34-1的形状差异。因此能抑制由于填角部分34-1的形状差异导致的具有底部填料的芯片层叠体13的外形的差异。
因此变得能够管理具有底部填料的芯片层叠体13的外部尺寸。
因为具有底部填料的芯片层叠体13的外部尺寸变得稳定,因此能改善具有底部填料的芯片层叠体13由处理时的外力造成的应力。
此外,修整了填角部分34-1。因此能在加热具有底部填料的芯片层叠体13时降低底部填料34的应力。
因此能避免制造得较薄(例如具有50μm或更小厚度的半导体芯片)的第一和第二半导体芯片35至39破裂(芯片裂纹),以及第一和第二半导体芯片35至39之间的连接部(接合区域)的破裂。
因为修整了填角部分34-1,因此可以使得具有底部填料的芯片层叠体13在大小上更小。因此可以使得其上安装了具有底部填料的芯片层叠体13的布线衬底11在大小上更小。
此外,因为布线衬底11在大小上变得更小,因此具有布线衬底11和具有底部填料的芯片层叠体13的半导体器件10(参见图1)也可在大小上变得更小。
(第二实施例)
将参考图17说明根据本发明第二实施例的半导体器件。在图17中,与第一实施例的半导体器件10相同的部件由相同的附图标记表示。
如图17中所示,第二实施例的半导体器件110除以下方面之外具有与半导体器件10相同的构造:提供布线衬底111以替代在第一实施例的半导体器件10中提供的布线衬底11;以及提供逻辑半导体芯片113、多个金属引线114以及粘合剂115。
布线衬底111除以下方面之外具有与第一实施例中描述的布线衬底11相同的构造:连接盘22布置在布线衬底本体21的表面21a的***;布线24布置在布线衬底本体21的背表面21b上;连接盘22以及布线24和贯穿电极56连接;以及布线24和外部连接盘26连接。
逻辑半导体芯片113包括具有一个平坦表面117a以及另一表面117b的第三芯片本体117;多个表面凸块电极118(第三凸块电极);以及多个表面凸块电极119(第四凸块电极)。
利用在第三芯片本体117的一个表面117a上提供的粘合剂115,逻辑半导体芯片113结合到布线衬底111的第一阻焊剂25。
第三芯片本体117为矩形,并包括半导体衬底122和电路元件层123。
对于衬底122来说,例如可采用单晶硅衬底。半导体衬底122具有为平坦平面的表面122a以及背表面122b。
电路元件层123形成在半导体衬底122的表面122a上。电路元件层123包括示意图中未示出的晶体管、多个堆叠的层间绝缘膜以及形成在多个层间绝缘膜上的布线图案(通孔和布线)。在电路元件层123上形成逻辑元件(未示出)。
表面凸块电极118提供在电路元件层123的表面123a上(或第三芯片本体117的另一表面117b上)。表面凸块电极118布置在电路元件层123的表面123a的中心部分(即布置在具有底部填料的芯片层叠体13的安装区域中)。
表面凸块电极118连接至具有底部填料的芯片层叠体13的表面凸块电极56。即,具有底部填料的芯片层叠体13倒装芯片安装在结合在布线衬底111上的逻辑半导体芯片113上。
表面凸块电极119提供在电路元件层123的表面123a上。表面凸块电极119布置在电路元件层123的表面123a的***。
表面凸块电极119连接至金属引线114的另一端,金属引线114的一端连接至布线衬底111的连接盘22。
即,逻辑半导体芯片113通过引线接合而连接至布线衬底111。因此,逻辑半导体芯片113电连接到布线衬底111,并电连接芯片层叠体33和布线衬底111。
对于表面凸块电极118和119来说,例如可采用Cu/Ni/Au叠层膜:Cu/Ni/Au叠层膜是通过在电路元件层123的表面123a上顺序堆叠Cu膜、Ni膜和Au膜而制成的。Cu/Ni/Au叠层膜可通过镀敷制成。
第一密封树脂14布置为填充逻辑半导体芯片113和具有底部填料的芯片层叠体13之间的间隙。
第二密封树脂15提供在第一阻焊剂25的上表面25a上(或布线衬底111的主表面上),以这样的方式以便密封具有底部填料的芯片层叠体13、第一密封树脂14、逻辑半导体芯片113以及金属引线114。
第二实施例的半导体器件可实现与第一实施例的半导体器件10相同的有利效果。此外,因为第二实施例的半导体器件包括堆叠的存储半导体芯片(第一和第二半导体芯片35至38)以及逻辑半导体芯片113,因此半导体器件110可具有更高级的功能。
顺便提及,第二实施例中所描述的是逻辑半导体芯片113和布线衬底111通过引线接合连接的示例,如图17中所示。但是以下构造也是可取的:提供图17中所示的贯穿电极54和背表面凸块电极55来替代逻辑半导体芯片113的表面凸块电极119;逻辑半导体芯片113和布线衬底111可通过贯穿电极54电连接。
第二实施例的半导体器件110可通过下述方法制造。
首先制备下列部件:逻辑半导体芯片113,其一个表面117a是平坦表面且在另一表面117b上具有表面凸块电极118和119;以及图10A和10B中所示的具有底部填料的芯片层叠体13,其是通过执行在第一实施例中描述的与图2至5、6A、6B、7A、7B、8、9、10A和10B中相同的工艺而形成的。
随后,以逻辑半导体芯片113的一个表面(半导体衬底122的背表面122b)面对其上提供连接盘22的布线衬底111的主表面(第一阻焊剂25的上表面25a)的方式,结合逻辑半导体芯片113。
随后,在表面凸块电极118上倒装芯片安装具有底部填料的芯片层叠体13。此外,第一密封树脂14形成为密封具有底部填料的芯片层叠体13和逻辑半导体芯片113之间的间隙。随后,通过引线接合连接表面凸块电极119和连接盘22。
随后,在布线衬底111的主表面上,第二密封树脂15形成为密封具有底部填料的芯片层叠体13、第一密封树脂14以及逻辑半导体芯片113。
随后,在布线衬底111相对于主表面的表面(布线衬底本体21的背表面21b)上形成电连接连接盘22的外部连接盘26。
此后,执行第一实施例中描述的与图15和16中所示的相同的工艺。由此制成多个第二实施例的半导体器件110。
第二实施例的半导体器件的制造方法可实现与第一实施例的半导体器件10的制造方法相同的有利效果。此外,因为第二实施例的半导体器件包括堆叠的存储半导体芯片(第一和第二半导体芯片35至38)以及逻辑半导体芯片113,因此半导体器件110可具有更高级的功能。
(第三实施例)
将参考图18说明根据本发明第三实施例的半导体器件。在图18中,与第一实施例的半导体器件10相同的部件由相同的附图标记表示。
如图18中所示,本实施例的半导体器件200与图1中所示的第一实施例的半导体器件100的主要不同之处在于:图1中所示的具有底部填料的芯片层叠体13由具有底部填料的芯片层叠体220替代;以及第二半导体芯片39由第三半导体芯片230替代。
具有底部填料的芯片层叠体220包括芯片层叠体210和底部填料34。
芯片层叠体210由第一半导体芯片35和多个第二半导体芯片36至38构成。类似于第一实施例,对于半导体芯片35至38来说,可采用诸如DRAM的用于存储器的半导体芯片。顺便提及,第三半导体芯片230是与芯片层叠体210不同的部件。
第三半导体芯片230是控制半导体芯片35至38的逻辑芯片。用作逻辑芯片的第三半导体芯片230包括形成在主表面上的多个表面凸块电极231以及形成在背表面上的多个背表面凸块电极232。背表面凸块电极232电连接到对应的贯穿电极233。贯穿电极233和表面凸块电极231连接到示意图中未示出的第三半导体芯片230的内部电路。以表面凸块电极231连接到在布线衬底11上提供的布线凸块22的方式,第三半导体芯片230倒装芯片安装在布线衬底11上。
布线衬底11和第三半导体芯片230之间的空间由第一密封树脂14填充。
根据本实施例,在第三半导体芯片230上安装具有底部填料的芯片层叠体220。第三半导体芯片230和具有底部填料的芯片层叠体220之间的空间由第三密封树脂16填充。对于第三密封树脂16来说,例如可采用NCP(非导电浆体)。
构成芯片层叠体210的半导体芯片35至38经由贯穿电极56电连接在一起。在芯片层叠体210中,底部填料34提供为暴露位于如图18中所示的底层(或工艺过程中的顶层)处的半导体芯片38的表面,以及填充半导体芯片35至38之间的间隙。类似于第一实施例,在底部填料34上形成平行于半导体芯片35至38的侧表面延伸的平面34a。芯片层叠体210的外形由平面34a形成。如图18中所示,以位于底层(或工艺过程中的顶层处)的半导体芯片38的表面凸块电极56连接到作为逻辑芯片的第三半导体芯片230的背表面凸块电极232的方式,芯片层叠体210堆叠并安装在第三半导体芯片230上。
顺便提及,在图18中,位于顶层(或工艺过程中的底层处)的半导体芯片35是具有与其他半导体芯片36至38相同功能的存储芯片。但是,在半导体芯片35上没有形成贯穿电极和背表面凸块电极。半导体芯片35比其他半导体芯片36至38更厚。例如,半导体芯片35形成为具有100μm的厚度,其他半导体芯片36至38形成为具有50μm的厚度。半导体芯片35是布置在作为逻辑芯片的第三半导体芯片230最远端的存储芯片。
顺便提及,在其上沿堆叠方向线性布置贯穿电极56的芯片层叠体210上,随着贯穿电极56膨胀和收缩,制造工艺等过程中的温度变化引起应力。其最大应力施加至布置在布线衬底11最远端的半导体芯片35的贯穿电极的一部分。担心可能发生芯片裂纹。但是根据本实施例,在布置在布线衬底11最远端的半导体芯片35上没有提供贯穿电极和背表面凸块。因此,其上没有提供贯穿电极的半导体芯片35的表面能够经得住应力。因此,可抑制在布置在布线衬底11最远的半导体芯片35上容易发生的芯片裂纹。因此能提高半导体器件200的可靠性。
根据本实施例,类似于第一实施例,底部填料34提供为填充芯片层叠体210的半导体芯片35至38之间的间隙,并具有在芯片层叠体210周围平行于半导体芯片35至38的侧表面35a至38a延伸的平面34a。因此可降低施加至芯片层叠体210的应力。此外能降低由布线衬底11上的具有底部填料的芯片层叠体220所占据的空间。因此可以使得布线衬底11和半导体器件200在大小上更小。
此外,多个存储芯片和逻辑芯片堆叠在一个封装体中。可以使得半导体器件200在水平大小上更小并能实现更高级的功能。与第二实施例不同,逻辑芯片倒装芯片连接到布线衬底11。因此还能提高半导体器件200的速度。
以下将说明制造本实施例的半导体器件200的方法。
首先,制备图2中所示的半导体芯片35至38。通过图3和4中所示的方法堆叠半导体芯片35至38,由此创建芯片层叠体210。此时,并未堆叠图4中所示的半导体芯片39。
随后,具有填角部分34-1的底部填料34通过图5、6A和6B中所示的方法引入到芯片层叠体210。此时,位于顶层的是半导体芯片38;形成在半导体芯片38的主表面上的表面凸块电极56仍然暴露而未被底部填料34覆盖。
随后,通过图7A和7B中所示方法,将芯片层叠体210附接到切割带86。通过图8和9中所示方法,修整底部填料34的填角部分34-1。结果,形成了具有底部填料的芯片层叠体220。
通过图11中所示的方法,将液态第一密封树脂14被供应至布线主板衬底93的表面。随后,将半导体芯片230按压在第一密封树脂14上。因此在半导体芯片230的主表面上提供的表面凸块电极231和在布线衬底11(布线主板衬底93)上提供的布线凸块12结合在一起。以此方式,在布线衬底11(布线主板衬底93)的表面上倒装芯片连接半导体芯片230。
随后,液态第三树脂16被供应至半导体芯片230的背表面。通过图12中所示的方法,将具有底部填料的芯片层叠体220按压在第三密封树脂16上。结果,在半导体芯片230的背表面上提供的背表面凸块电极232以及在半导体芯片38的主表面上形成的表面凸块电极56结合在一起。以此方式,在半导体芯片230的背表面上倒装芯片连接具有底部填料的芯片层叠体220。
此后,通过图13至16中所示方法,执行模制和切割。结果,获得半导体器件200。
(第四实施例)
将参考图19说明根据本发明第四实施例的半导体器件。在图19中,与第三实施例的半导体器件200相同的部件由相同的附图标记表示。
如图19中所示,本实施例的半导体器件300与图18中所示的第三实施例的半导体器件200的主要不同在于作为逻辑芯片的图18中所示的半导体芯片230安装在不同于具有底部填料的芯片层叠体220的平面的平面上。
具有底部填料的芯片层叠体220和半导体芯片230倒装芯片连接至硅***物240的表面上的相互不同的平面。硅***物240安装在布线衬底11上并用作一种类型的再布线层。
本实施例的半导体器件300可实现与上述第三实施例的半导体器件200相同的有利效果。此外,具有底部填料的芯片层叠体220和半导体芯片230安装在相互不同的平面上。因此具有底部填料的芯片层叠体220和半导体芯片230能更灵活地组合。此外,无需在作为逻辑芯片的第三半导体芯片230上提供贯穿电极。因此可降低半导体芯片230的制造成本。
以下将说明制造本实施例的半导体器件300的方法。
首先,如图20中所示,制备布线主板衬底93,其具有由切割线G划分的多个布线衬底形成区域F。布线衬底形成区域F是最后变成布线衬底11的区域。
在将液态第一密封树脂14供应至布线衬底形成区域F之后,将硅***物240按压在第一密封树脂14上。结果,在硅***物240的主表面上提供的表面凸块电极241以及在布线主板衬底93上提供的布线凸块12结合在一起。以此方式,在布线主板衬底93的表面上倒装芯片连接硅***物240。此外,布线主板衬底93和硅***物240之间的空间由第一密封树脂14填充。
硅***物240是通过在硅衬底上形成再布线层而制成的衬底。在硅***物240的表面上形成的多个表面凸块电极241以及在背表面上形成的多个背表面凸块电极242经由对应的贯穿电极243电连接在一起。
随后,如图21中所示,在硅***物240上倒装芯片连接作为逻辑芯片的第三半导体芯片230和具有底部填料的芯片层叠体220。
通过将液态第三密封树脂16供应至在硅***物240的背表面上应安装第三半导体芯片230的区域以及具有底部填料的芯片层叠体220应安装的区域来执行上述工艺,且随后将第三半导体芯片230和具有底部填料的芯片层叠体220按压在第三密封树脂16上。结果,第三半导体芯片230和具有底部填料的芯片层叠体220倒装芯片连接至硅***物240的背表面。
随后,如图22中所示,在布线主板衬底93由第二密封树脂15覆盖之后,如图23中所示安装作为焊球的外部连接端子17。随后,如图24中所示,在线主板衬底93由切割带99支撑的情况下,采用切割刀片89沿切割线G进行切削,由此将多个半导体器件300变成单独的片。
显然,本发明不限于上述实施例,而是在不脱离本发明的范围和精神的情况下可进行改进和改变。
例如,第一和第二实施例中描述的是由一个接口半导体芯片和多个(或更具体地,四个)存储半导体芯片构成芯片层叠体33的示例。第三和第四实施例中描述的是由多个(或更具体地,四个)存储半导体芯片构成芯片层叠体210的示例。但是,只要芯片层叠体33或210由经由贯穿电极54电连接多个半导体芯片制成,则构成芯片层叠体33或210的半导体芯片的类型不限于第一至第四实施例中描述的半导体芯片的类型。
第一和第二实施例中描述的是堆叠五个半导体芯片(第一和第二半导体芯片35至39)以形成芯片层叠体33的示例。但是构成芯片层叠体33的半导体芯片的数量(或堆叠芯片的数量)不限于五个。例如,对于第三和第四实施例来说,可堆叠四个半导体芯片以形成芯片层叠体210。
Claims (22)
1.一种制造半导体器件的方法,包括:
堆叠多个半导体芯片以形成第一芯片层叠体;
提供底部填料以填充所述半导体芯片之间的间隙,使得在所述第一芯片层叠体周围形成填角部分;以及
修整所述填角部分以形成第二芯片层叠体。
2.根据权利要求1所述的制造半导体器件的方法,其中,执行所述修整使得所述第二芯片层叠体具有基本上平行于所述半导体芯片中的每一个的侧表面的修整表面。
3.根据权利要求1所述的制造半导体器件的方法,其中
所述半导体芯片中的每一个都具有矩形形状,由此所述填角部分形成在所述第一芯片层叠体的四个侧壁中的每一个上,以及
执行所述修整使得形成在所述四个侧壁上的所述填角部分中的每一个都被修整。
4.根据权利要求1所述的制造半导体器件的方法,其中,通过切割或抛光来执行所述修整。
5.根据权利要求1至4中的任一项所述的制造半导体器件的方法,还包括将所述第二芯片层叠体倒装芯片安装在布线衬底上。
6.根据权利要求1至4中的任一项所述的制造半导体器件的方法,还包括:
将另一半导体芯片倒装芯片安装在布线衬底上,使得所述布线衬底的主表面面对所述另一半导体芯片的一个表面;以及
将所述第二芯片层叠体倒装芯片安装在所述另一半导体芯片的另一表面上。
7.根据权利要求1至4中的任一项所述的制造半导体器件的方法,还包括:
将另一半导体芯片倒装芯片安装在布线衬底的主表面的第一区域上;以及
将所述第二芯片层叠体倒装芯片安装在与所述布线衬底的所述主表面的所述第一区域不同的第二区域上。
8.根据权利要求7所述的制造半导体器件的方法,还包括在所述布线衬底的所述主表面以及所述另一半导体芯片和所述第二芯片层叠体之间提供硅***物。
9.根据权利要求1至4中的任一项所述的制造半导体器件的方法,其中
所述多个半导体芯片包括第一半导体芯片和多个第二半导体芯片,
所述第一半导体芯片包括第一芯片本体,所述第一芯片本体具有作为基本平坦面的一个表面和其上提供有第一凸块电极的另一表面,
所述第二半导体芯片中的每一个都包括第二芯片本体、贯穿所述第二芯片本体的贯穿电极以及在所述贯穿电极的两端提供的第二凸块电极,并且
通过将所述第一半导体芯片安装到结合工具的载物台上使得所述第一芯片本体的所述一个表面面对所述载物台,并且随后将所述第二半导体芯片顺序安装在所述第一半导体芯片上使得所述第一凸块电极、所述第二凸块电极和所述贯穿电极彼此电连接,来执行所述堆叠。
10.根据权利要求9所述的制造半导体器件的方法,其中,所述提供所述底部填料包括:
放置所述第一芯片层叠体使得所述第一芯片本体的所述一个表面面对附接到载物台的平坦面的片材;
将液态的所述底部填料分布至所述第一芯片层叠体的侧壁以借助毛细现象密封所述半导体芯片之间的间隙;以及
固化所述底部填料以使其从液态转变为固态。
11.根据权利要求9所述的制造半导体器件的方法,其中,在所述堆叠中最后堆叠的所述第二半导体芯片中的一个是接口芯片,并且其他所述第二半导体芯片和所述第一半导体芯片是存储芯片。
12.根据权利要求9所述的制造半导体器件的方法,还包括将所述第二芯片层叠体倒装芯片安装在具有连接盘的布线衬底上。
13.根据权利要求12所述的制造半导体器件的方法,其中,执行所述倒装芯片安装使得从所述底部填料中暴露出的所述第二凸块电极和所述布线衬底的所述连接盘彼此结合。
14.根据权利要求12所述的制造半导体器件的方法,还包括形成第一密封树脂以密封所述第二芯片层叠体和所述布线衬底之间的空间。
15.根据权利要求14所述的制造半导体器件的方法,还包括形成第二密封树脂以密封所述布线衬底的主表面上的所述第一密封树脂和所述第二芯片层叠体。
16.根据权利要求15所述的制造半导体器件的方法,还包括形成电连接至所述布线衬底的背表面上的所述连接盘的外部连接盘。
17.根据权利要求1至4中的任一项所述的制造半导体器件的方法,还包括:
制备逻辑半导体芯片,所述逻辑半导体芯片具有作为基本平坦面的一个表面以及其上提供有第三和第四凸块电极的另一表面;
将所述逻辑半导体芯片安装在其主表面上具有连接盘的布线衬底上,使得所述逻辑半导体芯片的所述一个表面面对所述布线衬底的所述主表面;
将所述第二芯片层叠体倒装芯片安装在所述逻辑半导体芯片的所述另一表面上,使得所述第三凸块电极电连接到所述第二芯片层叠体;以及
将所述第四凸块电极通过引线接合连接至所述连接盘。
18.根据权利要求17所述的制造半导体器件的方法,还包括形成第一密封树脂以密封所述第二芯片层叠体和所述逻辑半导体芯片之间的空间。
19.根据权利要求18所述的制造半导体器件的方法,还包括形成第二密封树脂以密封所述布线衬底的所述主表面上的所述逻辑半导体芯片、所述第二芯片层叠体、以及所述第一密封树脂。
20.根据权利要求17所述的制造半导体器件的方法,还包括形成电连接至所述布线衬底的背表面上的所述连接盘的外部连接盘。
21.一种制造半导体器件的方法,包括:
堆叠多个半导体芯片以在所述半导体芯片中的相邻半导体芯片之间形成间隙;
将密封树脂提供至所述半导体芯片中的相邻半导体芯片之间的间隙,使得所述密封树脂的一部分从所述半导体芯片中的至少一个半导体芯片的侧表面突出;以及
修整所述密封树脂的所述突出部分以形成平坦表面。
22.根据权利要求21所述的制造半导体器件的方法,其中,所述平坦表面平行于所述半导体芯片中的至少一个半导体芯片的所述侧表面。
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- 2012-11-28 KR KR1020120136383A patent/KR20130059305A/ko not_active Application Discontinuation
- 2012-11-28 CN CN2012104955991A patent/CN103137500A/zh active Pending
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CN104425464A (zh) * | 2013-09-09 | 2015-03-18 | 株式会社东芝 | 半导体装置 |
CN106415826A (zh) * | 2014-06-26 | 2017-02-15 | 索尼公司 | 半导体器件和制造半导体器件的方法 |
US10867973B2 (en) | 2016-09-16 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of forming the same |
CN107833864A (zh) * | 2016-09-16 | 2018-03-23 | 台湾积体电路制造股份有限公司 | 封装结构及其形成方法 |
US11990454B2 (en) | 2016-09-16 | 2024-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of forming the same |
CN107833864B (zh) * | 2016-09-16 | 2020-03-31 | 台湾积体电路制造股份有限公司 | 封装结构及其形成方法 |
CN108695263A (zh) * | 2017-04-03 | 2018-10-23 | 爱思开海力士有限公司 | 半导体封装及其制造方法 |
CN110021557A (zh) * | 2017-12-01 | 2019-07-16 | 美光科技公司 | 半导体装置封装及相关方法 |
CN110021557B (zh) * | 2017-12-01 | 2024-03-12 | 美光科技公司 | 半导体装置封装及相关方法 |
CN110047764B (zh) * | 2019-04-01 | 2021-07-30 | 京微齐力(北京)科技有限公司 | 一种集成fpga芯片和人工智能芯片的***级封装方法 |
CN110047764A (zh) * | 2019-04-01 | 2019-07-23 | 京微齐力(北京)科技有限公司 | 一种集成fpga芯片和人工智能芯片的***级封装方法 |
CN112447535A (zh) * | 2019-08-28 | 2021-03-05 | 美光科技公司 | 用于堆叠式微电子装置的集成群接合和包封的方法和设备 |
CN112447535B (zh) * | 2019-08-28 | 2022-03-01 | 美光科技公司 | 用于堆叠式微电子装置的集成群接合和包封的方法和设备 |
CN111095548A (zh) * | 2019-09-30 | 2020-05-01 | 深圳市汇顶科技股份有限公司 | 封装结构及其形成方法、封装方法 |
WO2021062674A1 (zh) * | 2019-09-30 | 2021-04-08 | 深圳市汇顶科技股份有限公司 | 封装结构及其形成方法、封装方法 |
WO2023050093A1 (zh) * | 2021-09-28 | 2023-04-06 | 华为技术有限公司 | 芯片封装结构及其封装方法、通信装置 |
Also Published As
Publication number | Publication date |
---|---|
US20130137216A1 (en) | 2013-05-30 |
KR20140130395A (ko) | 2014-11-10 |
JP2013138177A (ja) | 2013-07-11 |
TW201336039A (zh) | 2013-09-01 |
US20140295620A1 (en) | 2014-10-02 |
KR20130059305A (ko) | 2013-06-05 |
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