CN110544723B - 具有部分碳化硅材料/硅材料异质结的u-mosfet及其制作方法 - Google Patents
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Abstract
本发明提出了一种具有部分碳化硅材料/硅材料异质结的U‑MOSFET及其制作方法，该U‑MOSFET器件主要特点是将碳化硅材料与硅材料相结合形成异质结，以碳化硅衬底和N型碳化硅外延层整体的凸字型结构表面为基础形成N型硅外延层，并刻蚀N型硅外延层中间区域深入N型碳化硅外延层顶部，形成槽栅结构。利用碳化硅材料的高临界击穿电场特性，通过击穿点转移技术，将器件槽栅拐角处栅氧的强电场引入碳化硅材料中，抬高了器件的纵向电场峰，器件可承担更高的击穿电压，突破了传统硅基U‑MOSFET器件受单一硅材料临界击穿电场的限制，同时碳化硅材料的高热导率特性有利于器件散热，提高了器件可靠性，有效改善了器件性能。
Description
技术领域
本发明涉及功率半导体器件领域，尤其涉及一种U-MOSFET结构及其制作方法。
背景技术
半导体功率器件是指主要用于电力设备的电能变换和控制电路方面的大功率电子器件。随着半导体功率技术的快速发展，功率半导体器件已经广泛应用于现代工业控制和国防装备中。在20世纪80年代后期，由于刻槽技术的发展，功率半导体界开始采用该工艺技术开发U-MOSFET结构。与VD-MOSFET结构相比，U-MOSFET结构同样具备开关速度快、损耗小、输入阻抗高、驱动功率小、频率特性好、跨导高线性度高等特性，由于U-MOSFET结构没有JFET区，其内部电阻明显降低。
发明内容
本发明提出了一种具有部分碳化硅材料/硅材料异质结的U-MOSFET及其制作方法，旨在进一步提高U-MOSFET的击穿电压，改善器件性能。
本发明的技术方案如下：
具有部分碳化硅材料/硅材料异质结的U-MOSFET，包括：
N+型衬底；
位于N+型衬底上表面的N型外延层；
在N型外延层上部左、右两端区域分别形成的P型基区；P型基区中形成沟道以及N+型源区和P+沟道衬底接触；
源极，覆盖P+沟道衬底接触与N+型源区相接区域的上表面；两处源极共接；
漏极，位于所述N+型衬底下表面；
其特殊之处在于：
所述N+型衬底采用碳化硅材料；
所述N型外延层由两部分构成：一部分为凹字型结构的N型碳化硅外延层，位于所述N+型衬底上表面中间区域；另一部分为两处N型硅外延层，分别位于所述N+型衬底上表面左、右两端区域，相应与所述N型碳化硅外延层的侧面邻接；两处P型基区相应形成于两处N型硅外延层的上部；
所述N型硅外延层的厚度大于N型碳化硅外延层的厚度，整体构成凹槽结构，该凹槽以所述凹字型结构的凹部为底，凹槽深度大于P型基区与N型硅外延层之间PN结的深度，所述凹槽内填充形成栅极，在栅极与凹槽内壁之间设置有栅氧化层；栅极的上表面覆盖有钝化层；
所述N型碳化硅外延层和N型硅外延层的厚度和掺杂浓度由器件的耐压要求决定，其中，N型碳化硅外延层和N型硅外延层的掺杂浓度低于N+型衬底的掺杂浓度。
基于以上方案，本发明还进一步作了如下优化：
两处源极通过覆盖于钝化层上表面的同材料金属(即与源级材料相同的金属)连成一体。
所述凹字型结构是通过部分刻蚀形成的，N型外延层左右两边刻蚀延伸到N+型衬底上表面，中间部分刻蚀深入到N型碳化硅外延层内，N型碳化硅外延层顶部的刻蚀深度Ln为0.5μm～2μm。
N型硅外延层是通过异质外延技术或键合技术在N+型衬底和N型碳化硅外延层上表面形成的；所述P型基区及其N+型源区和P+沟道衬底接触，是在N型硅外延层上部采用离子注入技术形成的。
N型硅外延层和N型碳化硅外延层的掺杂浓度比N+型衬底的掺杂浓度小4-6个数量级。
N型硅外延层的掺杂浓度为1×1015～3×1015cm-3，N型碳化硅外延层的掺杂浓度为3×1015～6×1015cm-3。
所述凹槽底部与所述PN结之间的高度差Lm为2μm～4μm。
所述凹槽侧面到N型碳化硅外延层侧面的距离Wn为0.5μm～2μm。
栅极为多晶硅栅极，源极为金属化源极，漏极为金属化漏极。
本发明技术方案的有益效果如下：
本发明将碳化硅材料与硅材料相结合，采用碳化硅材料作U-MOSFET的衬底，在碳化硅材料N+型衬底上外延生长形成掺杂浓度较低的N型碳化硅材料外延层，对N型碳化硅材料外延层进行部分刻蚀形成凸字型结构，再以该N型碳化硅外延层为基础异质外延生长(或利用键合技术形成)N型硅材料外延层，采用硅成熟工艺形成U-MOSFET器件的有源区。利用碳化硅材料的高临界击穿电场特性，通过击穿点转移，将器件槽栅拐角处栅氧的强电场引入碳化硅材料中，抬高了器件的纵向电场峰，U-MOSFET器件可承担更高的击穿电压，突破了传统硅基U-MOSFET器件受单一硅材料临界击穿电场的限制，同时碳化硅材料的高热导率特性有利于器件散热，提高了器件可靠性，有效改善了器件性能。
附图说明
图1是本发明的结构示意图。
其中，1-N+型源区；2-P+沟道衬底接触(P+型体区)；3-栅极；4-钝化层；5-源极；6-栅氧化层；7-P型基区；8-N型碳化硅外延层；9-N型硅外延层；10-N+型衬底；11-漏极。
具体实施方式
下面结合附图以N沟道U-MOSFET为例介绍本发明。
如图1所示，本实施例包括：
碳化硅材料的N+型衬底10；
位于N+型衬底10上表面中间区域的N型碳化硅外延层8，N型碳化硅外延层的厚度和浓度根据不同的耐压等级设定；
在N+型衬底10和N型碳化硅外延层8上表面异质外延生长或利用键合技术形成的N型硅外延层9，N型硅外延层的厚度和浓度根据不同的耐压等级设定；
分别在N型硅外延层9上部的左、右两端区域形成的两处P型基区7；每一处P型基区7中形成沟道以及N+型源区2和P+沟道衬底接触1；在所述N型硅外延层位于两处N+型源区2之间的区域刻蚀凹槽至N型硅外延层9中，同时满足凹槽深度大于P型基区7与N型硅外延层9之间PN结的深度，凹槽延伸到N型碳化硅外延层8中，凹槽的深度根据不同的耐压等级设定，在凹槽内壁淀积有栅氧化层6；
栅极3设置于栅氧化层6的内壁；栅极3的上表面覆盖有钝化层4；
源极5，覆盖P+沟道衬底接触1与N+型源区2相接区域的上表面；两处源极5共接；
漏极11，位于所述N+型衬底10下表面。
N型硅外延层和N型碳化硅外延层的掺杂浓度比N+型衬底的掺杂浓度小4-6个数量级。N型硅外延层的掺杂浓度为1×1015～3×1015cm-3，N型碳化硅外延层的掺杂浓度为3×1015～6×1015cm-3。
N型碳化硅外延层顶部的刻蚀深度Ln为0.5μm～2μm。凹槽底部与所述PN结之间的高度差Lm为2μm～4μm。凹槽侧面到N型碳化硅外延层侧面的距离Wn为0.5μm～2μm。
以N沟道U-MOSFET为例，具体可以通过以下步骤进行制备：
1)在碳化硅材料的N+型衬底10的上表面外延形成所述N型碳化硅外延层8；
2)在N+型衬底10下表面形成金属化漏极；
3)采用部分刻蚀技术对N型碳化硅外延层8进行部分刻蚀，刻蚀延伸到N+型衬底10上表面，形成凸字型结构；
4)在N+型衬底10和N型碳化硅外延层8上表面异质外延生长技术(或利用键合技术)形成N型硅外延层9；
5)在N型硅外延层9上部的左、右两端区域采用离子注入技术形成P型基区7以及N+型源区2和P+沟道衬底接触1，并在两处N+型源区2之间的区域刻蚀形成凹槽，满足凹槽深度大于P型基区7与N型硅外延层9之间PN结的深度，凹槽延伸到N型碳化硅外延层8中；在凹槽内壁淀积有栅氧化层6；
6)采用局部氧化技术在凹槽内壁淀积形成栅氧化层6，并淀积多晶硅，然后刻蚀多晶硅以及栅氧化层，形成多晶硅栅极3；
7)在器件表面淀积钝化层4，并在对应于源极的位置刻蚀接触孔；
8)在接触孔内淀积金属并刻蚀形成源极，形成覆盖整个P型基区7以及钝化层4上表面的源级一体结构。
经ISE TCAD仿真表明，该器件较之传统硅基U-MOSFET的性能改善，在两种器件漂移区长度相同，漂移区掺杂浓度相同的情况下，该器件的击穿电压相比于传统硅基U-MOSFET提高了2-3倍。例如，U-MOSFET的漂移区长度为11μm时，击穿电压突破300V。
本发明中的U-MOSFET也可以为P型沟道，其结构与N沟道U-MOSFET等同，也将其视为属于本申请权利要求的保护范围，在此不再赘述。
本发明的U-MOSFET中，8与9可以同型，也可以不同型，即：8为N型碳化硅外延层，9也可以为P型硅外延层；也可以8为P型碳化硅外延层，9为N型硅外延层；也可以8为P型碳化硅外延层，9为P型硅外延层。其结构仍是U-MOSFET器件，与本发明等同，也应将其视为属于本申请权利要求的保护范围，在此不再赘述。
Claims (10)
1.一种具有部分碳化硅材料/硅材料异质结的U-MOSFET，包括：
N+型衬底(10)；
位于N+型衬底(10)上表面的N型外延层；
在N型外延层上部左、右两端区域分别形成的P型基区(7)；P型基区(7)中形成沟道以及N+型源区(2)和P+沟道衬底接触(1)；
源极(5)，覆盖P+沟道衬底接触(1)与N+型源区(2)相接区域的上表面；两处源极(5)共接；
漏极(11)，位于所述N+型衬底(10)下表面；
其特征在于：
所述N+型衬底(10)采用碳化硅材料；
所述N型外延层由两部分构成：一部分为凹字型结构的N型碳化硅外延层(8)，位于所述N+型衬底(10)上表面中间区域；另一部分为两处N型硅外延层(9)，分别位于所述N+型衬底(10)上表面左、右两端区域，相应与所述N型碳化硅外延层(8)的侧面邻接；两处P型基区(7)相应形成于两处N型硅外延层(9)的上部；
所述N型硅外延层(9)的厚度大于N型碳化硅外延层(8)的厚度，整体构成凹槽结构，该凹槽以所述凹字型结构的凹部为底，凹槽深度大于P型基区(7)与N型硅外延层(9)之间PN结的深度，所述凹槽内填充形成栅极(3)，在栅极(3)与凹槽内壁之间设置有栅氧化层(6)；栅极(3)的上表面覆盖有钝化层(4)；
所述N型碳化硅外延层(8)和N型硅外延层(9)的厚度和掺杂浓度由器件的耐压要求决定，其中，N型碳化硅外延层(8)和N型硅外延层(9)的掺杂浓度低于N+型衬底(10)的掺杂浓度。
2.根据权利要求1所述的具有部分碳化硅材料/硅材料异质结的U-MOSFET，其特征在于：两处源极(5)通过覆盖于钝化层(4)上表面的同材料金属连成一体。
3.根据权利要求1所述的具有部分碳化硅材料/硅材料异质结的U-MOSFET，其特征在于：所述凹字型结构是通过部分刻蚀形成的，N型外延层左右两边刻蚀延伸到N+型衬底(10)上表面，中间部分刻蚀深入到N型碳化硅外延层(8)内，N型碳化硅外延层(8)顶部的刻蚀深度Ln为0.5μm～2μm。
4.根据权利要求1所述的具有部分碳化硅材料/硅材料异质结的U-MOSFET，其特征在于：所述N型硅外延层(9)是通过异质外延技术或键合技术在N+型衬底(10)和N型碳化硅外延层(8)上表面形成的；所述P型基区(7)及其N+型源区(2)和P+沟道衬底接触(1)，是在N型硅外延层(9)上部采用离子注入技术形成的。
5.根据权利要求1所述的具有部分碳化硅材料/硅材料异质结的U-MOSFET，其特征在于：所述N型硅外延层(9)和N型碳化硅外延层(8)的掺杂浓度比N+型衬底(10)的掺杂浓度小4-6个数量级。
6.根据权利要求1所述的具有部分碳化硅材料/硅材料异质结的U-MOSFET，其特征在于：所述N型硅外延层(9)的掺杂浓度为1×1015～3×1015cm-3，N型碳化硅外延层(8)的掺杂浓度为3×1015～6×1015cm-3。
7.根据权利要求1所述的具有部分碳化硅材料/硅材料异质结的U-MOSFET，其特征在于：所述凹槽底部与所述PN结之间的高度差Lm为2μm～4μm。
8.根据权利要求1所述的具有部分碳化硅材料/硅材料异质结的U-MOSFET，其特征在于：所述凹槽侧面到N型碳化硅外延层(8)侧面的距离Wn为0.5μm～2μm。
9.根据权利要求1所述的具有部分碳化硅材料/硅材料异质结的U-MOSFET，其特征在于：所述栅极(3)为多晶硅栅极，所述源极(5)为金属化源极，漏极(11)为金属化漏极。
10.一种制作权利要求1所述的具有部分碳化硅材料/硅材料异质结的U-MOSFET的方法，包括以下步骤：
1)在碳化硅的N+型衬底(10)的上表面外延形成N型碳化硅外延层(8)；
2)在N+型衬底(10)下表面形成金属化漏极(11)；
3)采用部分刻蚀技术对N型碳化硅外延层(8)进行部分刻蚀，左右两边刻蚀延伸到N+型衬底(10)上表面；
4)在N+型衬底(10)和N型碳化硅外延层(8)上表面异质外延生长或利用键合技术形成N型硅外延层(9)；
5)在N型硅外延层(9)上部的左、右两端区域采用离子注入技术形成P型基区(7)以及N+型源区(2)和P+沟道衬底接触(1)，并在两处N+型源区(2)之间的区域刻蚀形成凹槽，凹槽延伸到N型碳化硅外延层(8)中，满足凹槽深度大于P型基区(7)与N型硅外延层(9)之间PN结的深度，凹槽底部深入N型碳化硅外延层(8)内部，凹槽的宽度小于N型碳化硅外延层(8)的宽度，在凹槽内壁淀积栅氧化层(6)；
6)采用局部氧化技术在凹槽内壁淀积形成栅氧化层(6)，并淀积多晶硅，然后刻蚀多晶硅以及栅氧化层，形成多晶硅栅极(3)；
7)在器件表面淀积钝化层(4)，并在对应于源极的位置刻蚀接触孔；
8)在接触孔内淀积金属并刻蚀形成源极，形成覆盖整个P型基区(7)以及钝化层(4)上表面的源极一体结构。
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