CN103021888B - 用于制造包括高可靠性晶粒底填充的集成电路***的方法 - Google Patents

用于制造包括高可靠性晶粒底填充的集成电路***的方法 Download PDF

Info

Publication number
CN103021888B
CN103021888B CN201210356840.2A CN201210356840A CN103021888B CN 103021888 B CN103021888 B CN 103021888B CN 201210356840 A CN201210356840 A CN 201210356840A CN 103021888 B CN103021888 B CN 103021888B
Authority
CN
China
Prior art keywords
integrated circuit
stripping
semiconductor substrate
adhesive tape
slicing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201210356840.2A
Other languages
English (en)
Other versions
CN103021888A (zh
Inventor
任明镇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries US Inc
Original Assignee
GlobalFoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries Inc filed Critical GlobalFoundries Inc
Publication of CN103021888A publication Critical patent/CN103021888A/zh
Application granted granted Critical
Publication of CN103021888B publication Critical patent/CN103021888B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2733—Manufacturing methods by local deposition of the material of the layer connector in solid form
    • H01L2224/27334—Manufacturing methods by local deposition of the material of the layer connector in solid form using preformed layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提供一种用于制造包括高可靠性晶粒底填充的集成电路***的方法，该方法用于制造集成电路***，其包括在半导体衬底中和上制造多个集成电路。附接间隔开来的焊料凸点到多个集成电路，焊料凸点电接触集成电路的组件。提供切块胶带，于其上具有底填充材料层，并层压半导体衬底到切块胶带，其中底填充材料层填补焊料凸点间的空间。切块半导体衬底和底填充材料层以单切多个集成电路的个别集成电路，并附接多个集成电路的个别集成电路之一到如另一个集成电路芯片或印刷电路板的第二衬底。

Description

用于制造包括高可靠性晶粒底填充的集成电路***的方法
技术领域
本发明一般涉及用于制造集成电路***的方法，尤其涉及用于制造具有高可靠性底填充(under-fill)的集成电路***的方法。
背景技术
集成电路***往往包括以堆迭关系附接到其它集成电路（IC）、插板或印刷电路板的集成电路(IC)。IC***可以包括，例如，互连的微处理器电路、存储器电路、模拟电路、等等，以利用个别电路的独特属性。通过垂直堆迭***组件，可以最小化***的大小或覆盖面积(footprint)。
集成电路***包括至少一个IC晶粒(die)，其通过回流焊料凸点(solder bump)而粘合到另一个衬底，以同时提供晶粒与衬底间的物理附接和晶粒与衬底上的金属垫间的电接触。晶粒与衬底间的空间必须以底填充材料填充以保护IC的表面并隔绝污染物。在先进的技术中，因为所涉及的复杂拓扑(topology)、焊料凸点间的精细间距、和连接的结构间的窄缝的缘故，很难妥善填充晶粒和衬底间的空间。
因此，希望提供用于制造包括可靠底填充工艺的集成电路***的方法。此外，希望提供用于制造IC***的方法，该***与临时粘合/脱粘、晶片级底填充、和IC芯片切块(dicing)和单切（singulation）兼容。此外，自随后的详细说明和所附的权利要求书，结合附图、上述技术领域和背景技术，本发明的其它可取的特点和特征将变得明显。
发明内容
提供一种用于制造集成电路***的方法。根据一个实施例，所述方法包括在半导体衬底中和上制造多个集成电路。附接间隔开来的焊料凸点到所述多个集成电路，所述焊料凸点电接触所述集成电路的组件。提供切块胶带(dicing tape)，于其上具有底填充材料层，并层压(laminate)所述半导体衬底到所述切块胶带，其中，所述底填充材料层填补所述焊料凸点间的空间。切块所述半导体衬底和所述底填充材料层以单切所述多个集成电路的个别集成电路，并附接所述多个集成电路的所述个别集成电路之一到如另一个集成电路芯片或印刷电路板的第二衬底。
根据另一个实施例，所述方法包括在半导体衬底中和上制造集成电路。制造集成电路包括蚀刻通孔开口(via opening)到所述半导体衬底的前表面中并以导电材料填充所述通孔开口来形成穿过衬底通孔(through substrate vias，TSV)。粘合所述半导体衬底的所述前表面到载体晶片，并抛光所述半导体衬底的背侧以暴露出所述导电材料的一部分。在与所述导电材料电接触的所述背侧上形成多个焊料凸点。提供切块胶带，于其上具有底填充材料层，且层压所述半导体衬底的所述背侧到所述切块胶带。自所述载体晶片脱粘所述半导体衬底，并将所述半导体衬底和所述底填充材料层切块成个别的集成电路芯片。接着在第二衬底上组装(assemble)所述个别的集成电路芯片和底填充材料。
根据又另一个实施例，所述方法包括在半导体衬底中和上制造多个集成电路，所述集成电路的每一个集成电路包括自前表面朝背表面延伸的多个金属填充通孔和在所述前表面上的多个焊料凸点，每一个与所述多个金属填充通孔之一电接触。粘合所述前表面到载体晶片，并抛光所述背表面以薄化所述半导体衬底并暴露出所述多个金属填充通孔的一部分。在与所述多个金属填充通孔的暴露部分电接触的所述背表面上形成重新分布层(redistribution layer，RDL)，并形成与所述重新分布层电接触的多个背侧焊料凸点。提供切块胶带，于其上具有底填充材料层，并层压所述半导体衬底的所述背表面到所述切块胶带，所述底填充材料填补在背侧焊料凸点间的空间。去除所述载体晶片并切块所述半导体衬底和所述底填充材料层以将所述衬底分成多个个别的集成电路。附接所述多个个别的集成电路之一到第二衬底并加热以导致所述多个背侧焊料凸点流动并粘接到所述第二衬底上的金属垫。
附图说明
此后将结合附图说明本发明，其中相似参考号码是相似的组件，且其中：
图1-图10为根据各种实施例概略绘示用于制造集成电路***的方法步骤的简化截面图；以及
图11-图12为根据替代实施例概略绘示用于制造集成电路***的方法步骤的简化截面图。
具体实施方式
下面的详细描述本质上仅仅是示范，且并无意限制本发明或本发明的应用和用途。此外，本发明必无意受限于在上述技术领域、背景技术、发明内容或以下的详细说明中所提出的任何明确或隐含的理论。
图1-图10为根据各种实施例概略绘示用于制造集成电路***的方法步骤的简化截面图。作为本文所用，“集成电路***”是指粘合到衬底的至少一个集成电路（IC）芯片或晶粒，该衬底可以是另一个芯片、插层或印刷电路板。虽然没有说明，IC***可以包括多个IC芯片，也许是不同类型的，如微处理器、存储器、模拟或类似，其堆积在一起而形成三维***。IC和IC***的制造中的各个步骤都是本领域中的技术人员所熟知，所以为了简洁，将仅在本文简要地提及许多传统的步骤，或将完全省略而不提供众所周知的工艺细节。
如图1所示，根据一个实施的方法开始于在半导体衬底50中和上制造多个集成电路。在此简化截面图中，由单虚线区52简单表示多个集成电路。如众所周知，集成电路一般是长方形的形式且以规律的阵列设置在半导体衬底上，由切割格(scribe grid)将每个IC与下一个分离。作为用于制造IC芯片堆迭阵列的方法的一部分，蚀刻多个间隔开来的通孔开口54到半导体衬底的前表面56中。通孔开口可以有，例如，30-100微米（μm）的深度。以如铜的导电材料58填充通孔开口。填充金属或其它导电材料的通孔开口会形成穿过衬底通孔（TSV），其提供用于互连多个芯片和相关衬底的有效手段。可在IC制造中的不同时期形成填充通孔，但在沉积和图案化第一层金属后形成最方便。虽然没有说明，IC制造以正常的方式继续多层金属、层间介质和之类的形成。多个间隔开来的焊料凸点60是附接到IC的前表面，其至少一些是与填充通孔中的导电材料电接触并与IC的组件电接触。
根据一个实施例，如图2所示该方法接着粘合半导体衬底的前表面到载体晶片62。半导体衬底50和载体晶片62通过粘胶层(adhesivelayer)64粘合在一起。载体晶片作为当抛光（例如通过化学机械抛光（Chemical Mechanical Polishing，CMP））半导体衬底的背表面66到如图3所示的薄化衬底时的支撑。在抛光期间，去除由虚线68所示的半导体衬底50的部分来暴露出在通孔开口54中的导电材料58的一部分，从而完成了TSV的形成。本领域中的技术人员将会认知到薄化的半导体衬底将仅有50-75微米(μm)的厚度，与通孔开口的深度一致，且正是因为此薄度而需使用到载体晶片62。
根据一个实施例，继续半导体衬底50的现已薄化的背表面的处理，如图4所示。清洗背表面66，且虽然没有在这个横断面图中显示，如果对正在实施的IC***来说有必要的话，可以施加金属化重新分布层（RDL）于该表面。RDL，如果使用的话，电接触TSV的至少一些。间隔开来的背侧焊料凸点72是附接到衬底的背表面而与RDL和/或TSV电接触。
如图5所示，提供切块胶带74，最好是拉伸于切块带架76上方。如众所周知，切块胶带典型是高分子材料，其用于在将半导体衬底分成个别的IC芯片或晶粒的切块操作期间和之后将半导体衬底的块保持在一起。施加一底填充材料层78到切块胶带的表面。与目前披露的方法相比之下，在传统加工中，仅在芯片已经附接到衬底后才通过毛细管底填充工艺来施加底填充材料。底填充材料，正如本领域的技术人员所熟知的，是电气绝缘材料，用来提供IC芯片与IC芯片将如下所解释般粘合至其的衬底间的坚固的机械连接。底填充材料也隔绝了污染物并在芯片与衬底间形成热桥。底填充材料78，最好有等于或大于由箭头80所示的间隔开来的背侧焊料凸点的高度的厚度。底填充材料通常是高分子材料，且只有部分固化，使其在这个处理阶段仍然是塑料。也可在切块胶带和底填充材料层间包括紫外线（Ultra Violet，UV）释放层(release layer)82。
根据一个实施例，该方法接着层压半导体衬底50的背表面66到切块胶带74和底填充材料层78，如图6中所示。部分固化的底填充材料包围并填补背侧焊料凸点72间的空间。以和传统上在无底填充材料层的情况下会进行的同样的方式来完成层压。
如图7所示，一旦半导体衬底50层压到切块胶带74和底填充材料层78，半导体衬底可自载体晶片62脱粘，因为现在由切块胶带和切块胶带架支撑薄化的衬底。在去除载体晶片62后，自半导体衬底的前表面去除粘胶层64（由箭头65表示后续的粘胶去除）并彻底清洗表面。
在清洗半导体衬底50的表面后，可将衬底切块成个别的集成电路芯片或晶粒90，如图8所示。可通过割锯、划片或沿个别IC芯片间的划线（如虚线92所示）激光切割来切块半导体衬底。切块操作切穿半导体衬底、底填充材料层78并到切块胶带74。虽然在简化截面图只在半导体衬底的前面上显示两个焊料凸点60且只在背侧上显示两个背侧焊料凸点72，在实际操作中，可视实施设计的集成电路的需要使用任何数量的焊料凸点，通常是数百个，无论是前侧或背侧。
如图9中所示，该方法接着自切块胶带单切并去除如IC芯片94的个别集成电路芯片。可例如通过机器人控制的拾取和放置设备去除个别的芯片。如果已纳入紫外线释放层82到底填充材料层下方的结构，可通过最好自背侧以UV辐射辐照切块胶带，而自切块胶带释放个别的IC芯片来加以去除。UV辐射使底填充材料自切块胶带释放。在自切块胶带释放后，IC芯片94包括具有焊料凸点在表面上的完成集成电路，焊料凸点72封闭在部分固化的底填充材料78中。
IC芯片94是附接到另一个衬底96-1或96-2（统称衬底96）以完成集成电路***，如图10中所示。衬底96可以是插衬底或印刷电路板96-1，如图10A中所示，或另一个集成电路芯片96-2，如图10B中所示。IC芯片94可以单独使用在IC***中或可以是组装在一起而形成***的多个IC芯片之一。可以附接多个IC芯片到相同的插衬底或印刷电路板和/或多个IC芯片可在三维堆迭中一个迭着一个地堆迭形成IC***。
IC芯片94是通过对准背侧焊料凸点72与如图10A中的衬底96-1上的金属垫98或通过对准焊料凸点72与如图10B中的IC衬底96-2的表面上的金属垫98（未显示）或焊料凸点73而附接到衬底96。焊料凸点是通过加热焊料并导致其流动而电连接到金属垫98或到焊料凸点93。焊料凸点较佳通过热压缩（Thermal-Compression，TC）粘合工艺连接到金属垫或焊料凸点73。在TC粘合工艺中，使焊料流动所需的热量是与压缩力合并。当IC芯片定位在衬底96上方且焊料凸点如由箭头100所表示压对着金属垫或焊料凸点73时，在焊料凸点下方的部分固化的底填充材料会变形，而允许焊料凸点和金属垫或焊料凸点73间的接触。在粘合后，加热底填充材料78以完全固化材料，而在焊料凸点连结周围形成保护层并机械固定IC芯片到衬底。
虽未显示，如上述般制造和组装的多个IC芯片的三维堆迭也可以是倒装芯片式(flip chip)粘合到如印刷电路板的衬底来完成三维IC***。在多个IC芯片之一的前面上的焊料凸点60可以和之前对于背侧焊料凸点所述的相同方式附接到衬底上的导电垫。
层压半导体衬底的背表面到以底填充材料层所覆盖的切块胶带的上述方法也可以应用到倒装芯片式粘合具有焊料凸点的集成电路的前表面到另一个衬底，如图11和图12中所示。在半导体衬底150中和上制造IC 152，包括焊料凸点160到和部分IC电接触的前表面156的附接，如图11中所示。在一些实施例中，集成电路可能还包括自充满导电材料158的通孔开口154所形成的TSV。
半导体衬底的前表面是层压到切块胶带174，其上已设置有底填充材料层178，如图12中所示。根据一个实施例，释放层182是设置在切块胶带和底填充材料层间。半导体衬底，不论经薄化与否，可以是沿划线切块来分开多个IC，如虚线192所示。
在切块后，可以于上相关于图9和图10所述的相同方式自切块胶带单切并去除个别的IC。拾取和放置设备可以自切块胶带去除个别的芯片并将它们定位在印制电路板上的导电粘合垫上方。较佳通过热压缩粘合工艺加热焊料凸点，使焊料流动并连接焊料凸点到导电垫。如上述般固化底填充材料来完成该工艺。
虽然已在上述详细说明中提出至少一个示范实施例，可认知到存在有广大数量的变化。也应该认知到示范实施例仅是例子，不是为了以任何方式限制本发明的范围、适用性或配置。更确切地，上述详细说明将提供在本领域的技术人员实施示范实施例的一个方便导引。应了解到可做出组件功能和排列的各种变化，而不背离在所附的权利要求书中所提出的本发明的范围和其法律等效者。

Claims (20)

1.一种制造集成电路***的方法，包含：
在半导体衬底中和上制造多个集成电路；
附接间隔开来的焊料凸点到所述多个集成电路，所述焊料凸点电接触所述集成电路的组件，其中，所述间隔开来的焊料凸点是位在所述半导体衬底的背表面上；
提供切块胶带，于其上具有底填充材料层；
层压所述半导体衬底到所述切块胶带，其中，所述底填充材料层填补所述焊料凸点间的空间；
切块所述半导体衬底和所述底填充材料层以单切所述多个集成电路的个别集成电路；以及
附接所述多个集成电路的所述个别集成电路之一到第二衬底。
2.根据权利要求1所述的方法，其中，提供切块胶带包含提供切块胶带，于其上具有底填充材料层，所述底填充材料层具有等于或大于所述间隔开来的焊料凸点的高度的厚度。
3.根据权利要求1所述的方法，其中，提供切块胶带包含提供具有在所述底填充材料层下方的紫外线释放层的切块胶带。
4.根据权利要求3所述的方法，其中，在切块所述半导体衬底和所述底填充材料层后，暴露所述切块胶带到紫外线辐射而使所述底填充材料自所述切块胶带释放。
5.根据权利要求1所述的方法，进一步包含，在附接所述多个集成电路的所述个别集成电路之一到第二衬底后，加热所述多个集成电路的一所述集成电路来固化所述底填充材料。
6.根据权利要求1所述的方法，其中，附接所述多个集成电路的所述个别集成电路之一到第二衬底包含附接所述个别集成电路之一到第二集成电路芯片以形成三维集成电路***。
7.根据权利要求1所述的方法，其中，制造多个集成电路进一步包含形成延伸穿过所述半导体衬底并电耦合到所述间隔开来的焊料凸点的穿过衬底通孔。
8.根据权利要求7所述的方法，其中，制造多个集成电路进一步包含：
暂时粘合所述半导体衬底到载体晶片；以及
在附接所述间隔开来的焊料凸点前，薄化所述半导体衬底。
9.根据权利要求8所述的方法，进一步包含在层压所述半导体衬底到所述切块胶带后，自所述载体晶片脱粘所述半导体衬底。
10.一种用于制造集成电路***的方法，包含：
在半导体衬底中和上制造集成电路，包括蚀刻通孔开口到所述半导体衬底的前表面中并以导电材料填充所述通孔开口来形成穿过衬底通孔；
粘合所述半导体衬底的所述前表面到载体晶片；
抛光所述半导体衬底的背侧以暴露出所述导电材料的一部分；
在与所述导电材料电接触的所述背侧上形成多个焊料凸点；
提供切块胶带，于其上具有底填充材料层；
层压所述半导体衬底的所述背侧到所述切块胶带；
自所述载体晶片脱粘所述半导体衬底；
将所述半导体衬底和所述底填充材料层切块成个别的集成电路芯片；以及
在第二衬底上组装所述个别的集成电路芯片和底填充材料。
11.根据权利要求10所述的方法，进一步包含在形成所述多个焊料凸点前，在所述半导体衬底的所述背侧上形成重新分布层，所述重新分布层电耦合于所述导电材料与所述多个焊料凸点间。
12.根据权利要求10所述的方法，其中，提供切块胶带包含提供具有在切块胶带与所述底填充材料层间的紫外线释放层的所述切块胶带。
13.根据权利要求12所述的方法，进一步包含在切块以自所述切块胶带释放所述个别集成电路芯片和所述底填充材料的一部分后，以紫外线辐射辐照所述切块胶带。
14.根据权利要求10所述的方法，其中，在第二衬底上组装所述个别的集成电路芯片和底填充材料包含：
在第二衬底上方定位一个别的集成电路芯片；
加热所述个别的集成电路芯片以导致所述焊料凸点流动并导致到所述第二衬底上的导电垫的电耦合；以及
加热所述底填充材料以固化所述底填充材料。
15.根据权利要求10所述的方法，其中，在第二衬底上组装所述个别的集成电路芯片和底填充材料包含附接一个别的集成电路芯片到第二集成电路芯片而形成三维集成电路***。
16.一种用于制造集成电路***的方法，包含：
在半导体衬底中和上制造多个集成电路，所述集成电路的每一个集成电路包括自前表面朝背表面延伸的多个金属填充通孔和在所述前表面上的多个焊料凸点，每一个与所述多个金属填充通孔之一电接触；
粘合所述前表面到载体晶片；
抛光所述背表面以薄化所述半导体衬底并暴露出所述多个金属填充通孔的一部分；
在与所述多个金属填充通孔的暴露部分电接触的所述背表面上形成重新分布层；
形成与所述重新分布层电接触的多个背侧焊料凸点；
提供切块胶带，于其上具有底填充材料层；
层压所述半导体衬底的所述背表面到所述切块胶带，所述底填充材料填补在所述背侧焊料凸点间的空间；
去除所述载体晶片；
切块所述半导体衬底和所述底填充材料层以将所述多个集成电路分成多个个别的集成电路芯片；以及
附接所述多个个别的集成电路之一到第二衬底并加热以导致所述多个背侧焊料凸点流动并粘接到所述第二衬底上的金属垫。
17.根据权利要求16所述的方法，其中，附接进一步包含加热所述多个个别的集成电路的一所述集成电路和所述底填充材料以固化所述底填充材料。
18.根据权利要求16所述的方法，其中，提供切块胶带包含提供切块胶带，于其上具有底填充材料层，所述底填充材料层具有至少等于所述背侧焊料凸点的高度的厚度。
19.根据权利要求16所述的方法，其中，附接所述多个个别的集成电路之一到第二衬底包含附接所述多个个别的集成电路的一所述集成电路到第二集成电路芯片，所述方法进一步包含倒装芯片式粘合所述前表面上的所述焊料凸点到印刷电路板。
20.根据权利要求16所述的方法，其中，提供切块胶带进一步包含提供具有在切块胶带与所述底填充材料层间的紫外线释放层的所述切块胶带。
CN201210356840.2A 2011-09-23 2012-09-21 用于制造包括高可靠性晶粒底填充的集成电路***的方法 Expired - Fee Related CN103021888B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/243,605 2011-09-23
US13/243,605 US8409927B1 (en) 2011-09-23 2011-09-23 Methods for fabricating integrated circuit systems including high reliability die under-fill

Publications (2)

Publication Number Publication Date
CN103021888A CN103021888A (zh) 2013-04-03
CN103021888B true CN103021888B (zh) 2015-06-03

Family

ID=47911706

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210356840.2A Expired - Fee Related CN103021888B (zh) 2011-09-23 2012-09-21 用于制造包括高可靠性晶粒底填充的集成电路***的方法

Country Status (3)

Country Link
US (1) US8409927B1 (zh)
CN (1) CN103021888B (zh)
TW (1) TWI590398B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130075892A1 (en) * 2011-09-27 2013-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Three Dimensional Integrated Circuit Fabrication
US8785249B2 (en) * 2012-05-23 2014-07-22 The Charles Stark Draper Laboratory, Inc. Three dimensional microelectronic components and fabrication methods for same
US20140103499A1 (en) 2012-10-11 2014-04-17 International Business Machines Corporation Advanced handler wafer bonding and debonding
US9441753B2 (en) * 2013-04-30 2016-09-13 Boston Dynamics Printed circuit board electrorheological fluid valve
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
TW202308015A (zh) * 2016-01-15 2023-02-16 荷蘭商庫力克及索發荷蘭公司 放置超小或超薄之離散組件
JP2018046237A (ja) * 2016-09-16 2018-03-22 株式会社東芝 半導体装置およびその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1993809A (zh) * 2004-08-03 2007-07-04 古河电气工业株式会社 半导体器件制造方法及晶片加工带
TW201101428A (en) * 2009-06-08 2011-01-01 Stats Chippac Ltd Semiconductor device and method of forming an interconnect structure with TSV using encapsulant for structural support
CN102163559A (zh) * 2010-02-18 2011-08-24 台湾积体电路制造股份有限公司 堆叠装置的制造方法及装置晶片处理方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6794751B2 (en) * 2001-06-29 2004-09-21 Intel Corporation Multi-purpose planarizing/back-grind/pre-underfill arrangements for bumped wafers and dies
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
TWI234211B (en) * 2003-12-26 2005-06-11 Advanced Semiconductor Eng Method for forming an underfilling layer on a bumped wafer
US7727875B2 (en) * 2007-06-21 2010-06-01 Stats Chippac, Ltd. Grooving bumped wafer pre-underfill system
KR101493872B1 (ko) * 2008-08-20 2015-02-17 삼성전자주식회사 백그라인딩-언더필 필름, 그 형성방법, 이를 이용한 반도체패키지 및 그 형성방법
US8689437B2 (en) * 2009-06-24 2014-04-08 International Business Machines Corporation Method for forming integrated circuit assembly

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1993809A (zh) * 2004-08-03 2007-07-04 古河电气工业株式会社 半导体器件制造方法及晶片加工带
TW201101428A (en) * 2009-06-08 2011-01-01 Stats Chippac Ltd Semiconductor device and method of forming an interconnect structure with TSV using encapsulant for structural support
CN102163559A (zh) * 2010-02-18 2011-08-24 台湾积体电路制造股份有限公司 堆叠装置的制造方法及装置晶片处理方法

Also Published As

Publication number Publication date
US20130078767A1 (en) 2013-03-28
US8409927B1 (en) 2013-04-02
TWI590398B (zh) 2017-07-01
CN103021888A (zh) 2013-04-03
TW201320264A (zh) 2013-05-16

Similar Documents

Publication Publication Date Title
CN103021888B (zh) 用于制造包括高可靠性晶粒底填充的集成电路***的方法
TWI546915B (zh) 多重中介層基板電路組件以及其製造方法
TWI536519B (zh) 半導體封裝結構以及其製造方法
TWI697959B (zh) 半導體封裝及封裝半導體裝置之方法
US9570429B2 (en) Methods of fabrication and testing of three-dimensional stacked integrated circuit system-in-package
JP5422720B2 (ja) エッジ接続ウエハレベル積層体
US7683459B2 (en) Bonding method for through-silicon-via based 3D wafer stacking
US9257415B2 (en) Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
CN103325703B (zh) 在封装件形成期间探测芯片
TWI517322B (zh) 半導體元件及其製作方法
US20110033979A1 (en) Edge connect wafer level stacking
CN103117279A (zh) 形成芯片在晶圆的总成的方法
TW201611186A (zh) 半導體裝置之製造方法
JP5942823B2 (ja) 電子部品装置の製造方法、電子部品装置及び電子装置
US7723213B2 (en) Manufacturing method of semiconductor chips and semiconductor device having the semiconductor chips
WO2009154761A9 (en) Stacking of wafer-level chip scale packages having edge contacts
TWI628757B (zh) 終極薄扇出型晶片封裝構造及其製造方法
KR20090048597A (ko) 전자 3ｄ 모듈들의 일괄적 제조를 위한 프로세스
US9029199B2 (en) Method for manufacturing semiconductor device
CN103681618A (zh) 具有通孔的功能性玻璃处理晶片
WO2009146587A1 (en) Bongding method for through-silicon-via based 3d wafer stacking
CN106252279A (zh) 半导体结构及其制造方法
US20150179609A1 (en) Method for interconnecting die and substrate in an electronic package
CN112349595A (zh) 芯片封装结构的制作方法
CN105261568A (zh) 中介基板的制法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20210223

Address after: California, USA

Patentee after: Lattice chip (USA) integrated circuit technology Co.,Ltd.

Address before: Greater Cayman Islands, British Cayman Islands

Patentee before: GLOBALFOUNDRIES Inc.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20150603

Termination date: 20210921