CN103117279A - 形成芯片在晶圆的总成的方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims description 27
- 235000012431 wafers Nutrition 0.000 claims description 50
- 239000000758 substrate Substances 0.000 claims description 32
- 239000000206 moulding compound Substances 0.000 claims description 27
- 238000004806 packaging method and process Methods 0.000 claims description 23
- 239000007767 bonding agent Substances 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 230000005611 electricity Effects 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 8
- 239000003989 dielectric material Substances 0.000 claims description 5
- PYRKKGOKRMZEIT-UHFFFAOYSA-N 2-[6-(2-cyclopropylethoxy)-9-(2-hydroxy-2-methylpropyl)-1h-phenanthro[9,10-d]imidazol-2-yl]-5-fluorobenzene-1,3-dicarbonitrile Chemical compound C1=C2C3=CC(CC(C)(O)C)=CC=C3C=3NC(C=4C(=CC(F)=CC=4C#N)C#N)=NC=3C2=CC=C1OCCC1CC1 PYRKKGOKRMZEIT-UHFFFAOYSA-N 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- 238000005452 bending Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 3
- 239000002985 plastic film Substances 0.000 description 3
- 229920006255 plastic film Polymers 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/141—Disposition
- H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
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Abstract
本发明公开了一种器件,该器件包括底部芯片和接合到所述底部芯片的有源顶部管芯。伪管芯附接到所述底部芯片。所述伪管芯与所述底部芯片电隔离。本发明还公开了形成芯片在晶圆的总成的方法。
Description
技术领域
本发明涉及半导体领域,更具体地,本发明涉及一种形成芯片在晶圆的总成的方法。
背景技术
在三维集成电路的形成过程中,管芯通常接合在半导体晶圆上。接合工艺典型地接合包括选择合格的管芯(顶部管芯),并且利用倒装焊接将顶部管芯接合到底部芯片上。底部芯片中的每一个均可以被接合到一个或者多个顶部管芯上。在接合后,将底部填充物分发到顶部管芯和底部芯片之间的间隙内,并且模塑料模制到顶部管芯和底部晶圆上。在模制模塑料后,由于模塑料的收缩,可能导致封装件弯曲。因此,可以产生应力并且将其应用于底部晶圆和覆在上面的顶部管芯。
在底部晶圆中的硅衬底被研磨期间,在背部研磨工艺后,情形变得更糟,并因此显著地减少了底部晶圆的厚度。弯曲相应地更严重。所述弯曲可以导致最终得到的封装件中的层与层之间的粘性差,抗潮性差,防止凸块破裂的能力差等等。结果,可靠性问题很有可能发生,可靠性问题可以在热循环测试,下坠测试,弯曲测试等中验证。
发明内容
为了解决现有技术中所存在的问题,根据本发明的一个方面,提供了一种器件,所述器件包括:
底部芯片;
有源顶部管芯,接合到所述底部芯片;和
伪管芯,附接到所述底部芯片,其中所述伪管芯与所述底部芯片电隔离。
在一些实施例中,所述伪管芯选自基本上由以下组成的组中:在其中没有集成电路的空白管芯,在其中没有低k电介质层、金属线、和通孔的硅管芯,和它们的组合。
在一些实施例中,所述伪管芯设置成不与电源连接。
在一些实施例中,所述有源顶部管芯接合到所述底部芯片并且通过电连接件与所述底部芯片电连接,其中所述伪管芯通过粘接剂粘附到所述底部芯片,并且其中所述伪管芯通过所述粘接剂与所述底部芯片电隔离。
在一些实施例中,所述器件进一步包括在所述有源顶部管芯和所述伪管芯之间的间隙中的模塑料。
在一些实施例中,所述底部芯片是晶圆的一部分,并且没有从所述晶圆切割掉。
在一些实施例中,所述底部芯片进一步包括在所述底部芯片的半导体衬底中的衬底通孔。
根据本发明的另一个方面,提供了一种器件,所述器件包括:
底部芯片,包括:
衬底;
通孔,从所述衬底的第一侧延伸至所述衬底的第二侧;
第一连接件,在所述衬底的所述第一侧上;和
第二连接件,在所述衬底的所述第二侧上,其中所述第一连接件通过所述通孔与所述第二连接件电连接;
有源顶部管芯,在所述衬底的所述第一侧上,所述有源顶部管芯通过所述第一连接件接合到所述底部芯片;
伪管芯,在所述衬底的所述第一侧上;和
管芯附接膜,使所述伪管芯附接到所述底部芯片。
在一些实施例中,所述伪管芯设置成不与任何电源连接。
在一些实施例中,所述管芯附接膜包括介电材料,并且其中没有导电部件穿透所述管芯附接膜。
在一些实施例中,所述器件进一步包括在所述有源顶部管芯和所述伪管芯之间的间隙中的模塑料。
在一些实施例中,所述伪管芯中不包括有源集成电路。
在一些实施例中,所述伪管芯是空白管芯,所述空白管芯中不包括任何集成电路。
在一些实施例中,所述伪管芯是晶圆的一部分,并且没有从所述晶圆切割掉。
根据本发明的又一个方面,提供了一种方法,所述方法包括:
将多个有源顶部管芯接合到底部晶圆,其中所述多个有源顶部管芯的每个均通过电连接件接合到在所述底部晶圆中的多个相同的芯片中的一个;
将多个伪管芯附接到所述多个相同的芯片,其中所述多个伪管芯的每个均通过多个管芯附接膜中的一个附接到多个相同的芯片中的一个,并且其中所述多个伪管芯通过所述多个管芯附接膜与所述多个相同的芯片电隔离;和,
将模塑料填充到所述多个有源顶部管芯和所述多个伪管芯之间的间隙内。
在一些实施例中,所述方法进一步包括:在施加所述模塑料的步骤之前,将伪管芯附接到在所述底部晶圆中的不完整的底部芯片,其中所述模塑料与所述伪管芯物理接触。
在一些实施例中,所述方法进一步包括:在填充所述模塑料的步骤之后,使用粘接剂将载具附接到所述底部晶圆;对在所述底部晶圆中的衬底进行背侧研磨以暴露在所述底部晶圆中的硅通孔;和在所述底部晶圆的背侧上形成背侧互连结构;和切割所述底部晶圆以形成多个封装件,其中所述多个封装件中的每个均包括所述多个有源顶部管芯中的一个和所述多个伪管芯中的一个。
在一些实施例的方法中,没有电连接件将所述多个伪管芯中的任意一个与所述多个相同的芯片中的任意一个电连接。
在一些实施例的方法中,所述多个伪管芯是在其中没有集成电路的空白管芯。
在一些实施例的方法中,所述多个伪管芯是在其中没有低-k电介质层、金属线和通孔的硅管芯。
附图说明
为了更完整地理解本发明实施例及其优点,现将结合附图所进行的以下描述作为参考,其中:
图1到图6是根据各种实施例的在封装件制造的中间阶段的截面图,其中,伪管芯接合到在晶圆上的底部芯片。
图7和图8示出了根据各种可选实施例的在封装件制造的中间阶段的截面图,其中,伪管芯接合到离散的底部芯片。
具体实施方式
下面,详细讨论本发明各实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式,而不用于限制本发明的范围。
根据各种实施例,提供了封装结构和用于形成封装结构的方法。举例说明了形成封装结构的中间阶段。阐述了不同实施例的差别。遍及各个视图和示例的实施例,相同的参考标号用于标识相同的元件。
图1A示出了底部晶圆20的俯视图。在一种实施例中,底部晶圆20是一种器件晶圆,器件晶圆包括半导体衬底38(图1A中未显示,请参考图1B),以及形成在半导体衬底38的表面上的有源器件诸如晶体管(图中未显示)。半导体衬底38可以是硅衬底,或者由其它半导体材料形成。底部晶圆20包括在其中的多个相同的底部芯片24,其中底部芯片24可以彼此相同。切割线26将底部芯片24彼此隔离开。多个顶部管芯30包括有源顶部管芯30A和伪管芯30B,所述顶部管芯30接合在底部芯片24上。在整个描述中,术语“有源管芯”和“有源顶部管芯”是指具有电气功能的管芯或者芯片,所述电气功能有助于最终得到的封装件的电气操作,而术语“伪管芯”是指不具有任何电气功能的管芯或者芯片,并且所述伪管芯对最终得到的封装件的电气操作不起作用。有源顶部管芯30可以是器件管芯,也可以是封装件,该封装件包括接合在其它封装元件上的器件管芯,如封装衬底,***件(interposer)或者类似物。
图1B示出了图1A中显示的结构的截面图,其中截面图沿图1A中的横穿线1B-1B的平面得到。底部芯片24可以是有源芯片,包括有源器件,接触插塞,金属线,通孔等(这些形成在衬底38的顶部表面38A上),尽管它们未在图1B中显示。如图1B所示,底部芯片24可以与一个或者多个有源顶部管芯30A接合。电连接件32将有源顶部管芯30A接合到底部管芯24。电连接件32可以焊接凸点,粘合金属和金属的粘接剂,接合到金属柱的焊料突块或者类似物,并且可以用于在底部芯片24和有源顶部管芯30A之间传导电信号。因此,有源顶部管芯30A中的集成电路器件例如晶体管(未显示)与在底部芯片24中的器件电连接。在一种实施例中,电连接件32与半导体衬底38中的衬底通孔(TSV,有时也被称为硅通孔)36电连接。TSV36从衬底38的顶部表面38A延伸至衬底38的顶部表面38A和底部表面38B之间的中间水平位置。
伪管芯30B附接到底部管芯24,例如,通过管芯附接膜40,管芯附接膜40可以是基于聚合物的胶粘物。可选地,管芯附接膜40可以是能在受热时固化的热塑性薄膜。在一些实施例中,管芯附接膜40可以是在暴露在光线下时失去粘性的粘接剂。伪管芯30B可以是空白管芯,例如可以是半导体管芯(如硅管芯),其不具有有源集成电路器件如晶体管,和/或无源器件如电阻器,电容器,和/或诸如此类的器件。伪管芯30B也可以没有低k电介质层,金属线,通孔,和/或类似物。在一些其它实施例中,伪管芯30B可以是电介质管芯。在又一些其它实施例中,伪管芯30B可以再利用在测试中失败的劣质管芯,并因此可以包括本文中诸如晶体管之类的集成电路。然而,如果可以的话,在伪管芯30B中的集成电路器件在最终得到的封装件60(图5)的操作中不执行任何电气功能,并且不被供电。
管芯附接膜40可以由电绝缘材料形成,并且可以使伪管芯30B和底部芯片24电绝缘。尽管图1A示出了接合底部芯片24的单个伪管芯30B,在可替代的实施例中,多个伪管芯30B可以接合到同一底部芯片24上。
再参考图1A,一些伪管芯30B接合到底部芯片24上,底部芯片24是具有矩形形状的完整的芯片,并且是功能性芯片。另外的伪管芯30B也可以接合到不完整的底部芯片24’上。不完整的底部芯片24’位于晶圆20的边缘,并且不具有矩形形状。不完整的底部芯片24’不封装为供使用的产品。因此,没有有源顶部管芯30A接合到不完整的底部芯片24’上。
图2A和图2B示出了模制工艺。模塑料44填充在有源顶部管芯30A和伪管芯30B之间的间隙内。模塑料44的顶部表面可以高于有源顶部管芯30A和伪管芯30B的顶部表面。然后进行固化工艺以固化模塑料44。
图2A示出了通过横穿图1A中的线1B-1B的同一平面得到的截面图。如图2A所示,模塑料44与有源顶部管芯30A,伪管芯30B,管芯附接膜40和底部芯片24物理接触。图2B示出了不完整的底部芯片24’的截面图,其中,其是从横穿图1A中的线2B-2B同一平面获得的截面图。如图2B所示,管芯附接膜40使伪管芯30B接合不完整的管芯24’,并且模塑料44可以与管芯附接膜40,伪管芯30B,和不完整的管芯24’物理接触。
然后,如图3所示,进行平坦化例如研磨以去除过多的模塑料44,以便模塑料44的顶部表面44A是平的。在一实施例中,进行平坦化直到暴露出有源顶部管芯30A的顶部表面30A和伪管芯30B。
在图1A示例的实施例中,接合到同一底部芯片24上的有源顶部管芯30A的整个俯视区域小于底部芯片24的俯视区域。此外,底部芯片24的芯片区域的很大一部分没有被有源顶部管芯30A覆盖。这导致有源顶部管芯30A相互之间形成大间隙,并因此,在如图3所示的结构中,如果伪管芯30B不存在,模塑料44会有高图案密度,特别是在包括大间隙的芯片区域。另一方面,在一些包括有源顶部管芯30A的其他芯片区域,塑料膜44的图案密度低。通过***伪管芯30B,遍及晶圆20的塑料膜44的图案密度更均匀。这可以帮助降低最终得到的封装件的弯曲(例如如图3中所示的结构),最终得到的封装件包括底部晶圆20,顶部管芯30和模塑料44。
参考图4,如图3所示的封装件结构被翻转颠倒。塑料膜44和顶部管芯30粘接(接合)在载具48上,例如,通过粘接剂50。在一实施例中,粘接剂50是光脱粘膜,它在暴露于光线时失去粘合性。例如,粘接剂50可以是紫外线胶(UV)。粘接剂50也可以是热脱粘膜,它在受热时失去粘合性。粘接剂50也可以由与管芯附接膜40的材料基本相同的材料形成。在一个示例性的形成工艺中,进行背侧研磨以研磨衬底38,直到露出TSV36。
参考图5,形成底部芯片24(和底部晶圆20)的背侧互连结构。在一个示例性的实施例中,背侧互连结构包括电介质层52,和焊盘/再分配线54。焊盘/再分配线54电连接TSV。其次,连接件56可以设置或者形成在焊盘54上。在一些实施例中,连接件56是焊球或者焊接凸点,连接件56被设置或者形成以便回焊。在可选实施例中,连接件56可以包括用于粘合金属与金属的粘接剂,接合到金属柱的焊接凸点,或者类似物,并且连接件56可用于在芯片24和另一封装元件(例如,器件管芯,***件,封装衬底或者印刷电路板(PCB))之间传导电信号。
接下来,如图6所示,将载具48与晶圆20分离(不再接合)(例如通过将图4所示的粘接剂暴露在光中),以致可以去除粘接剂50和载具48。然后进行切割管芯步骤以将晶圆20切割开从而形成多个封装件60,其中,多个封装件60中的一个在图6中显示。在最终得到的封装件60中,伪管芯30B保留,并且伪管芯30B在后续的封装工艺后(例如,将封装件60接合到封装衬底,***件,印刷电路板(PCB)等)没有被去除。另外,在封装件60被使用以及被供电时,伪管芯30B仍然存在。
图7和图8示出了根据可选实施例的在封装件结构的形成的中间阶段的截面图。除非另有说明,在这些实施例中的参考标号表示如图1至图6中所示的实施例中的相同元件。参考图7,提供了底部芯片24。需要指出的是,底部芯片24可以包括有源器件,接触插塞,金属线,通孔等,尽管图7中未显示它们。在一些实施例中,底部芯片24已经从相应的晶圆锯开并分离,因此这以后也被称为底部管芯24。在可选实施例中,底部芯片24是还没有切割分开的晶圆的一部分。晶圆可以包括多个与示例的底部芯片24大致相同的芯片。背侧互连结构包括形成在底部管芯24上的背侧电介质层52和金属线/焊盘54。连接件56可以任选地形成在背侧互连结构上,并且电连接在底部管芯24中的TSV36和器件诸如晶体管。
在图8中,有源顶部管芯30A接合底部管芯24,并且伪管芯30B附接底部管芯24。接合方法,附接方法,和各自的材料可以基本与图1B中所示的一致,因此在此不再赘述。接下来,模塑料44被应用,固化,并且可选地被研磨。所得的结构可以基本与如图6所示的一致。在图7和图8中的底部芯片是晶圆的一部分的实施例中,可以进行管芯切割步骤以将晶圆切割并分离开,使得与图8中所类似的芯片彼此分离,并且每一个芯片均具有如图8中的结构。在实施例中,通过伪管芯附接到晶圆或者底部管芯上,模塑料的图案密度可以更均匀,因此可以降低在最终得到的封装件中的弯曲。弯曲降低导致最终得到的封装件中不同层之间的分层降低。结果,模塑料具有更好的抗潮渗透性。因而提高了封装的可靠性。伪管芯的使用使得在最终得到的封装件中更少地使用模塑料,并因此降低了来自模塑料的排气。
根据一些实施例,器件包括底部芯片和接合在底部芯片上的有源顶部管芯。伪管芯附接到底部芯片上。伪管芯与底部芯片电隔离。
根据一些其它实施例,器件包括底部晶圆,所述底部晶圆包括多个相同的芯片。多个有源顶部管芯接合到底部晶圆,其中多个有源顶部管芯中的每个均通过电连接件接合多个相同的芯片。多个伪管芯附接到底部芯片,其中,多个伪管芯中的每个附接到多个相同芯片中的一个。所述器件进一步包括多个管芯附接膜,其中多个管芯附接膜中的每一个将多个伪管芯中的一个粘附到在多个相同芯片中的一个。
根据又一些其它实施例,一种方法包括将多个有源顶部管芯接合到底部晶圆上。多个有源顶部管芯中的每个均通过电连接件接合到在底部晶圆中的多个相同芯片中的一个。多个伪管芯附接到多个相同的芯片。多个伪管芯中的每个均通过多个管芯附接膜中的一个附接到多个相同芯片中的一个。多个伪管芯通过多个管芯附接膜与多个相同的芯片电隔离。将模塑料填充到多个有源顶部管芯和多个管芯伪管芯之间的间隙中。
虽然已经对本发明进行详细的描述,应当理解,本发明其它变化的实施方式仍落入本发明的始终和保护范围之内。此外,本申请的范围不局限于说明书中所描述的工艺、机器、制造以及要素组合、装置、方法和步骤的特定实施方式。本领域技术人员根据本发明容易得到目前存在的或随后改进的工艺、机器、制造、要素组合、装置、方法或步骤,根据本发明可实现大体相同的功能或实现与本文所描述的相关实施方式大体相同的结果。因此,所附的权利要求包括在这些工艺、机器、制造、要素组合、装置、方法或步骤的范围内。另外每项权利要求构成独立的实施方式,并且各种权利和实施方式的组合同样属于本发明的范围。
Claims (10)
1.一种器件,所述器件包括:
底部芯片;
有源顶部管芯,接合到所述底部芯片;和
伪管芯,附接到所述底部芯片,其中所述伪管芯与所述底部芯片电隔离。
2.如权利要求1所述的器件,其中所述伪管芯选自基本上由以下组成的组中:在其中没有集成电路的空白管芯,在其中没有低k电介质层、金属线、和通孔的硅管芯,和它们的组合。
3.如权利要求1所述的器件,其中所述伪管芯设置成不与电源连接。
4.如权利要求1所述的器件,其中所述有源顶部管芯接合到所述底部芯片并且通过电连接件与所述底部芯片电连接,其中所述伪管芯通过粘接剂粘附到所述底部芯片,并且其中所述伪管芯通过所述粘接剂与所述底部芯片电隔离。
5.一种器件,所述器件包括:
底部芯片,包括:
衬底;
通孔,从所述衬底的第一侧延伸至所述衬底的第二侧;
第一连接件,在所述衬底的所述第一侧上;和
第二连接件,在所述衬底的所述第二侧上,其中所述第一连接件通过所述通孔与所述第二连接件电连接;
有源顶部管芯,在所述衬底的所述第一侧上,所述有源顶部管芯通过所述第一连接件接合到所述底部芯片;
伪管芯,在所述衬底的所述第一侧上;和
管芯附接膜,使所述伪管芯附接到所述底部芯片。
6.如权利要求5所述的器件,其中所述伪管芯设置成不与任何电源连接。
7.如权利要求6所述的器件,其中所述管芯附接膜包括介电材料,并且其中没有导电部件穿透所述管芯附接膜。
8.一种方法,所述方法包括:
将多个有源顶部管芯接合到底部晶圆,其中所述多个有源顶部管芯的每个均通过电连接件接合到在所述底部晶圆中的多个相同的芯片中的一个;
将多个伪管芯附接到所述多个相同的芯片,其中所述多个伪管芯的每个均通过多个管芯附接膜中的一个附接到多个相同的芯片中的一个,并且其中所述多个伪管芯通过所述多个管芯附接膜与所述多个相同的芯片电隔离;和,
将模塑料填充到所述多个有源顶部管芯和所述多个伪管芯之间的间隙内。
9.如权利要求8所述的方法,进一步包括:
在施加所述模塑料的步骤之前,将伪管芯附接到在所述底部晶圆中的不完整的底部芯片,其中所述模塑料与所述伪管芯物理接触。
10.如权利要求8所述的方法,进一步包括:
在填充所述模塑料的步骤之后,使用粘接剂将载具附接到所述底部晶圆;
对在所述底部晶圆中的衬底进行背侧研磨以暴露在所述底部晶圆中的硅通孔;和
在所述底部晶圆的背侧上形成背侧互连结构;和
切割所述底部晶圆以形成多个封装件,其中所述多个封装件中的每个均包括所述多个有源顶部管芯中的一个和所述多个伪管芯中的一个。
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US20140287553A1 (en) | 2014-09-25 |
US9312149B2 (en) | 2016-04-12 |
TW201322319A (zh) | 2013-06-01 |
TWI555074B (zh) | 2016-10-21 |
US20130119552A1 (en) | 2013-05-16 |
US8779599B2 (en) | 2014-07-15 |
CN103117279B (zh) | 2016-10-05 |
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