CN102714143B - 外延片以及半导体元件 - Google Patents

外延片以及半导体元件 Download PDF

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CN102714143B
CN102714143B CN201080060769.2A CN201080060769A CN102714143B CN 102714143 B CN102714143 B CN 102714143B CN 201080060769 A CN201080060769 A CN 201080060769A CN 102714143 B CN102714143 B CN 102714143B
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silicon carbide
layer
resilient coating
alloy
carbide substrate
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CN102714143A (zh
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大塚健一
黑田研一
渡边宽
油谷直毅
炭谷博昭
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Mitsubishi Electric Corp
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Abstract

提供一种碳化硅外延片以及碳化硅半导体元件，可提高外延生长层的晶体质量，在形成厚膜的外延生长层时也不会使载流子移动性降低，且元件电阻低。碳化硅半导体元件（101）具有：n型碳化硅基板（1），以浓度C掺杂了氮那样的通过掺杂会使晶格常数减小的掺杂物；n型碳化硅外延生长层（3），以比碳化硅基板小的浓度掺杂了与碳化硅基板（1）相同的掺杂物；和n型缓冲层，在碳化硅基板（1）与碳化硅外延层（3）之间掺杂了所述掺杂物。缓冲层（2）以层叠了2层以上的相同厚度的层而成的多层构造形成，相对多层构造的层数N，从碳化硅外延层（3）侧起第K个层的掺杂浓度成为C·K/（N+1）。

Description

外延片以及半导体元件
技术领域
本发明涉及以碳化硅为材料的外延片（Epitaxialwafer）以及使用该外延片形成的半导体元件。
背景技术
在使用了碳化硅半导体的半导体元件中，作为元件构造，将在低电阻基板上生长的外延生长层用作动作层的情况较多。在功率半导体元件中外延生长层作为耐压层而发挥功能，但通常外延生长层由单层形成（例如，参照专利文献1），根据动作的电压，外延生长层是3~100μm或者其以上的厚度，其掺杂浓度至多为1016cm－3量级，是1015cm－3量级的情况较多。相对于此，在成为基板的低电阻晶体中掺杂了1019cm－3左右的掺杂物的情况较多。因此，在外延生长层（耐压层）与基板中掺杂浓度大不相同，所以两者的晶格常数不同，在外延生长层的厚度厚的情况下，由于晶格常数差、即与晶格失配相伴的晶体缺陷的导入而使外延生长层的晶体质量变差，其结果，产生载流子的移动性降低而使元件电阻增大这样的问题。
因此，为了缓和由于晶格常数差而产生的向晶体质量的影响，针对（11－20）面的碳化硅晶体，公开了在基板与外延生长层之间设置掺杂浓度为2×1015~3×1019cm-3、层厚为0.3~15μm的缓冲层，并公开了设置上述掺杂浓度以及层厚的范围的单层膜、阶段式倾斜构造、连续式倾斜构造（例如，参照专利文献2）。
另外，针对（0001）面以及（000－1）面的碳化硅晶体，公开了如下方案：作为设置于基板与外延生长层之间的缓冲层，以抑制基面位错被导入外延生长层为目的，层叠多个成为基底的基板的掺杂浓度的1/10~1/2程度的掺杂浓度的层，设置掺杂浓度阶段状地变化的阶段性的倾斜膜（例如，参照专利文献3）。
专利文献1：日本特开平6－268202号公报
专利文献2：日本特开2000－319099号公报
专利文献3：日本特开2008－74661号公报
发明内容
在上述那样的以往的以碳化硅半导体为材料的外延片以及半导体元件中，虽然公开了在基板与成为耐压层的外延生长层之间设置单层膜、掺杂浓度阶段性或者连续性地变化的阶段式倾斜构造或者连续式倾斜构造的缓冲层，但并未公开与基板以及外延生长层的掺杂物的种类、其浓度对应的适合的结构。特别是对于阶段式倾斜构造的缓冲层、连续式倾斜构造的缓冲层，由于未公开考虑了由于所添加的掺杂物而产生的晶格失配的朝向的缓冲层的结构，所以在以往的碳化硅外延片以及半导体元件中，存在外延生长层的晶体质量变差、载流子的移动性降低的情况。
本发明是为了解决上述那样的问题而完成的，实现能够比以往提高外延生长层的晶体质量、即使在形成厚膜的外延生长层的情况下也不会使载流子移动性降低、且元件电阻低的外延片以及半导体元件。
本发明的外延片以及半导体元件的特征在于，具有：第1导电类型的碳化硅基板，以浓度C掺杂了通过掺杂会使晶格常数减小的掺杂物；第1导电类型的缓冲层，设置在所述碳化硅基板上，并掺杂了所述掺杂物；以及第1导电类型的碳化硅外延生长层，设置在所述缓冲层上，以比所述碳化硅基板小的浓度掺杂了所述掺杂物，其中，以层叠了2层以上的厚度大致相同的层而成的多层构造来形成所述缓冲层，所述缓冲层相对所述多层构造的层数N，从所述碳化硅外延生长层侧起第K个层的掺杂浓度是C·K/（N+1）。
根据本发明，能够有效地缓和碳化硅基板与外延生长的晶格失配，所以能够抑制由于碳化硅基板与外延生长层的晶格常数差而产生的晶体缺陷被导入到外延生长层。其结果，能够得到可防止外延生长层的晶体质量变差、即使形成厚膜的外延生长层也不会使载流子的移动性降低、且元件电阻低的外延片以及半导体元件。
附图说明
图1是示出本发明的实施方式1中的半导体元件的构造的截面图。
图2是示出本发明的实施方式1中的外延片的构造的截面图。
图3是示出本发明的实施方式2中的半导体元件的构造的截面图。
（符号说明）
1：碳化硅基板；2：缓冲层；3：漂移层（外延生长层）；100：外延片；101：肖特基势垒二极管；102：MOSFET。
具体实施方式
以下，参照附图，说明本发明的实施方式。另外，在表示晶体面的密勒指数的显示方法中，一般在指数的上面附加表示负的指数的负号，但在本说明书中，在指数的前面附加负号而示出。
实施方式1.
图1是示出本发明的实施方式1中的半导体元件的结构的截面图。另外，图2是示出本发明的实施方式1中的外延片的结构的截面图。
在图2中，外延片100包括：从（0001）面具有倾斜角（off-angle）的作为第1导电类型的n型的低电阻碳化硅基板1、在该碳化硅基板1上形成的n型缓冲层2、以及在该缓冲层2上通过外延生长而形成的外延生长层3。关于缓冲层2的结构，另行详细叙述。
然后，使用该外延片100，形成图1所示的作为半导体元件的碳化硅肖特基势垒二极管101。在肖特基势垒二极管101中，外延片100的外延生长层3成为用于保持耐压的n型漂移层。该漂移层3的层厚是3~150μm程度，掺杂浓度是0.5~20×1015cm－3程度，形成为比碳化硅基板1的掺杂浓度低。另外，在肖特基势垒二极管101的元件周边部，形成有第2导电类型的p型区域4而作为终端构造。在外延片100中的外延生长层3中通过离子注入以及活性化热处理工序而选择性地形成该p型区域4，以层厚为0.5~2μm程度、掺杂浓度为1~100×1017cm-3程度来形成该p型区域4。另外，在漂移层3上，以与p型区域4也接触的方式形成有阳极电极5。而且，阴极电极6形成于n型低电阻碳化硅基板1的背面。
阳极电极5对于漂移层3是肖特基接触，对于p型区域4可以是肖特基接触、欧姆接触中的任一个。为了使阳极电极5针对p型区域4作为欧姆电极发挥功能，作为接触电阻值，如果设为10－3Ωcm2以下，则能够减小经由p型区域4的电流流过时的接触部的影响所致的导通电压的上升。更优选为，如果设为10-4Ωcm2以下的接触电阻值，则能够几乎忽略接触部的影响所致的电压上升。
关于碳化硅基板1，优选以不会导致元件电阻增大的方式使电阻率尽量小，高浓度地掺杂V族元素，但如果掺杂浓度过高，则易于导入晶体缺陷，所以通常以使成为1019cm－3左右的浓度的方式进行掺杂。在本实施方式中，将例如氮那样的随着掺杂为高浓度而使碳化硅晶体的晶格常数变小的元素用作碳化硅基板1的掺杂物。
缓冲层2成为图1的（a）~（c）所示那样的结构。另外，在图1的（a）~（c）所示的图中，纵轴表示厚度方向的距离，横轴表示氮浓度。以层叠了2层以上的掺杂的浓度不同且厚度大致相同的层而得到的多层构造来形成缓冲层2，缓冲层2的掺杂物与碳化硅基板1的掺杂物相同。另外，“厚度大致相同的层”是指，如果是起到本发明的效果的范围，则允许制造上的误差。另外，相对于构成缓冲层2的层的数量N、碳化硅基板1的氮的掺杂浓度C，以使从漂移层3的一侧起第K个层的掺杂浓度成为K·C/（N+1）的方式，层叠了各层。另外，K可取的范围是1≤K≤N。
图1的（a）是示出以2层来构成缓冲层2时的缓冲层2的浓度分布的图。在该情况下，缓冲层2由漂移层侧层2a和基板侧层2b这2层构成，如果碳化硅基板1的氮浓度是1019cm-3，则漂移层侧层2a和基板侧层2b的掺杂浓度分别成为3.3×1018cm-3、6.7×1018cm-3。
图1的（b）是示出以3层来构成缓冲层2时的缓冲层2的浓度分布的图。在该情况下，缓冲层2由漂移层侧层2c、中间层2d以及基板侧层2e这3层构成，如果碳化硅基板1的氮浓度是1019cm-3，则漂移层侧层2c、中间层2d以及基板侧层2e的各掺杂浓度分别成为2.5×1018cm-3、5×1018cm－3以及7.5×1018cm-3。
图1的（c）是示出以4层来构成缓冲层2时的缓冲层2的浓度分布的图。在该情况下，缓冲层2由漂移层侧层2f、漂移层侧中间层2g、基板侧中间层2h以及基板侧层2i构成，如果碳化硅基板1的氮浓度是1019cm-3，则漂移层侧层2f、漂移层侧中间层2g、基板侧中间层2h以及基板侧层2i的掺杂浓度分别成为2×1018cm-3、4×1018cm-3、6×1018cm－3以及8×1018cm-3。
以上示出了构成缓冲层2的层数N是N=2、3、4这3种情况的例子，但也可以是成为这以外的值的结构。这样，通过将缓冲层2设为掺杂浓度以线性标度（Linearscale）大致等间隔地阶段性地减小的层厚大致相同的多层构造，碳化硅基板1与漂移层3之间的晶格常数差被大致等分割为N+1级。其结果，缓冲层2的晶格常数从碳化硅基板1朝向漂移层3以大致相同的晶格常数差而减小，所以能够有效地缓和与碳化硅基板1和漂移层3的晶格常数差相伴的晶格失配的影响。
另外，在掺杂物是氮的情况下，如果增大掺杂浓度，则碳化硅的晶格常数会变小，所以作为外延生长层的漂移层3的晶格常数会大于碳化硅基板1。因此，在缓冲层2中，在水平方向上施加压缩的应力，在外延生长层的生长方向即厚度方向上施加拉伸的应力。这样，关于缓冲层2的杂质浓度，阶段性地使晶格常数以线性标度按照大致相同的变化量变化，由此，在晶体的生长方向上外延生长之后向室温进行冷却时的收缩和拉伸应力变得平衡，晶体缺陷不会在生长方向上延伸，即使生成了晶体缺陷，也会在与和构成缓冲层2的各层或者碳化硅基板1、漂移层3之间的某一个界面平行的方向上延伸，所以能够防止在外延生长层内生成，不会使载流子的移动性降低而能够实现元件电阻低的半导体元件。
另外，通过将构成缓冲层2的各层的厚度设为100nm以下而设为与漂移层3的厚度相比极其小的值，能够抑制由于导入缓冲层2而产生的元件电阻的上升。
实施方式2.
图3是示出本发明的实施方式2中的半导体元件的结构的截面图。
在图3中，作为半导体元件的碳化硅MOSFET102与实施方式1同样地，使用如下外延片100来形成，其中，该外延片100具有：从（0001）面具有倾斜角的n型低电阻碳化硅基板1、在该碳化硅基板1上形成的n型缓冲层2、以及在该缓冲层2上通过外延生长而形成的外延生长层3。另外，缓冲层2的结构与实施方式1相同，外延生长层3作为用于保持耐压的n型碳化硅漂移层而发挥功能的情形也与实施方式1相同。
在n型漂移层3中通过离子注入以及活性化热处理工序，选择性地形成p型碳化硅体区域14以及n型碳化硅源区域15。体区域14的层厚为0.5~2μm程度、掺杂浓度为3~20×1017cm-3程度，体区域14也可以是在形成沟道而成或者接近沟道而成的最表面降低了掺杂浓度的结构。通过降低最表面的掺杂浓度，杂质所致的散射（scattering）被降低，沟道中的载流子移动性增加而能够降低元件电阻。也可以另行选择性地进行离子注入，以使体区域14中的仅接触区域24的最表面区域成为5~50×1018cm－3程度而成为浓度比其他部分高的掺杂。源区域15的层厚为0.3~1μm程度、掺杂浓度为5~50×1018cm－3程度。
在该层构造上形成栅绝缘膜17、栅电极18而制作栅部。虽然在图3所示的MOSFET102中没有设置沟道层，但也可以另行设置沟道层。在设置沟道层的情况下，其导电类型既可以是n型也可以是p型，为了改善由于离子注入核素（ionimplantationspecies）的活性化热处理而发生的表面粗糙，优选例如通过外延生长来形成，但如果由于活性化热处理而发生的表面粗糙少，则也可以是通过选择性的离子注入而形成了沟道层的构造。
既可以一并进行离子注入核素的活性化热处理，也可以针对各个注入工序的每一个进行活性化热处理。
关于栅绝缘膜17，通过碳化硅半导体的热氧化、氮化、或者将绝缘膜进行堆积沉积来形成氧化硅膜或者氮氧化硅膜等，或者通过一并使用它们而在体区域中的与成为沟道的区域34相对的部分中形成为10~100nm程度的厚度。
栅电极18是通过多晶硅膜、金属膜的沉积而形成的。对于栅部以外的区域，去除沟道层（未图示）、栅绝缘膜17、栅电极18。关于沟道层，也可以在形成栅绝缘膜17之前除去栅部以外的区域。在形成了层间绝缘膜19之后，在除去成为源电极20的接触部的区域的层间绝缘膜之后形成源电极20。而且，在n型基板1的背面形成漏电极21，在源电极20以及层间绝缘膜19上形成布线22。虽然未图示，但成为在形成栅电极焊盘的元件外周部的一部分区域中层间绝缘膜上的布线22被除去了的结构。
缓冲层2是与图1所示那样的实施方式1同样的结构，通过将缓冲层2设为使掺杂浓度以线性标度大致等间隔地阶段性地减小的大致相同层厚的多层构造，能够防止晶体缺陷导入到作为外延生长层的漂移层3，不会使载流子的移动性降低而能够抑制元件电阻的上升。
另外，通过将构成缓冲层2的各层的厚度设为100nm以下而成为与漂移层3的厚度相比极其小的值，能够抑制由于导入缓冲层2而发生的元件电阻的上升。
在上述实施方式1、2中，将碳化硅基板1的面方位设为从（0001）面具有倾斜角的面，但在不具有倾斜角的（0001）面、（000－1）面、（11－20）面、（03－38）面等任一个晶体面方位中，图1所示的结构的缓冲层也能够防止晶体缺陷导入到外延生长层，并且能够抑制元件电阻的上升。
另外，在实施方式1、2中，作为掺杂物示出了氮的例子，但即使是氮以外，只要是通过掺杂会使碳化硅晶体的晶格常数减小的掺杂物，通过将缓冲层设为图1所示的结构，就能够防止晶体缺陷导入到外延生长层，并且能够抑制元件电阻的上升。

Claims (6)

1.一种外延片，其特征在于，具有：
第1导电类型的碳化硅基板，以浓度C掺杂了通过掺杂会使晶格常数减小的掺杂物；
第1导电类型的缓冲层，设置在所述碳化硅基板上，并掺杂了所述掺杂物；以及
第1导电类型的碳化硅外延生长层，设置在所述缓冲层上，以比所述碳化硅基板小的浓度掺杂了所述掺杂物，其中，
以层叠了2层以上的厚度大致相同的层而成的多层构造来形成所述缓冲层，所述缓冲层相对所述多层构造的层数N，从所述碳化硅外延生长层侧起第K个层的掺杂浓度是C·K/(N+1)。
2.根据权利要求1所述的外延片，其特征在于，
所述掺杂物是氮。
3.根据权利要求1或者2所述的外延片，其特征在于，
构成所述缓冲层的各层的层厚是100nm以下。
4.一种半导体元件，其特征在于，具有：
第1导电类型的碳化硅基板，以浓度C掺杂了通过掺杂会使晶格常数减小的掺杂物；
第1导电类型的缓冲层，设置在所述碳化硅基板上，并掺杂了所述掺杂物；以及
第1导电类型的碳化硅外延生长层，设置在所述缓冲层上，以比所述碳化硅基板小的浓度掺杂了所述掺杂物，其中，
以层叠了2层以上的厚度大致相同的层而成的多层构造来形成所述缓冲层，所述缓冲层相对所述多层构造的层数N，从所述碳化硅外延生长层侧起第K个层的掺杂浓度是C·K/(N+1)，
所述碳化硅外延生长层是漂移层。
5.根据权利要求4所述的半导体元件，其特征在于，
所述掺杂物是氮。
6.根据权利要求4或者5所述的半导体元件，其特征在于，
构成所述缓冲层的各层的层厚是100nm以下。
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