CN102637450B - Address decoder of current sharing-type memory - Google Patents
Address decoder of current sharing-type memory Download PDFInfo
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- CN102637450B CN102637450B CN201210109999.4A CN201210109999A CN102637450B CN 102637450 B CN102637450 B CN 102637450B CN 201210109999 A CN201210109999 A CN 201210109999A CN 102637450 B CN102637450 B CN 102637450B
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- 238000003491 array Methods 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 238000002592 echocardiography Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005039 memory span Effects 0.000 description 1
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Abstract
The invention discloses an address decoder of a current sharing-type memory. The address decoder comprises multiple address decoding circuits with a current sharing port, wherein the current sharing ports of each address decoding circuit are connected together to share driving current, so that the driving capacity of the address decoder is enhanced. The address decoding circuit consists of an address decoding unit and a driving unit, wherein the address decoding unit is used for decoding a memory address and outputting decoding signals with a differential form; and the driving unit uses an active pull-down circuit, amplifies the decoding signal, then outputs single-ended driving signals, provides pull-down current to drive an equivalent capacitor formed by memory arrays, and provides a current sharing port. The address decoder has the advantages that the driving capacity of the decoding circuit is enhanced by utilizing the active pull-down circuit, and the current sharing port is provided. The address decoder has the characteristics of simple circuit structure, stable circuit, low power consumption, high working speed, strong driving capacity, and the like.
Description
Technical field
The present invention relates to integrated circuit memory design field, particularly the address decoder of the shared storer of a kind of electric current.
Background technology
Semiconductor memory is generally made up of address decoder, storage array and sense amplifier.Address decoder is made up of multiple address decoding circuitries, for the storer of N bit address, needs 2
nindividual address decoding circuitry.Along with the increase of memory span, storage array is increasing.Storage array, for address decoding circuitry, is equivalent to electric capacity.Along with the increase of storage array, equivalent capacity also increases gradually.Address decoding circuitry, general employing penetrated a grade follower driving storage array, as shown in Figure 1.But penetrate grade follower in the time driving load capacitance, there are serious problems.Along with the increase of load capacitance, penetrating a grade negative edge for follower signal output waveform sharply increases.Fix owing to penetrating a grade follower working current, slow to the load capacitance velocity of discharge, its output signal is obviously long than the rise time fall time.Load capacitance is larger, the rise time and fall time difference larger.Rise time and fall time are different, greatly reduce the operating rate of circuit.The working current that grade follower is penetrated in increase can reduce fall time, the difference that reduces rise time and fall time, but power consumption also increases greatly.
Summary of the invention
(1) technical matters that will solve
In view of this, fundamental purpose of the present invention is the address decoder of the shared storer of electric current that a kind of high speed, low-power consumption are provided, can drive jumbo memory array, in order to solve traditional address decoding circuitry driving when large capacity storage array its signal fall time much larger than the rise time, solve the bottleneck of its operating rate.
(2) technical scheme
In order to achieve the above object, the invention provides the address decoder of the shared storer of a kind of electric current, this address decoder comprises multiple address decoding circuitries with electric current shared port, the electric current shared port of each address decoding circuitry links together, realize and share drive current, to increase the driving force of address decoder.
In such scheme, the described address decoding circuitry with electric current shared port comprises address decoder unit and driver element, and wherein address decoder unit is for dividing decoded signal to output difference after decoded memory address; Driver element is used for this differential decoding signal to amplify to increase driving force, and provides pull-down current in order to drive the equivalent capacity that in storer, storage array forms, and electric current shared port is provided.
In such scheme, there is multiple way of realization described address decoder unit, comprises the rejection gate based on emitter-coupled logic, or diode AND gate.
In such scheme, described driver element is an active pull down circuit, comprising:
The first resistance R
1, the first resistance R
1one end ground connection, the in-phase end of the other end and differential decoding signal and the 3rd transistor Q
3base stage be connected;
The second resistance R
2, the second resistance R
2the end of oppisite phase of one end and differential decoding signal and the 4th transistor Q
4base stage be connected, the other end and the 3rd transistor Q
3emitter and the 4th transistor Q
4collector be connected;
The 3rd transistor Q
3, base stage and the first resistance R
1be connected, grounded collector, emitter is as output node V
owith the second resistance R
2and the 4th transistor Q
4collector is connected;
The 4th transistor Q
4, base stage and the second resistance R
2one end is connected, and collector is as output node V
owith the second resistance R
2the other end and the 3rd transistor Q
3emitter is connected, and emitter is as electric current shared port V
c, with drive current source I
2be connected.
Drive current source I
2, one end is as electric current shared port V
cwith the 4th transistor Q
4emitter is connected, and the other end is connected with power supply VEE.
In such scheme, described drive current source I
2there is multiple way of realization, comprise multiple little current source parallel connections are equivalent to a large current source, or the drive current source in multiple address decoding circuitries is linked together by electric current shared port.
(3) beneficial effect
Can find out from technique scheme, the present invention has following beneficial effect:
1, the address decoder of the shared storer of electric current provided by the invention, adopt active pull down circuit to strengthen driving force, and by sharing electric current between multiple driver elements, realize the electric current of drive current source is redistributed, increase the discharge process of pull-down current accelerating weight electric capacity, reach reduce provide when circuit power consumption enough drive currents solved traditional address decoding circuitry in the time driving large capacity storage array its signal fall time much larger than the rise time, solve the bottleneck of its operating rate, thereby improved the operating rate of circuit.
2, the address decoder of the shared storer of electric current provided by the invention, its advantage is to adopt active pull down circuit to strengthen the driving force of decoding circuit, and electric current shared port is provided, there is the features such as circuit structure is simple, circuit stable, low in energy consumption, operating rate is fast, driving force is strong.
Brief description of the drawings
Fig. 1 is the schematic diagram of legacy memory address decoding circuitry;
Fig. 2 is the schematic diagram of low-power consumption high speed address decoding circuitry of the present invention;
Fig. 3 is the schematic diagram of the address decoder of the low-power consumption of the present invention shared storer of electric current at a high speed;
Fig. 4 is the schematic diagram of address decoding circuitry of the present invention circuit working principle in the time of address switchover;
Fig. 5 is the multiple way of realization schematic diagram of current source in the present invention;
To be decoded memory address circuit of the present invention driving 2.0pF electric capacity output waveform to Fig. 6, with the schematic diagram of the comparison of traditional circuit;
Fig. 7 is the schematic diagram that the signal output waveform of decoded memory address circuit of the present invention changes along with load capacitance.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
It should be noted that, the specific embodiment of the present invention adopts negative supply power supply, rail ground connection on power supply, and lower rail is negative supply VEE.Certainly, also can adopt positive supply power supply, now on power supply, rail is power supply VCC, lower rail ground connection.
A kind of example structure of low-power consumption high speed address decoding circuitry of the present invention as shown in Figure 2, comprises address decoder unit 100 and driver element 200 two parts.
Address decoder unit 100 adopts emitter coupled logical OR not gate (ECL NOR) structure.N difference address A
1a
2... A
nrespectively with transistor Q
1-1q
1-2... Q
1-Nbase stage be connected.N transistor Q
1-1q
1-2... Q
1-Nbe relation in parallel, referred to as Q
1.Q
1emitter and Q
2emitter be connected simultaneously and current source I
1be connected, Q
2base stage and N difference address A
1a
2... A
ncommon mode electrical level V
bbe connected.Current source I
1the other end is connected with power supply VEE.Q
1collector and resistance R
1be connected simultaneously and the transistor Q of driver element 200
3base stage is connected; Q
2collector and resistance R
2connected time and the transistor Q of driver element 200
4base stage is connected.Resistance R
1the other end is connected to the ground, resistance R
2transistor Q in the other end and driver element 200
3emitter and Q
4collector is connected, and this node of mark is Vo.
Driver element 200, is an active pull down circuit, wherein middle Q
3collector is connected to ground, Q
4emitter and pull-down current source I
2be connected, and this shared current node of mark is V
c, I
2the other end be connected with power supply VEE.
As shown in Figure 3, for N bit addresses storer, need 2
nindividual address decoding circuitry, in order to produce 2
nindividual memory array drives signal.The address decoder of the shared storer of electric current provided by the invention is by 2
nthe V of individual address decoding circuitry
cbe connected, thus, 2
nindividual address decoding circuitry can share 2
nindividual pull-down current source.Suppose, the storage array of storer is chosen in the representative of address decoding circuitry output high level signal.The address decoding circuitry feature of storer is synchronization 2
nin individual address decoding signal, only having one is high level.Switch moment, 2 in storage address
nin the output of individual address decoder unit, only have one to be switched to low level from high level, only have one to be switched to high level from low level, all the other keep low level.
Address decoding circuitry is used for accelerating its output and is switched to low level discharge process from high level, and is switched to the charging process of high level from low level.The present invention passes through to share electric current and increases pull-down current required while electric discharge, increases charging current required while charging simultaneously, as shown in Figure 4, and wherein C
1and C
2represent the equivalent capacity that storage array forms.
Suppose address decoding circuitry V
o1be switched to low level from high level, V
o2be switched to high level from low level.Decoding unit 100 of the present invention produces the differential signal of two single spin-echos.For this reason at V
o1while being switched to low level from high level, V
b1be switched to high level, thereby increase Q
2in electric current, accelerate to load capacitance C
1electric discharge.At V
o2while being switched to high level from low level, V
b2be switched to low level, Q
4in cut-off state, Q
3middle electric current is all used for accelerating load capacitance C
2charging.Q
4in cut-off state, current source I for this reason
2there is unnecessary electric current.To C
1after electric discharge finishes, V
b1return to low level, Q
2middle electric current will reduce, current source I
1in unnecessary electric current will be used for accelerating next discharge process by shared mode.
The principle that shared electric current of the present invention accelerates discharge process is, synchronization only has an address decoding circuitry in discharge process, other address decoding circuitries in low level output will have unnecessary electric current, address decoding circuitry in charging process is also had to unnecessary electric current simultaneously, share by electric current, realize the electric current of drive current source is redistributed, unnecessary other address circuits electric current collection is got up for increasing discharge current, accelerate discharge process.
Current source described in the present invention has multiple way of realization, as shown in Figure 5.
Adopt traditional circuit as shown in Figure 1 to drive load capacitance C
l, along with the increase of load capacitance, drive the negative edge time of signal will obviously be greater than rising edge, limit the operating rate of circuit.Decoded memory address circuit of the present invention is driving 2.0pF electric capacity output waveform, and with the comparative result of traditional circuit, as shown in Figure 6, the negative edge time of circuit of the present invention is significantly less than traditional circuit.And adopt the shared address decoding circuitry of electric current provided by the invention to drive same load capacitance C
l, at C
lbe increased to 2.5pF from 0.5pF, negative edge time and rising time are not significantly increased, and both are substantially equal, as shown in Figure 7, and visible validity of the present invention.
It should be noted that, although address decoder unit 100 adopts emitter coupled logical OR not gate (ECL NOR) structure to describe in example structure, the present invention can answer other address decoder element circuits.
It should be noted that, although adopt bipolar transistor to describe in diagram, structure of the present invention can be applied to MOS circuit.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (3)
1. the address decoder of the shared storer of electric current, it is characterized in that, this address decoder comprises multiple address decoding circuitries with electric current shared port, the electric current shared port of each address decoding circuitry links together, realize and share drive current, to increase the driving force of address decoder;
Wherein, the described address decoding circuitry with electric current shared port comprises address decoder unit and driver element, and wherein address decoder unit is for dividing decoded signal to output difference after decoded memory address; Driver element is used for this differential decoding signal to amplify to increase driving force, and provides pull-down current in order to drive the equivalent capacity that in storer, storage array forms, and electric current shared port is provided;
Described driver element is an active pull down circuit, comprising:
The first resistance R
1, the first resistance R
1one end ground connection, the in-phase end of the other end and differential decoding signal and the 3rd transistor Q
3base stage be connected;
The second resistance R
2, the second resistance R
2the end of oppisite phase of one end and differential decoding signal and the 4th transistor Q
4base stage be connected, the other end and the 3rd transistor Q
3emitter and the 4th transistor Q
4collector be connected;
The 3rd transistor Q
3, base stage and the first resistance R
1be connected, grounded collector, emitter is as output node V
owith the second resistance R 2 and the 4th transistor Q
4collector is connected;
The 4th transistor Q
4, base stage and the second resistance R
2one end is connected, and collector is as output node V
owith the second resistance R
2the other end and the 3rd transistor Q
3emitter is connected, and emitter is as electric current shared port V
c, with drive current source I
2be connected;
Drive current source I
2, one end is as electric current shared port V
cwith the 4th transistor Q
4emitter is connected, and the other end is connected with power supply VEE.
2. the address decoder of the shared storer of electric current according to claim 1, is characterized in that, there is multiple way of realization described address decoder unit, comprises the rejection gate based on emitter-coupled logic, or diode AND gate.
3. the address decoder of the shared storer of electric current according to claim 1, is characterized in that, described drive current source I
2there is multiple way of realization, comprise multiple little current source parallel connections are equivalent to a large current source, or the drive current source in multiple address decoding circuitries is linked together by electric current shared port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210109999.4A CN102637450B (en) | 2012-04-13 | 2012-04-13 | Address decoder of current sharing-type memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210109999.4A CN102637450B (en) | 2012-04-13 | 2012-04-13 | Address decoder of current sharing-type memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102637450A CN102637450A (en) | 2012-08-15 |
| CN102637450B true CN102637450B (en) | 2014-09-17 |
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ID=46621816
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210109999.4A Active CN102637450B (en) | 2012-04-13 | 2012-04-13 | Address decoder of current sharing-type memory |
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| Country | Link |
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| CN (1) | CN102637450B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11149927B2 (en) * | 2019-03-01 | 2021-10-19 | Xiamen Eco Lighting Co. Ltd. | LED lighting apparatus |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5021688A (en) * | 1988-10-28 | 1991-06-04 | International Business Machines Corporation | Two stage address decoder circuit for semiconductor memories |
| CN101060594A (en) * | 2006-02-27 | 2007-10-24 | 索尼株式会社 | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100630346B1 (en) * | 2005-07-05 | 2006-10-02 | 삼성전자주식회사 | Circuit and method for driving word line by charge sharing on reading mode |
-
2012
- 2012-04-13 CN CN201210109999.4A patent/CN102637450B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5021688A (en) * | 1988-10-28 | 1991-06-04 | International Business Machines Corporation | Two stage address decoder circuit for semiconductor memories |
| CN101060594A (en) * | 2006-02-27 | 2007-10-24 | 索尼株式会社 | Semiconductor device |
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|---|---|
| CN102637450A (en) | 2012-08-15 |
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Effective date of registration: 20180904 Address after: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee after: Beijing Zhongke micro Investment Management Co.,Ltd. Address before: 100083 No.3, Beitucheng Road (West), Chaoyang District, Beijing Cities Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |
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| TR01 | Transfer of patent right |
Effective date of registration: 20181107 Address after: 215000 Jiangsu Suzhou Industrial Park 99 Jinji Hu Road 99 Suzhou Nancheng 1 building 505 room Patentee after: Zhongke core (Suzhou) Microelectronics Technology Co.,Ltd. Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee before: Beijing Zhongke micro Investment Management Co.,Ltd. |
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Effective date of registration: 20190814 Address after: Unit 505, 218 A7 Building, Xinghu Street, Suzhou Industrial Park, Jiangsu Province Patentee after: ACELA MICRO CO.,LTD. Address before: Room 505, No. 99 Jinjihu Avenue, Suzhou Industrial Park, Jiangsu Province Patentee before: Zhongke core (Suzhou) Microelectronics Technology Co.,Ltd. |
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Address after: Room 708-1, Building 1, Northwest District, Suzhou Nanocity, No. 99 Jinjihu Avenue, Suzhou Industrial Park, Suzhou Area, China (Jiangsu) Free Trade Pilot Zone, Suzhou City, Jiangsu Province, 215124 Patentee after: Xunxin Microelectronics (Suzhou) Co.,Ltd. Address before: 215000 unit 505, a7 / F, 218 Xinghu street, Suzhou Industrial Park, Jiangsu Province Patentee before: ACELA MICRO CO.,LTD. |
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