CN1777036A - Hybrid two-layer folding circuit for high speed low-power consumption folding structure A/D converter - Google Patents
Hybrid two-layer folding circuit for high speed low-power consumption folding structure A/D converter Download PDFInfo
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- CN1777036A CN1777036A CN 200510111061 CN200510111061A CN1777036A CN 1777036 A CN1777036 A CN 1777036A CN 200510111061 CN200510111061 CN 200510111061 CN 200510111061 A CN200510111061 A CN 200510111061A CN 1777036 A CN1777036 A CN 1777036A
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Abstract
The disclosed circuit is composed of amplifying circuit and output circuit. The amplifying circuit includes M pieces of identical amplifying unit in two layers. These amplifying units carry out amplification for 3*M pairs of difference input voltage. These difference inputs are supplied by outputs from preamplification, sample and hold unit. Output circuit consists of two pieces of resistance. Comparing with number of power supply in traditional folding circuit, the number of power supply needed in the invention is reduced greatly. Moreover, since number of transistor in difference input connected to output node is reduced greatly, parasitic capacitance between grid and drain poles at output node is reduced greatly.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of hybrid two-layer folding electric circuit that is used for high-speed low-power-consumption foldable structure analog to digital converter.
Background technology
As a bottleneck in the mixed-signal system chip, chip area, power consumption and design time that high-speed AD converter consumption is a large amount of.Simultaneously, the analog to digital converter of high speed intermediate resolution has a wide range of applications at aspects such as high-speed data communication, liquid crystal display driving, digital oscilloscope, hard drive circuit.In the analog-digital converter circuit structure of numerous kinds, foldable structure has at a high speed, area is little and advantages such as easy and digital technology compatibility.
Compare with all-parallel A/D converter, collapsible analog to digital converter is owing to having adopted folding electric circuit to greatly reduce the number of comparator, and the quantity of minimizing is relevant with collapse factors.Fig. 1 is the analog to digital converter schematic diagram that a 8bit resolution has adopted foldable structure, and collapse factors is 8.Folding electric circuit generally is made up of to obtain folded signal one group of cross-linked difference input.
The folding electric circuit module that adopts in the present collapsible analog to digital converter is made up of amplifying circuit and output circuit, wherein, constitute by M identical amplifying unit parallel connection in the amplifying circuit, each amplifying unit is made of a pair of difference input transistors and a current source, as M.J.Choe, B.S.Song, and K.Bacrania, " An 8-b 100-Msample/s CMOSPipelined Folding ADC; " IEEE J.Solid-State Circuits, vol.36, pp.184-194, Feb.2001; B.Nautaand A.G W.Venes, " A 70-MS/s 100-mW 8-b CMOS Folding and Interplating A/D Converter, " IEEE J.Solid-State Circuits, vol.30, pp.1302-1308, Dec.1995.Fig. 2 is a traditional folding electric circuit, and collapse factors is 8.As shown in Figure 2, collapse factors is high more, and required current source is many more, power consumption consumption is many more, and because the cross-linked output connected mode of the general employing of folding electric circuit can be introduced bigger parasitic gate leakage capacitance on output node, thereby influence the high frequency performance of folding electric circuit.
Summary of the invention
The object of the present invention is to provide a kind of hybrid two-layer folding electric circuit that is used for high-speed low-power-consumption foldable structure analog to digital converter, to overcome deficiencies such as existing folding electric circuit current source is many, power consumption is high, parasitic gate leakage capacitance is excessive.
The folding electric circuit of the present invention's design is made up of amplifying circuit 31 and output circuit 32.Overall circuit as shown in Figure 3.
Wherein amplifying circuit comprises M two layers of identical amplifying unit (for example: 311～313), these unit amplifies the difference input voltage 3*M.These difference inputs are provided by the pre-amplification in the collapsible analog to digital converter and the output of sample holding unit, two one of inputs of this unit are the analog input signals of analog to digital converter, one is reference voltage, the input reference voltage of each unit has nothing in common with each other, their the output input of folding electric circuit just like this, the pairing analog signal input range of its range of linearity also has nothing in common with each other.
Each two layers of amplifying unit is made of three pairs of difference input transistors 41～43 and a current source 44 respectively as shown in Figure 4, and the source short circuit of every pair of difference input pipe forms the common source end, and two grids are differential input ends; Two drain terminals of difference input transistors 42 connect the common source end of difference input transistors 41 and 43 respectively, the positive output end of difference input transistors 41 links to each other with the positive output end of difference input transistors 43, relative, the negative output terminal of difference input transistors 41 links to each other with the negative output terminal of difference input transistors 43, and two layers of amplifying unit have a pair of positive negative output; Current source one end connects the common source end of difference input transistors 42, other end ground connection.Each two layers of amplifying unit is responsible for three pairs of differential input signals are amplified.Owing to have nothing in common with each other in the analog input signal zone of every pair of pairing analog to digital converter of difference input transistors, so, just can obtain 3 folding output current signals of a pair of difference at the output of amplifying circuit along with the analog input signal voltage of analog to digital converter raises gradually.Here, on the principle, to M without limits, so long as odd number gets final product.Yet, actually, considering various factors, M is that the odd number in 1～9 is advisable.
The output of M two layers of amplifying unit connects by cross-linked mode, and promptly the positive output end of the 1st unit links to each other with the negative output terminal of the 2nd unit, and the positive output end with the 3rd unit links to each other again, and the like.Relative, the negative output terminal of the 1st unit links to each other with the positive output end of the 2nd unit, and the negative output terminal with the 3rd unit links to each other again, and the like.In the amplifying circuit of folding electric circuit, have nothing in common with each other in the analog input signal zone of each two layers of pairing analog to digital converter of amplifying unit, so along with the analog input signal voltage of analog to digital converter raises gradually, just can obtain the folding output current signal of a pair of difference at the output of amplifying circuit, its folding ratio is 3*M.Output circuit is made up of two resistance 321～322, is responsible for converting current signal to voltage signal output.
Compare with the traditional folding electric circuit with identical folding ratio, owing to adopted stacked structure, the required current source number of hybrid two-layer folding electric circuit significantly reduces; Because the minimizing of receiving the difference input transistors number of output node, the parasitic gate leakage capacitance of output node will reduce greatly.
Description of drawings
Fig. 1 shows the schematic diagram of folding conversion notion.
Fig. 2 shows the circuit connection diagram of single folding electric circuit commonly used.
Fig. 3 shows the circuit connection diagram of the single folding electric circuit that has adopted the hybrid two-layer structure.
Fig. 4 has shown the circuit connection diagram of single two layers of amplifying unit in the hybrid two-layer folding electric circuit.Wherein, (a) being the circuit connection diagram of single two layers of amplifying unit, (b) is the state diagram 1 of single two layers of amplifying unit, (c) is the state diagram 2 of single two layers of amplifying unit.
Fig. 5 has shown each main node work wave in 9 folding electric circuits.Wherein, be the output signal of pre-amplification and sampling hold circuit (a), (b) be the output signal of folding electric circuit 20 and 30.
Number in the figure: the 20th, the folding electric circuit of using always, 21 and 22 are respectively amplifying circuit and the output circuit in the circuit 20,211～219 is the basic difference amplifying unit in the amplifying circuit 21,60～77 is n channel mosfet (NMOS) transistor in the amplifying circuit 21,81～89 is the current source in the amplifying circuit 21,221～222 is the resistance in the output circuit 22, the 30th, the hybrid two-layer folding electric circuit, 31 and 32 are respectively amplifying circuit and the output circuit in the circuit 30,311～313 is two layers of amplifying unit in the amplifying circuit 31,321 and 322 is the resistance in the output resistance 32,41～43 is three pairs of difference input transistors of two layers of amplifying unit 311,44 is two layers of current source in the amplifying unit 311,411 and 412 is the nmos pass transistor in the difference input transistors 41,421 and 422 is the nmos pass transistor in the difference input transistors 42, and 431 and 432 is the nmos pass transistor in the difference input transistors 43.
Embodiment
Further describe the present invention below in conjunction with accompanying drawing.
The connection layout of folding electric circuit 20 commonly used as shown in Figure 2.Among the figure most important part, such as just not providing among the circuit form of the composition figure of current source.But this does not influence the generation that helps to understand folded signal by this figure.Circuit 20 used components and parts have n channel mosfet (NMOS) transistor 60～77, current source 81～89 and resistance 221～222.Mainly contain two parts circuit, one is that 21, one of amplifying circuits are output circuits 22.Amplifying circuit 21 is made of M identical basic difference amplifying unit, is example here with M=9, that is: basic difference amplifying unit 211～219.With unit 211 is that example illustrates that its circuit connects, and unit 211 is made up of a pair of input difference transistor 60～61 and a current source 81, and the source short circuit of difference input pipe forms the common source end, and two grids are differential input ends, and grid termination difference is imported anode V
In1+ the drain terminal of NMOS pipe 60 be the negative output terminal of this element circuit 211, grid termination difference is imported anode V
In1-the drain terminal of NMOS pipe 61 be the positive output end of this element circuit 211; Current source one end connects the common source end of difference input transistors, and other end ground connection is for unit 211 provides bias current.As difference input voltage V
Inl+ and V
In1-When being in the linear zone variation, the electric current of the difference output end of unit 211 is also followed variation, works as V
In1+Equal V
In1-The time, the difference current output of unit 211 will produce a zero crossing.The electric current that the current source that all basic amplifying units 211～219 adopt provides all equates.The output of all basic amplifying units 211～219 is linked together by cross-linked mode, the positive output end of Unit 211 links to each other with the negative output terminal of Unit 212, positive output end with Unit 213 links to each other again, and the like, obtain the output end current I of amplifying circuit 21
F1Relative, the negative output terminal of Unit 211 links to each other with the positive output end of Unit 212, and the negative output terminal with Unit 213 links to each other again, and the like, obtain the output end current I of amplifying circuit 21
F2Amplifying unit 211～219 difference input separately is not overlapping to the voltage linear district, along with the gradually changing of analog input voltage, has just produced folding difference output current signal I 9 times like this
F1And I
F222 of output circuits are with folding difference output current signal I
F1And I
F2Convert voltage signal to and as the output of circuit 20.By circuit structure as can be seen, produce folded signal 9 times, need 9 identical current sources, cause the power consumption of folding electric circuit very high.And owing to all connected the drain terminal of 9 input transistors on each output node, this can increase the grid leak parasitic capacitance on the output node greatly, thereby influences the speed of folding electric circuit.
Folding electric circuit among the present invention has adopted the hybrid two-layer structure, and its circuit 30 as shown in Figure 3, and is the same with Fig. 2, has also only provided the circuit of main part.Circuit is made up of amplifying circuit 31 and output circuit 32.Amplifying circuit comprises L two layers of identical amplifying unit, is example, that is: two layers of amplifying unit 311～313 here with L=3.Because two layers of amplifying unit 311～313 circuit connect all identical, so be example with unit 311 here, shown in Fig. 4 (a), unit 311 is made of three pairs of difference input transistors 41～43 and a current source 44 respectively, the source short circuit of every pair of difference input pipe, form the common source end, two grids are differential input ends; The input of grid termination difference is to anode V
In1+The drain terminal of NMOS pipe 411 import anode V with grid termination difference
In3+The drain terminal of NMOS pipe 431 link to each other, obtain the negative output terminal electric current I of this element circuit 311
Out-The input of grid termination difference is to negative terminal V
In1-The drain terminal of NMOS pipe 412 import negative terminal Vi with grid termination difference
N3-the drain terminal of NMOS pipe 432 link to each other, obtain the positive output end electric current I of this element circuit 311
Out+The input of grid termination difference is to anode V
In2+The drain terminal of NMOS pipe 421 receive the common source end of difference input transistors 43, grid termination difference is imported negative terminal V
In2-The drain terminal of NMOS pipe 422 receive the common source end of difference input transistors 41.Current source one end connects the common source end of difference input transistors 42, other end ground connection.
As difference input voltage V
In1+And V
In1-During linear change, NMOS pipe 411 and 412 is in linear zone.At this moment, because V
In2+And V
In3+Be low level, V
In2-And V
In3-Be high level, NMOS pipe 422 is in linear conducting district, is equivalent to a conducting resistance, and NMOS pipe 421,431 and 432 all is in cut-off region, shown in Fig. 4 (b).Work as V
In1+Equal V
In1-The time, I
Out+Equal I
Out-, difference output current (I
Out+-I
Out-) produce first zero crossing.As difference input voltage V
In2+And V
In2-During linear change, NMOS pipe 421 and 422 is in linear zone.At this moment, because V
In1-And V
In3+Be low level, V
In1+And V
In3-Be high level, NMOS pipe 411 and 432 is in linear conducting district, is equivalent to conducting resistance, and NMOS pipe 412,431 all is in cut-off region, shown in Fig. 4 (c).Work as V
In2+Equal V
In2-The time, I
Out+Equal I
Out-, the difference output current produces second zero crossing.As difference input voltage V
In3+And V
In3-During linear change, NMOS pipe 431 and 432 is in linear zone, similarly, works as V
In3+Equal V
In3-, the 3rd zero crossing of difference output current produced.
All basic amplifying units 311～313 adopt identical current source.The output of all basic amplifying units 311～313 is linked together by cross-linked mode, the positive output end of Unit 311 links to each other with the negative output terminal of Unit 312, positive output end with Unit 313 links to each other again, and the like, obtain the output end current I of amplifying circuit 31
F1Relative, the negative output terminal of Unit 311 links to each other with the positive output end of Unit 312, and the negative output terminal with Unit 312 links to each other again, and the like, obtain the output end current I of amplifying circuit 31
F2
In circuit 30, the difference input separately of two floor amplifying unit 311～313 is not overlapping to the voltage linear district, along with the gradually changing of analog input voltage, has just produced folding 9 folded signal I of difference output like this
F1And I
F2Output circuit is made up of two resistance 321～322, is responsible for converting current signal to voltage signal output.Fig. 5 is each main node work wave in circuit 20 and 30, the V shown in the figure
Ref1～V
Ref9Amplify and the external reference voltage of sampling hold circuit for pre-, analog input signal is the input signal of analog to digital converter.Fig. 5 (a) is pre-the amplification and the output signal that adopts holding circuit, is the input signal of folding electric circuit 20 and 30; Fig. 5 (b) is the output signal of folding electric circuit 20 and 30.
Compare with the folding electric circuit of traditional 9 folding ratios, the required current source number of hybrid two-layer folding electric circuit has reduced 2/3; Because the minimizing of receiving the difference input transistors number of output node, the parasitic gate leakage capacitance of output node has reduced by 1/3.The improvement of these characteristics has very big help for the foldable structure analog to digital converter of design high-speed low-power-consumption, and two layers structure also is suitable for the application of low supply voltage.
Claims (2)
1, a kind of high-speed low-power-consumption structural module transducer hybrid two-layer folding electric circuit is characterized in that being made up of amplifying circuit and output circuit, and wherein, amplifying circuit comprises M two layers of identical amplifying unit, and M is the odd number among the 1-9; These unit amplify the difference input voltage 3 * M, and these difference inputs are provided by the pre-amplification in the collapsible transducer and the output of sample holding unit; Each two layers of amplifying unit is made of three pairs of difference input transistors (41)～(43) and a current source (44) respectively, and the source short circuit of every pair of difference input pipe forms the common source end, and two grids are differential input ends; Two drain terminals of difference input transistors (42) connect the common source end of difference input transistors (41) and (43) respectively, the positive output end of difference input transistors (41) links to each other with the positive output end of difference input transistors (43), relative, the negative output terminal of difference input transistors (41) links to each other with the negative output terminal of difference input transistors (43), and two layers of amplifying unit have a pair of positive negative output; Current source one end connects the common source end of difference input transistors (42), other end ground connection; Output circuit is made up of 2 resistance (321) and (322).
2, hybrid two-layer folding electric circuit according to claim 1, the output that it is characterized in that described M two layers of amplifying unit connects by cross-linked mode, promptly the positive output end of the 1st unit links to each other with the negative output terminal of the 2nd unit, positive output end with the 3rd unit links to each other again, and the like; Relative, the negative output terminal of the 1st unit links to each other with the positive output end of the 2nd unit, and the negative output terminal with the 3rd unit links to each other again, and the like.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200510111061 CN1777036A (en) | 2005-12-01 | 2005-12-01 | Hybrid two-layer folding circuit for high speed low-power consumption folding structure A/D converter |
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| CN 200510111061 CN1777036A (en) | 2005-12-01 | 2005-12-01 | Hybrid two-layer folding circuit for high speed low-power consumption folding structure A/D converter |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055474A (en) * | 2009-10-28 | 2011-05-11 | 北京大学 | Folding device and folding and interpolating A/D converter |
| CN102109360B (en) * | 2009-12-24 | 2012-07-11 | 上海华虹Nec电子有限公司 | Signal processing circuit of linear Hall sensor |
| CN103825614B (en) * | 2014-02-12 | 2017-04-05 | 北京时代民芯科技有限公司 | A kind of high-speed low-power-consumption analog-digital converter of wideband input |
| CN107332562A (en) * | 2017-05-27 | 2017-11-07 | 烽火通信科技股份有限公司 | Signal sample circuit |
-
2005
- 2005-12-01 CN CN 200510111061 patent/CN1777036A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055474A (en) * | 2009-10-28 | 2011-05-11 | 北京大学 | Folding device and folding and interpolating A/D converter |
| CN102055474B (en) * | 2009-10-28 | 2013-06-26 | 北京大学 | Folding device and folding and interpolating A/D converter |
| CN102109360B (en) * | 2009-12-24 | 2012-07-11 | 上海华虹Nec电子有限公司 | Signal processing circuit of linear Hall sensor |
| CN103825614B (en) * | 2014-02-12 | 2017-04-05 | 北京时代民芯科技有限公司 | A kind of high-speed low-power-consumption analog-digital converter of wideband input |
| CN107332562A (en) * | 2017-05-27 | 2017-11-07 | 烽火通信科技股份有限公司 | Signal sample circuit |
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