CN108155903A - High speed and high pressure level shifting circuit applied to GaN gate drivings - Google Patents
High speed and high pressure level shifting circuit applied to GaN gate drivings Download PDFInfo
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- CN108155903A CN108155903A CN201711175450.4A CN201711175450A CN108155903A CN 108155903 A CN108155903 A CN 108155903A CN 201711175450 A CN201711175450 A CN 201711175450A CN 108155903 A CN108155903 A CN 108155903A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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Abstract
The invention discloses a kind of high speed and high pressure level shifting circuit applied to GaN gate drivings, including：Input circuit, the first PMOS transistor, level shifting circuit and shaping circuit；Input circuit first end is connected to level shifting circuit first end in first node, second end is connected to the drain electrode of the first PMOS transistor in second node, the grid of first PMOS transistor is connected to the first power cord, the source electrode of first PMOS transistor is connected to level shifting circuit second end in third node, level shifting circuit is connected to second source line, level shifting circuit second end is connected to the input terminal of shaping circuit in third node, shaping circuit is connected to the first power cord and second source line, its output terminal is connected to the first end of power device in fourth node, power device is connected to the first power cord and third power cord.
Description
Technical field
The invention belongs to IC design fields, high more particularly, to a kind of high speed applied to GaN gate drivings
Voltage level conversion circuit.
Background technology
Conventional electric power electronic power components based on silicon materials its theoretical limit of Step wise approximation, it is difficult to meet electric power
The growth requirement of electronic technology high frequency and high power density.Compared with traditional Si devices, GaN device presents it and is leading
The advantage being powered on resistance and gate charge can make power converter realize smaller volume, higher frequency and higher efficiency, so as to
It has broad application prospects in the fields such as automobile, communication, industry.The raising of switching frequency, can not only effectively reduce and be
The size of capacitance, inductance and transformer in system circuit, but also can inhibit to interfere, reduce ripple, improve power-supply system unit
Gain bandwidth is so as to improve its dynamic response performance.And the gate driving circuit of high speed is used to drive GaN power devices so that whole
A power converter reaches high efficiency and reduces circuit area, saves cost.
Fig. 1 shows typical GaN half-bridge drive circuits block diagram according to prior art.As shown in Figure 1, typical GaN
Half-bridge drive circuit is divided into high-end and low side two paths, by the way of Bootstrap, two-way low pressure input channel.In low side
During power GaN device is connected, switching node (SW) is pulled down to ground, and VDD is filled by bootstrap diode to bootstrap capacitor at this time
Electricity is so that the nearly VDD of bootstrap capacitor both end voltage differential.Instantly when end pipe is closed, high-end input signal opens high-end tubes, switch
Node voltage rises to VIN, i.e. VSW rises to VIN.Since bootstrap capacitor both end voltage is constant, therefore bootstrap voltage mode rail HB is booted
To VSW+VDD.High side circuitry remains VHB-VSW ≈ VDD.And HB is by bootstrap capacitor when being booted, the cathode of bootstrap diode
Voltage is high potential, higher than anode voltage VDD, therefore the reverse-biased cut-off of bootstrap diode.
Due to the Bootstrap feature of GaN drivings, therefore in order to control being switched on and off for high-end GaN power devices, need
Low pressure input control signal is converted into the level signal of high pressure floating by level translator.Level shifting circuit is gate driving electricity
The low-voltage control signal of input is converted to high pressure floating control signal, after cascode buffer by the key component in road
Control the conducting and shutdown of power device.
Most of level shifting circuit is applied in low-voltage circuit and to convert over the ground, such as by low voltage input signal
High low potential is respectively that be converted to the high low potential of output signal be respectively 1.8V and 0V to the periodic square wave signal of 1.2V and 0V
Periodic square wave signal.Such level shifting circuit type is more, but it is most of be not suitable for high pressure float level conversion circuit,
And transmission delay is larger.And high pressure float level conversion circuit be by whole " migration " to the high voltage rail of low voltage input signal, and
It not converts over the ground, the periodic square wave signal that low voltage input signal low and high level is respectively 5V and 0V is such as converted into output letter
Number high low potential is respectively the periodic square wave signal of 35V and 30V." floating " refers to that the low potential of level conversion output is not solid
Fixed ground potential but as external switch node floats the high-voltage potential of variation.And applied to the high pressure floating electricity of half-bridge driven
Flat conversion circuit is relatively fewer, and transmission delay is larger, therefore limits the application of the driving circuit at place, especially works as circumferential work
Rate device often applies power converter under HF switch frequency to play the advantage of high speed GaN when using GaN, because
This switch periods time is smaller, needs minimum level conversion time, no it will cause switching logic mistakes.And level conversion
Time is smaller, it is meant that and the switching frequency of power converter " can with " is higher, so that peripheral passive device size reduces, face
Product reduces, cost reduction.
For traditional transistor gate driving circuit mainly for Si MOS power tubes or IGBT, usual such power device should
Frequency environment is not high (hundreds of kHz switching frequencies), therefore transmission delay is larger.And when selecting GaN power devices, usually use
Under HF switch frequency (more than MHz), after especially switching frequency reaches 10MHz, conventional gate drives larger delay
It is excessive that (tens nanoseconds) will account for switch periods ratio, even results in logic error, and then limit switching frequency not increasing.
It is premise that gate driving can be operated in HF switch frequency that transmission delay, which was decreased within several nanoseconds,.And by
In high-end access compare with low side access more than level translator, therefore usually the delay of high-end access is more than low side access
Delay, need in low side access increase delay matching circuit so that the delay of height access is equal.In other words, driving electricity
The delay on road is determined by the delay of high-end access, and delay of the delay of high-end access depending on level translator, therefore is subtracted
Small level translator delay is to solve the overriding challenge of GaN driving circuits high frequency application.The level that traditional high pressure is floated turns
Parallel operation has two kinds of cross coupling structure and current-mirror structure, respectively as shown in Figure 2 and Figure 4.
Fig. 2 shows cross coupling structure high voltage level conversion circuits according to prior art.As shown in Fig. 2, M1 and M2
For low pressure PMOS, cross coupling structure is used, and Mdep1And Mdep2The high pressure in circuit is undertaken for high pressure DEPMOS, while
Play the role of that high pressure and low-voltage circuit is isolated.And VSSHIt is connected to Mdep1And Mdep2Low electricity of the grid as High voltage output signal
Position, V correspondinglyDDHHigh potential for High voltage output.Mid1And Mid2For high input voltage pipe.Work as VINHeight is converted to by low potential
During level, Mid1Conducting, Mid2Shutdown, node VdIt is pulled down, and then the grid of M2 is pulled down so that M2 is connected, and pulls up VOUT, and
Due to VOUTRaising is so that M1 shutdowns pull up reduced capability, M2 is contributed to draw high V i.e. for M2 gridsOUTProcess.For
VOUTFor, due to Mid2Shutdown, therefore VOUTPull-down current be turned off, contribute to VOUTIt pulls up, so far VOUTFor high potential.When
VINWhen being converted to low level by high potential, Mid1Shutdown, Mid2Conducting, VOUTIt is pulled down to low potential, the grid of M1 conducting pull-up M2
Voltage so that M2 is turned off, and for VOUTFor node, pull-up current reduction contributes to VOUTThe process being pulled down, so far VOUTQuilt
It is pulled down to low potential.Fig. 3 shows cross coupling structure high voltage level conversion circuit waveform diagram according to prior art.Such as
Shown in Fig. 3, the high-voltage level shifters of traditional cross coupling structure are due to high-impedance node VdSo that big saturation current
(Id) long period cannot be maintained.And the I reduceddIt can cause that M1/M2 " latch " is slack-off again, lead to VOUTIn the mistake of level conversion
Transmission delay is larger in journey.
Fig. 4 shows current-mirror structure high voltage level conversion circuit according to prior art.As shown in figure 4, M1 and M2 are
Low pressure PMOS forms current-mirror structure, Mid1And Mid2For high input voltage pipe, MdepThe high pressure in circuit is undertaken for DEPMOS, together
When also function to isolation high pressure and low-voltage circuit effect.And VSSHIt is connected to MdepLow potential of the grid as High voltage output signal,
V correspondinglyDDHHigh potential for High voltage output.Work as VINWhen being converted to high level by low spot position, Mid1Conducting, Mid2Shutdown, section
Point VdIt is pulled down, due to Mid1It is both turned on M1, therefore the saturation current I that left branch is largerdRight branch is mirrored onto as VOUT's
Pull-up current, and due to Mid2Therefore pull-down current is zero, V for shutdownOUTBy fast pull-up to high potential.And work as VINTurned by high potential
When being changed to low level, Mid1Shutdown, Mid2Conducting, therefore left branch disconnects no current, therefore current mirror does not have image current, VOUTQuilt
Low potential is pulled down to, without pull-up current.Traditional current-mirror structure high-voltage level shifters transmission delay is smaller, but power consumption compared with
Greatly.Fig. 5 shows current-mirror structure high voltage level conversion circuit waveform diagram according to prior art.As shown in figure 5, electric current
The level translator of mirror structure is due to low-impedance node Vd, big saturation current IdOutput node can be mirrored to, increases VOUT's
Slew rate.However, unnecessary current drain over the ground is had, such as work as V after level conversion is completedINWhen keeping high level,
Constant conduction is understood in the left side to ground leg, and can continue consumption have IdTo earth-current, cause larger current power dissipation.
Therefore, it is necessary to provide a kind of level shifting circuit structure of novel high speed high pressure, reduce transmission delay, and simultaneously
Keep relatively low current power dissipation over the ground.
Invention content
The purpose of the present invention is reduce level shifting circuit transmission delay so that the integrated circuit peripheral device of power converter
Part size reduces, and keeps relatively low current power dissipation over the ground simultaneously.
According to an aspect of the invention, it is proposed that a kind of high speed and high pressure level shifting circuit applied to GaN gate drivings,
Including：Input circuit, the first PMOS transistor, level shifting circuit and shaping circuit；
The input circuit first end is connected to the level shifting circuit first end in first node, and second end is second
Node is connected to the drain electrode of the first PMOS transistor, and the grid of first PMOS transistor is connected to first power cord,
The source electrode of first PMOS transistor is connected to the level shifting circuit second end, the level conversion electricity in third node
Road is connected to second source line, and the level shifting circuit second end is connected to the defeated of the shaping circuit in the third node
Enter end, the shaping circuit is connected to the first power cord and second source line, and output terminal is connected to the work(in fourth node
The first end of rate device, the power device are connected to the first power cord and third power cord.
Preferably, the input circuit includes：
First NMOS transistor, the grid of first NMOS transistor are used to receive input signal, the first NMOS
The drain electrode of transistor is connected to the first node；
Second NMOS transistor, the grid of second NMOS transistor are used to receive the input signal of reverse phase, institute
The drain electrode for stating the second NMOS transistor is connected to the drain electrode of first PMOS transistor, the source electrode of second NMOS transistor
It is connected to the ground current potential；
Third NMOS transistor, the grid of the third NMOS transistor are used to receive the input signal of reverse phase, institute
The drain electrode for stating third NMOS transistor is connected to the source electrode of first NMOS transistor, the source electrode of the third NMOS transistor
It is connected to the ground current potential；
Capacitance, described capacitance one end are connected to the source electrode of first NMOS transistor, and the other end is connected to the ground current potential.
Preferably, the input circuit further includes Zener diode, and the anode of the Zener diode is connected to described
One node, cathode are connected to second source line.
Preferably, the input circuit includes：
First NMOS transistor, the grid of first NMOS transistor are used to receive input signal, the first NMOS
The source electrode of transistor is connected to the ground current potential；
Second NMOS transistor, the grid of second NMOS transistor are used to receive the input signal of reverse phase, institute
The source electrode for stating the second NMOS transistor is connected to the ground current potential；
Third NMOS transistor, the grid of the third NMOS transistor are connected to the 4th power cord, the 3rd NMOS
The source electrode of transistor is connected to the drain electrode of first NMOS transistor；
4th NMOS transistor, the grid of the 4th NMOS transistor are connected to the 4th power cord, the 4th NMOS
The source electrode of transistor is connected to the drain electrode of second NMOS transistor, and the drain electrode of the 4th NMOS transistor is connected to described
The drain electrode of first PMOS transistor；
8th PMOS transistor, the grid of the 8th PMOS transistor are connected to the first power cord, the 8th PMOS
The drain electrode of transistor is connected to the drain electrode of the third NMOS transistor, and the source electrode of the 8th PMOS transistor is connected to described
First node.
Preferably, the level shifting circuit includes cross-couplings module and pull-up modules, the cross-couplings module
For level conversion, the pull-up modules are used to accelerate level conversion process.
Preferably, the cross-couplings module includes：
Second PMOS transistor, the source terminal of second PMOS transistor are connected to second source line, and described second
PMOS transistor drain electrode end is connected to the third node, and the gate terminal of second PMOS transistor is connected to the first segment
Point；
Third PMOS transistor, the source terminal of the third PMOS transistor are connected to second source line, and the third
PMOS transistor drain electrode end is connected to the first node, and the gate terminal of the third PMOS transistor is connected to the third section
Point.
Preferably, the pull-up modules include：
4th PMOS transistor, the gate terminal and drain electrode end of the 4th PMOS transistor are connected to the first node
Place；
5th PMOS transistor, the source terminal of the 5th PMOS transistor are connected to second source line, and the described 5th
The gate terminal of PMOS transistor is connected at the third node, the drain electrode end and the described 4th of the 5th PMOS transistor
The source terminal of PMOS transistor is connected；
6th PMOS transistor, the gate terminal and drain electrode end of the 6th PMOS transistor are connected to the third node
Place；
7th PMOS transistor, the source terminal of the 7th PMOS transistor are connected to second source line, and the described 7th
The gate terminal of PMOS transistor is connected at the first node, the drain electrode end and the described 6th of the 7th PMOS transistor
The source terminal of PMOS transistor is connected.
Preferably, drain electrode end of the first end of the input circuit for first NMOS transistor, the input circuit
Second end be second NMOS transistor drain electrode end, the level shifting circuit first end be the 3rd PMOS crystal
The drain electrode end of pipe, the level shifting circuit second end are the drain electrode end of second PMOS transistor.
Preferably, source terminal of the first end of the input circuit for the 8th PMOS transistor, the input circuit
Second end be the 4th NMOS transistor drain electrode end, the level shifting circuit first end be the 3rd PMOS crystal
The drain electrode end of pipe, the level shifting circuit second end are the drain electrode end of second PMOS transistor.
Preferably, first power cord is the low potential of current potential conversion, and the second source line is the height of current potential conversion
Current potential, the third power cord are the high input voltage of power converter, and the 4th power cord is bias voltage.
The beneficial effects of the present invention are：High speed and high pressure level shifting circuit provided by the invention has the transmission of sub-ns
Delay, can realize high speed, high frequency may operate under the switching frequency of 30MHz so that the whole electricity of power converter
Road peripheral components size reduces, so that area reduces, saves cost, while also keep relatively low current power dissipation over the ground.
Other features and advantages of the present invention will be described in detail in subsequent specific embodiment part.
Description of the drawings
Exemplary embodiment of the invention is described in more detail in conjunction with the accompanying drawings, it is of the invention above-mentioned and its
Its purpose, feature and advantage will be apparent, wherein, in exemplary embodiment of the invention, identical reference label
Typically represent same parts.
Fig. 1 shows typical GaN half-bridge drive circuits block diagram according to prior art.
Fig. 2 shows cross coupling structure high voltage level conversion circuits according to prior art.
Fig. 3 shows cross coupling structure high voltage level conversion circuit waveform diagram according to prior art.
Fig. 4 shows current-mirror structure high voltage level conversion circuit according to prior art.
Fig. 5 shows current-mirror structure high voltage level conversion circuit waveform diagram according to prior art.
Fig. 6 shows the high speed and high pressure level conversion electricity for being applied to GaN drivings according to first embodiment of the invention
Road.
Fig. 7 shows the simulation waveform of level shifting circuit according to first embodiment of the invention.
Fig. 8 shows the high speed and high pressure level conversion electricity for being applied to GaN drivings of second embodiment according to the present invention
Road.
Specific embodiment
The preferred embodiment of the present invention is described in more detail below.Although the following describe the preferred implementations of the present invention
Mode, however, it is to be appreciated that may be realized in various forms the present invention without should be limited by embodiments set forth herein.Phase
Instead, these embodiments are provided so that the present invention is more thorough and complete, and can be by the scope of the present invention completely
It is communicated to those skilled in the art.
Embodiment 1
Fig. 6 shows the high speed and high pressure level conversion electricity for being applied to GaN drivings according to first embodiment of the invention
Road.
As shown in fig. 6, the present invention provides a kind of high speed and high pressure level shifting circuit applied to GaN gate drivings, including：
Input circuit 601, the first PMOS transistor 602 (namely MP1 in Fig. 6), level shifting circuit 603 and shaping circuit 604；It is defeated
Enter 601 first end of circuit and be connected to 603 first end of level shifting circuit in first node NH, second end is in second node A connections
To the drain electrode of the first PMOS transistor 602, the grid of the first PMOS transistor 602 is connected to the first power cord, and the first PMOS is brilliant
The source electrode of body pipe 602 is connected to 603 second end of level shifting circuit in third node NL, and level shifting circuit 603 is connected to
Two power cords, 603 second end of level shifting circuit are connected to the input terminal of shaping circuit 604, shaping circuit in third node NL
604 are connected to the first power cord and second source line, and output terminal is connected to the first end of power device 605 in fourth node B,
Power device 605 is connected to the first power cord and third power cord.
The purpose of the present embodiment is to reduce level shifting circuit transmission delay to be less than 1ns so that the entirety of power converter
Circuit peripheral device size reduces, and keeps relatively low current power dissipation over the ground simultaneously.
Preferably, input circuit 601 includes：
For the grid of first NMOS transistor MN1, the first NMOS transistor MN1 for receiving input signal, the first NMOS is brilliant
The drain electrode of body pipe MN1 is connected to first node NH；
The grid of second NMOS transistor MN2, the second NMOS transistor MN2 is used to receiving the input signal of reverse phase, and second
The drain electrode of NMOS transistor MN2 is connected to the drain electrode of the first PMOS transistor 602, the source electrode connection of the second NMOS transistor MN2
To ground potential；
The grid of third NMOS transistor MN3, third NMOS transistor MN3 are used to receive the input signal of reverse phase, third
The drain electrode of NMOS transistor MN3 is connected to the source electrode of the first NMOS transistor MN1, the source electrode connection of third NMOS transistor MN3
To ground potential；
Capacitance C1, capacitance C1 one end are connected to the source electrode of the first NMOS transistor MN1, and the other end is connected to the ground current potential.
Preferably, input circuit 601 further includes Zener diode Z1, and the anode of Zener diode Z1 is connected to
One node NH, cathode are connected to second source line.
Specifically, diode Z1 is Zener diode, for the low potential of clamper first node NH, prevents from converting in high pressure
When by first node NH pull down it is too low, the grid source pressure voltage more than the second PMOS transistor MP2 leads to the second PMOS transistor
MP2 punctures
Preferably, level shifting circuit 603 includes cross-couplings module and pull-up modules, cross-couplings mould
Block is used for level conversion, and pull-up modules are used to accelerate level conversion process.
Preferably, cross-couplings module includes：
The source terminal of second PMOS transistor MP2, the second PMOS transistor MP2 is connected to second source line, the 2nd PMOS
Transistor MP2 drain electrode ends are connected to third node NL, and the gate terminal of the second PMOS transistor MP2 is connected to first node NH；
The source terminal of third PMOS transistor MP3, third PMOS transistor MP3 are connected to second source line, and third
PMOS transistor MP3 drain electrode ends are connected to first node NH, and the gate terminal of third PMOS transistor MP3 is connected to third node
NL。
Preferably, pull-up modules include：
The gate terminal and drain electrode end of 4th PMOS transistor MP4, the 4th PMOS transistor MP4 are connected to first node NH
Place；
The source terminal of 5th PMOS transistor MP5, the 5th PMOS transistor MP5 are connected to second source line, the 5th PMOS
The gate terminal of transistor MP5 is connected at third node NL, the drain electrode end and the 4th PMOS transistor of the 5th PMOS transistor MP5
The source terminal of MP4 is connected；
The gate terminal and drain electrode end of 6th PMOS transistor MP6, the 6th PMOS transistor MP6 are connected to third node NL
Place；
The source terminal of 7th PMOS transistor MP7, the 7th PMOS transistor MP7 are connected to second source line, the 7th PMOS
The gate terminal of transistor MP7 is connected at first node NH, the drain electrode end and the 6th PMOS transistor of the 7th PMOS transistor MP7
The source terminal of MP6 is connected.
Preferably, drain electrode end of the first end of input circuit 601 for the first NMOS transistor MN1, input circuit
601 second end is the drain electrode end of the second NMOS transistor MN2, and 603 first end of level shifting circuit is third PMOS transistor
The drain electrode end of MP3,603 second end of level shifting circuit are the drain electrode end of the second PMOS transistor MP2.
Preferably, the first power cord is the low potential VSW of current potential conversion, and second source line is the height of current potential conversion
Current potential VBOOT, third power cord is the high input voltage V of power converterDDH。
The output terminal of shaping circuit 604 is the output of level translator, controls the conducting and shutdown of power device 605
When also need by cascode buffer buf, by conducting and shutdown that power device GaN is controlled after cascode buffer buf.
The present embodiment is adopted the technical scheme that on the level translator coupled based on conventional cross, eliminates high impedance section
Put and introduce pull-up structures to accelerate the speed of level conversion, at the same introduce a capacitance C1 and switching tube MN3 come realize compared with
Low current power dissipation over the ground.
Traditional cross-couplings high-voltage level shifters remove Mdep1After high-voltage tube, high-impedance node is eliminated, and using neat
The diode Z1 that receives carrys out the low potential of clamper NH, prevents from pulling down NH when high pressure is converted too low, the grid source pressure voltage more than MP2,
MP2 is caused to puncture, while introduces the pull-up process that pull-up modules MP4-7 accelerates NH and NL respectively, and then accelerates level conversion
Process.And it adds in capacitance C1 and MN3 in the lower section of MN1 and causes in VINDuring for high level, the drop-down of left branch is to earth-current originally
Become for the charging current to capacitance C1, and MN3 is turned off at this time, is not formed to earth-current, and then reduces whole electricity over the ground
Flow power consumption.
Low voltage input signal VINLow and high level be respectively 5V, 0V.VDDLFor low-voltage power supply voltage 5V.And VDDHTurn for power
The high input voltage (~30V) of parallel operation, VSW are connected to the low potential that the grid of MP1 is converted as switching node as current potential.VDDHFor
Bootstrap voltage mode, as the high potential of high pressure conversion, and VBOOT- VSW remains that 5V is constant.When GaN is connected, VSW ≈ VDDH,
And V at this timeBOOT=VSW+5V.MN1 and MN2 is input pipe, and wherein MN1, MN2 and MP1 are undertaken for high-voltage MOS pipe in circuit
High pressure drop.VHO is the output of level translator, by conducting and pass that power device GaN is controlled after cascode buffer Buf
It is disconnected.
The level shifting circuit level shifter that the present embodiment is applied to GaN half-bridge drivens meet high speed and high pressure floating
Using.High-pressure section is undertaken using 3 high-voltage tubes (MN1, MN2 and MP1), wherein MN1 and MN2 are high pressure low-resistance MOS conducts
Input pipe reduces channel resistance, and then reduces transmission delay.The MP2 and MP3 of cross coupling structure carry out level conversion and will be floating
The grid that dynamic ground SW is connected to MP1 allows whole level shifting circuit to migrate input signal 0-5V to highest 30-35V
The conversion of high pressure float level is realized in output.Pull-up structures are made of MP4-7, accelerate pull-up process that transmission delay is less than
1ns realizes high-speed level conversion.It can be applied in GaN half-bridge drivens realize the level conversion under high frequency (30MHz) environment.
As shown in fig. 6, work as VINMN1 is connected during for high level, MN2 and MN3 shutdowns.Due to MN1 turns on pull-down NH, at this time
MP2 and MP7 conductings, two branches pull up NL simultaneously, and NL is high potential, turn off MP3, MP5, and then accelerate the drop-down of NH, and
It is connected while MN1 and MP3 and MP4, MP5 have of short duration during this, since the pull-down capability of MN1 will be much stronger than MP3 and MP5
The pull-up ability of two branches, therefore NH can be pulled down to low potential.And MP4 connects into the form of diode and also rises during this
To the effect of current limliting, pull-down capability will be weaker than to the pull-up ability of NH at this time to be further ensured that.And the conducting electric current of MN1 can be right
Capacitance C1 charges, displaced script MN1 to earth-current, and MN3 and MN2 shutdowns, therefore reduce total current power dissipation over the ground.And
Since NL is pulled to high potential, by exporting VHO high potentials after two phase inverter shapings, passing through cascode buffer Buf
GaN power devices are connected later.VSW=V at this timeDDH, and VBOOTIt is booted to VSW+5V.
Work as VINDuring for low level, MN1 shutdowns, MN2, MN3 are connected, and capacitance C1 is discharged by MN3.Due to MN2 turns on pull-down
NL is to low potential i.e. close to VSW, and MP3, MP5 conducting is so as to pull up NH to high potential, and then closes MP2, MP7, reduces NL quilts
The ability of pull-up accelerates the process of drop-down.And NL is pulled down to low potential, it is low that VHO is exported after two phase inverter shapings
Current potential is turning off GaN power devices by cascode buffer Buf.
Fig. 7 shows the simulation waveform of level shifting circuit according to first embodiment of the invention.It is illustrated in figure 7
Periodic square wave (30MHz) the signal 0-5V for inputting low pressure is converted to the high pressure of 30-35V and floated by designed level shifting circuit
Simulation waveform in dynamic Voltage rails.Conducting transmission delay is input signal VINWhen being converted by low potential to high potential 10% to electricity
10% time that circuit output VHO is converted by low potential to high potential is changed in flat turn.And delay is turned off as input signal VINBy height
Current potential to low potential convert when 90% to level shifting circuit output VHO by low potential to high potential convert 90% when
Between.Rise time is 10% to 90% time for exporting VHO in the level conversion by low potential to high potential.Fall time is
Export 90% to 10% times of the VHO in the level conversion by high potential to low potential.Therefore it can be found out by simulation waveform and led
Logical transmission delay 684ps, shutdown transmission delay 800ps.Rise time 241ps, fall time 266ps.Averagely to earth-current
37.01uA (to the average value of earth-current in a cycle).The high speed and high pressure level conversion of sub-ns transmission delays is realized, together
When ensure relatively low current power dissipation.Output signal is being used to control high-end GaN power tubes after Buffer.
High speed and high pressure level shifting circuit provided in this embodiment has the transmission delay of sub-ns, can realize at a high speed
Change, high frequency may operate under the switching frequency of 30MHz so that the integrated circuit peripheral components size of power converter subtracts
It is small, so that area reduces, cost is saved, while also keep relatively low current power dissipation over the ground.
Embodiment 2
Fig. 8 shows the high speed and high pressure level conversion electricity for being applied to GaN drivings of second embodiment according to the present invention
Road.
As shown in figure 8, the present invention provides a kind of high speed and high pressure level shifting circuit 803 applied to GaN gate drivings, packet
It includes：Input circuit 801, the first PMOS transistor 802 (namely MP1 in Fig. 8), level shifting circuit 803 and shaping circuit
804；801 first end of input circuit is connected to 803 first end of level shifting circuit in first node NH, and second end is in first node
A is connected to the drain electrode of the first PMOS transistor 802, and the grid of the first PMOS transistor 802 is connected to the first power cord, and first
The source electrode of PMOS transistor 802 is connected to 803 second end of level shifting circuit in third node NL, and level shifting circuit 803 connects
Second source line is connected to, 803 second end of level shifting circuit is connected to the input terminal of shaping circuit 804 in third node NL, whole
Shape circuit 804 is connected to the first power cord and second source line, and output terminal is connected to power device 805 in fourth node B
First end, power device 805 are connected to the first power cord and third power cord.
Preferably, input circuit 801 includes：
For the grid of first NMOS transistor MN1, the first NMOS transistor MN1 for receiving input signal, the first NMOS is brilliant
The source electrode of body pipe MN1 is connected to the ground current potential；
The grid of second NMOS transistor MN2, the second NMOS transistor MN2 is used to receiving the input signal of reverse phase, and second
The source electrode of NMOS transistor MN2 is connected to the ground current potential；
The grid of third NMOS transistor MN3, third NMOS transistor MN3 are connected to the 4th power cord, and the 3rd NMOS is brilliant
The source electrode of body pipe MN3 is connected to the drain electrode of the first NMOS transistor MN1；
The grid of 4th NMOS transistor MN4, the 4th NMOS transistor MN4 are connected to the 4th power cord, and the 4th NMOS is brilliant
The source electrode of body pipe MN4 is connected to the drain electrode of the second NMOS transistor MN2, and the drain electrode of the 4th NMOS transistor MN4 is connected to first
The drain electrode of PMOS transistor 802；
The grid of 8th PMOS transistor MP8, the 8th PMOS transistor MP8 are connected to the first power cord, and the 8th PMOS is brilliant
The drain electrode of body pipe MP8 is connected to the drain electrode of third NMOS transistor MN3, and the source electrode of the 8th PMOS transistor MP8 is connected to first
Node NH.
Preferably, level shifting circuit 803 includes cross-couplings module and pull-up modules, cross-couplings mould
Block is used for level conversion, and pull-up modules are used to accelerate level conversion process.
Preferably, cross-couplings module includes：
The source terminal of second PMOS transistor MP2, the second PMOS transistor MP2 is connected to second source line, the 2nd PMOS
Transistor MP2 drain electrode ends are connected to third node NL, and the gate terminal of the second PMOS transistor MP2 is connected to first node NH；
The source terminal of third PMOS transistor MP3, third PMOS transistor MP3 are connected to second source line, and third
PMOS transistor MP3 drain electrode ends are connected to first node NH, and the gate terminal of third PMOS transistor MP3 is connected to third node
NL。
Preferably, pull-up modules include：
The gate terminal and drain electrode end of 4th PMOS transistor MP4, the 4th PMOS transistor MP4 are connected to first node NH
Place；
The source terminal of 5th PMOS transistor MP5, the 5th PMOS transistor MP5 are connected to second source line, the 5th PMOS
The gate terminal of transistor MP5 is connected at third node NL, the drain electrode end and the 4th PMOS transistor of the 5th PMOS transistor MP5
The source terminal of MP4 is connected；
The gate terminal and drain electrode end of 6th PMOS transistor MP6, the 6th PMOS transistor MP6 are connected to third node NL
Place；
The source terminal of 7th PMOS transistor MP7, the 7th PMOS transistor MP7 are connected to second source line, the 7th PMOS
The gate terminal of transistor MP7 is connected at first node NH, the drain electrode end and the 6th PMOS transistor of the 7th PMOS transistor MP7
The source terminal of MP6 is connected.
Preferably, source terminal of the first end of input circuit 801 for the 8th PMOS transistor MP8, input circuit
Drain electrode end of 801 second end for the 4th NMOS transistor MN4,803 first end third PMOS transistor MP3 of level shifting circuit
Drain electrode end, 803 second end of level shifting circuit be the second PMOS transistor MP2 drain electrode end.
Preferably, the first power cord is the low potential VSW of current potential conversion, and second source line is the height of current potential conversion
Current potential VBOOT, third power cord is the high input voltage V of power converterDDH, the 4th power cord is bias voltage VBIAS。
The output terminal of shaping circuit 804 is the output of level translator, controls the conducting and shutdown of power device 805
When also need by cascode buffer buf, by conducting and shutdown that power device GaN is controlled after cascode buffer buf.
As shown in figure 8, from circuit structure, capacitance C1 and MN3 in Fig. 6 are eliminated, in fig. 8 by high input voltage
Pipe MN1 and MN2 change the quick processing for making low pressure metal-oxide-semiconductor to realize signal, increase MN3 and MN4 high-pressure MOSs and provide more than 30V
The effect of isolation partial pressure, the grid of MN3 and MN4 are by bias voltage VBIAS(5V) is provided, and identical with MP1 in the addition of left branch
High pressure DEPMOS-MP2, VSSHThe grid of MP2 is connected to, low potential when being pulled down as NH prevents NH in downdraw process by mistake
The drop-down of degree and the source and drain pressure voltage of grid source pressure voltage or MP4 more than MP3, it is similary to realize isolation partial pressure effect, relatively by
In the effect of MP2, Zener diode Z1 can be removed.Technical solution shown in Fig. 8, not as good as in embodiment 1 on transmission delay
Scheme is small, but can still realize relatively low transmission delay and relatively low current power dissipation.
High speed and high pressure level shifting circuit provided in this embodiment has the transmission delay of sub-ns, can realize at a high speed
Change, high frequency may operate under the switching frequency of 30MHz so that the integrated circuit peripheral components size of power converter subtracts
It is small, so that area reduces, cost is saved, while also keep relatively low current power dissipation over the ground.
It will be understood by those skilled in the art that above to the purpose of the description of the embodiment of the present invention only for illustratively saying
The advantageous effect of bright the embodiment of the present invention is not intended to limit embodiments of the invention to given any example.
Various embodiments of the present invention are described above, above description is exemplary, and non-exclusive, and
It is not limited to disclosed each embodiment.In the case of without departing from the scope and spirit of illustrated each embodiment, for this skill
Many modifications and changes will be apparent from for the those of ordinary skill in art field.
Claims (10)
1. a kind of high speed and high pressure level shifting circuit applied to GaN gate drivings, which is characterized in that including：Input circuit,
One PMOS transistor, level shifting circuit and shaping circuit；
The input circuit first end is connected to the level shifting circuit first end in first node, and second end is in second node
The drain electrode of the first PMOS transistor is connected to, the grid of first PMOS transistor is connected to first power cord, described
The source electrode of first PMOS transistor is connected to the level shifting circuit second end in third node, and the level shifting circuit connects
Second source line is connected to, the level shifting circuit second end is connected to the input of the shaping circuit in the third node
End, the shaping circuit are connected to the first power cord and second source line, and output terminal is connected to the power in fourth node
The first end of device, the power device are connected to the first power cord and third power cord.
2. the high speed and high pressure level shifting circuit according to claim 1 applied to GaN gate drivings, wherein, it is described defeated
Enter circuit to include：
First NMOS transistor, the grid of first NMOS transistor are used to receive input signal, the first NMOS crystal
The drain electrode of pipe is connected to the first node；
Second NMOS transistor, the grid of second NMOS transistor are used to receive the input signal of reverse phase, and described the
The drain electrode of bi-NMOS transistor is connected to the drain electrode of first PMOS transistor, the source electrode connection of second NMOS transistor
To ground potential；
Third NMOS transistor, the grid of the third NMOS transistor are used to receive the input signal of reverse phase, and described the
The drain electrode of three NMOS transistors is connected to the source electrode of first NMOS transistor, the source electrode connection of the third NMOS transistor
To ground potential；
Capacitance, described capacitance one end are connected to the source electrode of first NMOS transistor, and the other end is connected to the ground current potential.
3. the high speed and high pressure level shifting circuit according to claim 2 applied to GaN gate drivings, wherein, it is described defeated
Enter circuit and further include Zener diode, the anode of the Zener diode is connected to the first node, and cathode is connected to
Two power cords.
4. the high speed and high pressure level shifting circuit according to claim 1 applied to GaN gate drivings, wherein, it is described defeated
Enter circuit to include：
First NMOS transistor, the grid of first NMOS transistor are used to receive input signal, the first NMOS crystal
The source electrode of pipe is connected to the ground current potential；
Second NMOS transistor, the grid of second NMOS transistor are used to receive the input signal of reverse phase, and described the
The source electrode of bi-NMOS transistor is connected to the ground current potential；
Third NMOS transistor, the grid of the third NMOS transistor are connected to the 4th power cord, the 3rd NMOS crystal
The source electrode of pipe is connected to the drain electrode of first NMOS transistor；
4th NMOS transistor, the grid of the 4th NMOS transistor are connected to the 4th power cord, the 4th NMOS crystal
The source electrode of pipe is connected to the drain electrode of second NMOS transistor, and the drain electrode of the 4th NMOS transistor is connected to described first
The drain electrode of PMOS transistor；
8th PMOS transistor, the grid of the 8th PMOS transistor are connected to the first power cord, the 8th PMOS crystal
The drain electrode of pipe is connected to the drain electrode of the third NMOS transistor, and the source electrode of the 8th PMOS transistor is connected to described first
Node.
5. the high speed and high pressure level shifting circuit according to claim 1 applied to GaN gate drivings, wherein, the electricity
Flat conversion circuit includes cross-couplings module and pull-up modules, and the cross-couplings module is used for level conversion, described
Pull-up modules are used to accelerate level conversion process.
6. the high speed and high pressure level shifting circuit according to claim 5 applied to GaN gate drivings, wherein, the friendship
Fork coupling module includes：
Second PMOS transistor, the source terminal of second PMOS transistor are connected to second source line, and the 2nd PMOS is brilliant
Body pipe drain electrode end is connected to the third node, and the gate terminal of second PMOS transistor is connected to the first node；
Third PMOS transistor, the source terminal of the third PMOS transistor are connected to second source line, and the 3rd PMOS
Transistor drain end is connected to the first node, and the gate terminal of the third PMOS transistor is connected to the third node.
7. the high speed and high pressure level shifting circuit according to claim 5 applied to GaN gate drivings, wherein, it is described
Pull-up modules include：
4th PMOS transistor, the gate terminal and drain electrode end of the 4th PMOS transistor are connected at the first node；
5th PMOS transistor, the source terminal of the 5th PMOS transistor are connected to second source line, and the 5th PMOS is brilliant
The gate terminal of body pipe is connected at the third node, drain electrode end and the 4th PMOS crystal of the 5th PMOS transistor
The source terminal of pipe is connected；
6th PMOS transistor, the gate terminal and drain electrode end of the 6th PMOS transistor are connected at the third node；
7th PMOS transistor, the source terminal of the 7th PMOS transistor are connected to second source line, and the 7th PMOS is brilliant
The gate terminal of body pipe is connected at the first node, drain electrode end and the 6th PMOS crystal of the 7th PMOS transistor
The source terminal of pipe is connected.
8. the high speed and high pressure level shifting circuit according to claim 2 applied to GaN gate drivings, wherein, it is described defeated
The first end for entering circuit is the drain electrode end of first NMOS transistor, and the second end of the input circuit is the 2nd NMOS
The drain electrode end of transistor, the level shifting circuit first end are the drain electrode end of the third PMOS transistor, and the level turns
Change the drain electrode end that circuit second end is second PMOS transistor.
9. the high speed and high pressure level shifting circuit according to claim 4 applied to GaN gate drivings, wherein, it is described defeated
The first end for entering circuit is the source terminal of the 8th PMOS transistor, and the second end of the input circuit is the 4th NMOS
The drain electrode end of transistor, the level shifting circuit first end are the drain electrode end of the third PMOS transistor, and the level turns
Change the drain electrode end that circuit second end is second PMOS transistor.
10. the high speed and high pressure level shifting circuit according to claim 4 applied to GaN gate drivings, wherein, described
One power cord is the low potential of current potential conversion, and the second source line is the high potential of current potential conversion, and the third power cord is
The high input voltage of power converter, the 4th power cord are bias voltage.
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| CN201711175450.4A CN108155903B (en) | 2017-11-22 | 2017-11-22 | High-speed high-voltage level conversion circuit applied to GaN grid drive |
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|---|---|---|---|
| CN201711175450.4A CN108155903B (en) | 2017-11-22 | 2017-11-22 | High-speed high-voltage level conversion circuit applied to GaN grid drive |
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| CN108155903A true CN108155903A (en) | 2018-06-12 |
| CN108155903B CN108155903B (en) | 2020-10-09 |
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| CN109495095A (en) * | 2018-11-27 | 2019-03-19 | 黄山市祁门新飞电子科技发展有限公司 | Enhanced GaN power device gate drive circuit with defencive function |
| CN109672439A (en) * | 2019-01-17 | 2019-04-23 | 南京观海微电子有限公司 | Pressure-resistant level shifting circuit |
| CN110545096A (en) * | 2019-09-02 | 2019-12-06 | 成都锐成芯微科技股份有限公司 | Quick start circuit |
| CN112072900A (en) * | 2020-08-25 | 2020-12-11 | 苏州纳芯微电子股份有限公司 | Drive circuit of drive chip |
| CN112491408A (en) * | 2019-09-11 | 2021-03-12 | 成都锐成芯微科技股份有限公司 | Level conversion circuit |
| CN112671391A (en) * | 2020-12-21 | 2021-04-16 | 海光信息技术股份有限公司 | Level conversion circuit |
| CN113193865A (en) * | 2021-05-07 | 2021-07-30 | 电子科技大学 | Level shift circuit suitable for GaN half-bridge grid drive |
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| WO2023035513A1 (en) * | 2021-09-07 | 2023-03-16 | 上海集成电路研发中心有限公司 | Level conversion circuit and chip |
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| CN113193865A (en) * | 2021-05-07 | 2021-07-30 | 电子科技大学 | Level shift circuit suitable for GaN half-bridge grid drive |
| CN113193865B (en) * | 2021-05-07 | 2022-08-26 | 电子科技大学 | Level shift circuit suitable for GaN half-bridge grid drive |
| EP4113587A1 (en) * | 2021-07-02 | 2023-01-04 | Huawei Technologies Co., Ltd. | Drive circuit of bridge arm switching transistor, drive circuit, and power converter |
| CN113746469A (en) * | 2021-07-21 | 2021-12-03 | 广东美的白色家电技术创新中心有限公司 | Level shift circuit, power device and electrical equipment |
| WO2023035513A1 (en) * | 2021-09-07 | 2023-03-16 | 上海集成电路研发中心有限公司 | Level conversion circuit and chip |
| CN117254682A (en) * | 2023-11-20 | 2023-12-19 | 成都芯翼科技有限公司 | Anti-interference voltage conversion circuit |
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