CN102637450A - Address decoder of current sharing type memory - Google Patents
Address decoder of current sharing type memory Download PDFInfo
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- CN102637450A CN102637450A CN2012101099994A CN201210109999A CN102637450A CN 102637450 A CN102637450 A CN 102637450A CN 2012101099994 A CN2012101099994 A CN 2012101099994A CN 201210109999 A CN201210109999 A CN 201210109999A CN 102637450 A CN102637450 A CN 102637450A
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- electric current
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- 239000003990 capacitor Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005039 memory span Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Abstract
The invention discloses an address decoder of a current sharing type memory, which comprises a plurality of address decoding circuits with current sharing ports, wherein the current sharing ports of the address decoding circuits are connected together to realize sharing of driving current so as to increase the driving capability of the address decoder. The address decoding circuit is composed of an address decoding unit and a driving unit, wherein the address decoding unit is used for decoding the address of the memory and outputting a differential decoding signal; the driving unit adopts an active pull-down circuit, amplifies the decoding signal and outputs a single-ended driving signal, provides pull-down current for driving an equivalent capacitor formed by the storage array, and provides a current sharing port. The invention has the advantages that the driving capability of the decoding circuit is enhanced by adopting the active pull-down circuit, and the current sharing port is provided, so that the invention has the characteristics of simple circuit structure, stable circuit, low power consumption, high working speed, strong driving capability and the like.
Description
Technical field
The present invention relates to the integrated circuit memory design field, the address decoder of the shared storer of particularly a kind of electric current.
Background technology
Semiconductor memory generally is made up of address decoder, storage array and sense amplifier.Address decoder is made up of a plurality of address decoding circuitries, for the storer of N bit address, needs 2
NIndividual address decoding circuitry.Along with the increase of memory span, storage array is increasing.Storage array is for address decoding circuitry, and equivalence is an electric capacity.Along with the increase of storage array, equivalent capacity also increases gradually.Address decoding circuitry, the general employing penetrated a grade follower driving storage array, and be as shown in Figure 1.Yet penetrate grade follower when driving load capacitance, have serious problems.Along with the increase of load capacitance, penetrating grade negative edge of follower signal output waveform sharply increases.Owing to penetrate a grade follower working current and fix, slow to the load capacitance velocity of discharge, its output signal is obviously long than the rise time fall time.Load capacitance is big more, the rise time and fall time difference big more.Rise time and fall time are different, reduce the operating rate of circuit greatly.Increasing the working current of penetrating grade follower can reduce fall time, the difference that reduces rise time and fall time, but power consumption also increases greatly.
Summary of the invention
The technical matters that (one) will solve
In view of this; Fundamental purpose of the present invention is to provide the address decoder of the shared storer of electric current of a kind of high speed, low-power consumption; Can drive jumbo memory array; Solve the bottleneck of its operating rate much larger than the rise time fall time in order to solve traditional address decoding circuitry its signal when driving the high capacity storage array.
(2) technical scheme
In order to achieve the above object; The invention provides the address decoder of the shared storer of a kind of electric current; This address decoder comprises a plurality of address decoding circuitries that have the electric current shared port; The electric current shared port of each address decoding circuitry links together, and realizes sharing drive current, to increase the driving force of address decoder.
In the such scheme, the said address decoding circuitry that has the electric current shared port comprises address decoder unit and driver element, and wherein the address decoder unit is used for output differential decoding signal behind the decoded memory address; Driver element is used for this differential decoding signal is amplified with the increase driving force, and the equivalent capacity that provides pull-down current to constitute in order to storage array in the driving storer, and the electric current shared port is provided.
In the such scheme, there is multiple way of realization said address decoder unit, comprises the rejection gate based on emitter-coupled logic, or diode AND gate.
In the such scheme, said driver element is an active pull down circuit, comprising:
First resistance R
1, first resistance R
1One end ground connection, the in-phase end of the other end and differential decoding signal and the 3rd transistor Q
3Base stage link to each other;
Second resistance R
2, second resistance R
2The end of oppisite phase of one end and differential decoding signal and the 4th transistor Q
4Base stage link to each other the other end and the 3rd transistor Q
3Emitter and the 4th transistor Q
4Collector link to each other;
The 3rd transistor Q
3, the base stage and first resistance R
1Link to each other, grounded collector, emitter is as output node V
OWith second resistance R
2And the 4th transistor Q
4Collector links to each other;
The 4th transistor Q
4, the base stage and second resistance R
2One end links to each other, and collector is as output node V
OWith second resistance R
2The other end and the 3rd transistor Q
3Emitter links to each other, and emitter is as electric current shared port V
C, with drive current source I
2Link to each other.
Drive current source I
2, an end is as electric current shared port V
CWith the 4th transistor Q
4Emitter links to each other, and the other end links to each other with power supply VEE.
In the such scheme, said drive current source I
2Have multiple way of realization, comprise a plurality of little current source parallel connections are equivalent to a big current source, perhaps the drive current source in a plurality of address decoding circuitries is linked together through the electric current shared port.
(3) beneficial effect
Can find out that from technique scheme the present invention has following beneficial effect:
1, the address decoder of the shared storer of electric current provided by the invention; Adopt the active pull down circuit to strengthen driving force; And through sharing electric current between a plurality of driver elements; Realization is redistributed the electric current of drive current source, increases pull-down current accelerating weight capacitance discharges process, reach provide when reducing circuit power consumption enough drive currents solved traditional address decoding circuitry when driving the high capacity storage array its signal fall time much larger than the rise time; Solve the bottleneck of its operating rate, thereby improved the operating rate of circuit.
2, the address decoder of the shared storer of electric current provided by the invention; Its advantage is to adopt the active pull down circuit to strengthen the driving force of decoding circuit; And the electric current shared port is provided, have that circuit structure is simple, circuit stable, low in energy consumption, characteristics such as operating rate is fast, driving force is strong.
Description of drawings
Fig. 1 is the synoptic diagram of legacy memory address decoding circuitry;
Fig. 2 is the synoptic diagram of low-power consumption high speed address decoding circuitry of the present invention;
Fig. 3 is the synoptic diagram of the address decoder of the low-power consumption of the present invention shared storer of electric current at a high speed;
Fig. 4 is the synoptic diagram of address decoding circuitry of the present invention circuit working principle when address switchover;
Fig. 5 is the multiple way of realization synoptic diagram of current source among the present invention;
To be decoded memory address circuit of the present invention driving 2.0pF electric capacity output waveform to Fig. 6, with the synoptic diagram of the comparison of traditional circuit;
Fig. 7 is the synoptic diagram that the signal output waveform of decoded memory address circuit of the present invention changes along with load capacitance.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, to further explain of the present invention.
Need to prove that embodiment of the present invention adopts the negative supply power supply, rail ground connection on the power supply, following rail is negative supply VEE.Certainly, also can adopt the positive supply power supply, rail is power supply VCC on the power supply at this moment, following rail ground connection.
A kind of example structure of low-power consumption high speed address decoding circuitry of the present invention is as shown in Figure 2, comprises address decoder unit 100 and driver element 200 two parts.
Address decoder unit 100 adopts emitter coupled logical OR not gate (ECL NOR) structure.N difference address A
1A
2... A
NRespectively with transistor Q
1-1Q
1-2... Q
1-NBase stage link to each other.N transistor Q
1-1Q
1-2... Q
1-NBe the parallel connection relation, abbreviate Q as
1Q
1Emitter and Q
2Emitter link to each other simultaneously and current source I
1Link to each other Q
2Base stage and N difference address A
1A
2... A
NCommon mode electrical level V
BLink to each other.Current source I
1The other end links to each other with power supply VEE.Q
1Collector and resistance R
1Transistor Q with driver element 200 links to each other simultaneously
3Base stage links to each other; Q
2Collector and resistance R
2When linking to each other and the transistor Q of driver element 200
4Base stage links to each other.Resistance R
1The other end links to each other with ground, resistance R
2Transistor Q in the other end and the driver element 200
3Emitter and Q
4Collector links to each other, and this node of mark is Vo.
Driver element 200 is active pull down circuit, wherein middle Q
3Collector is connected to ground, Q
4Emitter and pull-down current source I
2Link to each other, and mark should shared current node be V
C, I
2The other end link to each other with power supply VEE.
As shown in Figure 3, for N bit addresses storer, need 2
NIndividual address decoding circuitry is in order to produce 2
NIndividual memory array drive signal.The address decoder of the shared storer of electric current provided by the invention is with 2
NThe V of individual address decoding circuitry
CLink to each other, thus, 2
NIndividual address decoding circuitry can share 2
NIndividual pull-down current source.Suppose that the storage array of storer is chosen in the representative of address decoding circuitry output high level signal.The address decoding circuitry characteristics of storer are synchronization 2
NHaving only one in the individual address decoding signal is high level.Switch moment, 2 in storage address
NHave only one to switch to low level from high level in the output of individual address decoder unit, have only one to switch to high level from low level, all the other keep low level.
Address decoding circuitry is used to quicken its output and switches to low level discharge process from high level, and switches to the charging process of high level from low level.The present invention passes through to share electric current and increases pull-down current required when discharging, and increases charging current required when charging simultaneously, and is as shown in Figure 4, wherein C
1And C
2The equivalent capacity of representing storage array to constitute.
Suppose address decoding circuitry V
O1Switch to low level from high level, V
O2Switch to high level from low level.Decoding unit 100 of the present invention produces two differential signals that phase place is opposite.For this reason at V
O1When high level switches to low level, V
B1Switch to high level, thereby increase Q
2In electric current, quicken load capacitance C
1Discharge.At V
O2When low level switches to high level, V
B2Switch to low level, Q
4Be in cut-off state, Q
3Middle electric current all is used for quickening load capacitance C
2Charging.Q
4Be in cut-off state, for this reason current source I
2Unnecessary electric current is arranged.To C
1After discharge finishes, V
B1Return to low level, Q
2Middle electric current will reduce current source I
1In unnecessary electric current will be used to quicken next discharge process through the mode of sharing.
The principle that shared electric current of the present invention quickens discharge process is; Synchronization has only an address decoding circuitry to be in discharge process, and other address decoding circuitries that are in low level output will have unnecessary electric current, simultaneously the address decoding circuitry that is in charging process also had unnecessary electric current; Share through electric current; Realization is redistributed the electric current of drive current source, and the unnecessary electric current collection of other address circuits is got up to be used for to increase discharge current, quickens discharge process.
Current source described in the present invention has multiple way of realization, and is as shown in Figure 5.
Adopt traditional circuit as shown in Figure 1 to drive load capacitance C
L, along with the increase of load capacitance, the negative edge time of drive signal will be obviously greater than rising edge, has limited the operating rate of circuit.Decoded memory address circuit of the present invention is driving 2.0pF electric capacity output waveform, and as shown in Figure 6 with the comparative result of traditional circuit, the negative edge time of circuit of the present invention is significantly less than traditional circuit.And adopt the shared address decoding circuitry of electric current provided by the invention to drive same load capacitance C
L, at C
LBe increased to 2.5pF from 0.5pF, negative edge time and rising edge time obviously do not increase, and both are equal basically, as shown in Figure 7, visible validity of the present invention.
Need to prove that though address decoder unit 100 adopts emitter coupled logical OR not gate (ECL NOR) structure to describe in the example structure, the present invention can answer other address decoder element circuits.
Need to prove that though adopt bipolar transistor to describe in the diagram, structure of the present invention can be applied to the MOS circuit.
Above-described specific embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, and institute it should be understood that the above is merely specific embodiment of the present invention; Be not limited to the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. the address decoder of the shared storer of electric current; It is characterized in that; This address decoder comprises a plurality of address decoding circuitries that have the electric current shared port; The electric current shared port of each address decoding circuitry links together, and realizes sharing drive current, to increase the driving force of address decoder.
2. the address decoder of the shared storer of electric current according to claim 1; It is characterized in that; The said address decoding circuitry that has the electric current shared port comprises address decoder unit and driver element, and wherein the address decoder unit is used for output differential decoding signal behind the decoded memory address; Driver element is used for this differential decoding signal is amplified with the increase driving force, and the equivalent capacity that provides pull-down current to constitute in order to storage array in the driving storer, and the electric current shared port is provided.
3. the address decoder of the shared storer of electric current according to claim 1 is characterized in that, there is multiple way of realization said address decoder unit, comprises the rejection gate based on emitter-coupled logic, or diode AND gate.
4. the address decoder of the shared storer of electric current according to claim 1 is characterized in that, said driver element is an active pull down circuit, comprising:
First resistance R
1, first resistance R
1One end ground connection, the in-phase end of the other end and differential decoding signal and the 3rd transistor Q
3Base stage link to each other;
Second resistance R
2, second resistance R
2The end of oppisite phase of one end and differential decoding signal and the 4th transistor Q
4Base stage link to each other the other end and the 3rd transistor Q
3Emitter and the 4th transistor Q
4Collector link to each other;
The 3rd transistor Q
3, the base stage and first resistance R
1Link to each other, grounded collector, emitter is as output node V
OWith second resistance R
2And the 4th transistor Q
4Collector links to each other;
The 4th transistor Q
4, the base stage and second resistance R
2One end links to each other, and collector is as output node V
OWith second resistance R
2The other end and the 3rd transistor Q
3Emitter links to each other, and emitter is as electric current shared port V
C, with drive current source I
2Link to each other.
Drive current source I
2, an end is as electric current shared port V
CWith the 4th transistor Q
4Emitter links to each other, and the other end links to each other with power supply VEE.
5. the address decoder of the shared storer of electric current according to claim 4 is characterized in that, said drive current source I
2Have multiple way of realization, comprise a plurality of little current source parallel connections are equivalent to a big current source, perhaps the drive current source in a plurality of address decoding circuitries is linked together through the electric current shared port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210109999.4A CN102637450B (en) | 2012-04-13 | 2012-04-13 | Address decoder of current sharing type memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210109999.4A CN102637450B (en) | 2012-04-13 | 2012-04-13 | Address decoder of current sharing type memory |
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| Publication Number | Publication Date |
|---|---|
| CN102637450A true CN102637450A (en) | 2012-08-15 |
| CN102637450B CN102637450B (en) | 2014-09-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210109999.4A Active CN102637450B (en) | 2012-04-13 | 2012-04-13 | Address decoder of current sharing type memory |
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| Country | Link |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11149927B2 (en) * | 2019-03-01 | 2021-10-19 | Xiamen Eco Lighting Co. Ltd. | LED lighting apparatus |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5021688A (en) * | 1988-10-28 | 1991-06-04 | International Business Machines Corporation | Two stage address decoder circuit for semiconductor memories |
| US20070008780A1 (en) * | 2005-07-05 | 2007-01-11 | Samsung Electronics Co., Ltd. | Circuit and method of driving a word line |
| CN101060594A (en) * | 2006-02-27 | 2007-10-24 | 索尼株式会社 | Semiconductor device |
-
2012
- 2012-04-13 CN CN201210109999.4A patent/CN102637450B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5021688A (en) * | 1988-10-28 | 1991-06-04 | International Business Machines Corporation | Two stage address decoder circuit for semiconductor memories |
| US20070008780A1 (en) * | 2005-07-05 | 2007-01-11 | Samsung Electronics Co., Ltd. | Circuit and method of driving a word line |
| CN101060594A (en) * | 2006-02-27 | 2007-10-24 | 索尼株式会社 | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11149927B2 (en) * | 2019-03-01 | 2021-10-19 | Xiamen Eco Lighting Co. Ltd. | LED lighting apparatus |
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| Publication number | Publication date |
|---|---|
| CN102637450B (en) | 2014-09-17 |
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Effective date of registration: 20180904 Address after: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee after: Beijing Zhongke micro Investment Management Co.,Ltd. Address before: 100083 No.3, Beitucheng Road (West), Chaoyang District, Beijing Cities Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |
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Effective date of registration: 20181107 Address after: 215000 Jiangsu Suzhou Industrial Park 99 Jinji Hu Road 99 Suzhou Nancheng 1 building 505 room Patentee after: Zhongke core (Suzhou) Microelectronics Technology Co.,Ltd. Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee before: Beijing Zhongke micro Investment Management Co.,Ltd. |
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Effective date of registration: 20190814 Address after: Unit 505, 218 A7 Building, Xinghu Street, Suzhou Industrial Park, Jiangsu Province Patentee after: ACELA MICRO CO.,LTD. Address before: Room 505, No. 99 Jinjihu Avenue, Suzhou Industrial Park, Jiangsu Province Patentee before: Zhongke core (Suzhou) Microelectronics Technology Co.,Ltd. |
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Address after: Room 708-1, Building 1, Northwest District, Suzhou Nanocity, No. 99 Jinjihu Avenue, Suzhou Industrial Park, Suzhou Area, China (Jiangsu) Free Trade Pilot Zone, Suzhou City, Jiangsu Province, 215124 Patentee after: Xunxin Microelectronics (Suzhou) Co.,Ltd. Address before: 215000 unit 505, a7 / F, 218 Xinghu street, Suzhou Industrial Park, Jiangsu Province Patentee before: ACELA MICRO CO.,LTD. |