CN102339850A - Octagonal latticed metal-oxide-semiconductor field-effect transistor (MOSFET) power tube layout structure - Google Patents
Octagonal latticed metal-oxide-semiconductor field-effect transistor (MOSFET) power tube layout structure Download PDFInfo
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- CN102339850A CN102339850A CN2010102291145A CN201010229114A CN102339850A CN 102339850 A CN102339850 A CN 102339850A CN 2010102291145 A CN2010102291145 A CN 2010102291145A CN 201010229114 A CN201010229114 A CN 201010229114A CN 102339850 A CN102339850 A CN 102339850A
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Abstract
The invention discloses an octagonal latticed metal-oxide-semiconductor field-effect transistor (MOSFET) power tube layout structure and aims at overcoming the defects that the on resistance is great, the parasitic capacitance is great, the requirements of layout design rules are hard to satisfy and the like because a large-size MOSFET is usually used as a power device in an integrated circuit and the area efficiency of a common interdigital MOSFET power tube layout structure is low. By using lattices formed by octagonal polycrystalline silicon strips to divide an active region into square arrays and the source/drain share of adjacent MOSFETs in all directions is realized, the area utilization ratio is improved; and by using areas formed by the inclined sides of adjacent octagons, the problem of back gate contact in the MOSFET is ingeniously solved. The basic unit of an octagonal latticed MOSFET power tube disclosed by the invention consists of active regions, source region contact holes, drain region contact holes, back gate contact holes, polycrystalline silicon strips and metal windings. The entire MOSFET layout structure consists of a plurality of basic units which are spliced together.
Description
Technical field
The invention belongs to the integrated circuit diagram design field, relate generally to a kind of domain topological structure of large scale MOSFET power tube, refer in particular to a kind of domain implementation with the latticed MOSFET power tube of octagon.
Background technology
In integrated circuits such as Switching Power Supply, low dropout voltage regulator, large-sized transistor often is used as high-current switch or high power device.In order to distinguish with low-power or small signal device, use the device that designs for this type specially and be called power tube, mainly contain two kinds of bipolar transistor and field-effect transistors.Compare with bipolar transistor, field-effect transistor has that required driving power is little, the device power capacity is big and advantage such as processing compatibility is good, uses very extensively.
The MOSFET that uses as power device needs bigger size usually.Being that example is analyzed as the MOSFET power tube of switch, MOSFET is input as capacitive network, must carry out charge and discharge to input capacitance during driving element, driving be capacitive load.Therefore, the essence of Driven MOSFET is exactly that drive circuit produces pulse signal source, and its grid capacitance is carried out charge and discharge, and the control procedure that makes it under gate charge of stipulating or corresponding threshold voltage of the grid, open or turn-off.Because certainly exist certain conducting resistance during the power tube conducting, this can bring certain conduction loss, thereby influences the conversion efficiency of power supply.In order to obtain high conversion rate, then must adopt the switching tube of low on-resistance, low conducting resistance be obtained and just large-sized power tube must be adopted.And in fact, there is above-mentioned problem in the MOSFET power tube too when doing other function use.
The area efficiency of MOSFET domain is very important.Use large-sized MOSFET power tube; Though reduced the conducting resistance of power tube in theory; But the MOSFET power tube will take very large chip area in domain manufacturing process; Metal connecting line and bonding wire resistance are very big to final conduction resistance value influence, also can introduce bigger parasitic capacitance simultaneously, have a strong impact on the response speed of MOSFET power tube.The MOSFET power tube (domain is as shown in Figure 1) of conventional interdigital structure, its performance no doubt increases, but has to sacrifice the problem that bigger area solves source/drain contact and the contact of back of the body grid, has increased the cost of chip.
Summary of the invention
Of preamble, shown in Figure 1 conventional interdigital MOSFET power tube structure, the chip area utilance is lower, and parasitic capacitance and resistance are bigger.To this problem, the invention discloses the latticed MOSFET power tube of a kind of octagon domain structure, its structural representation is as shown in Figure 2, and its major technique thought is presented as:
1. be divided into the grid array to active area through the grid that uses the octagon polysilicon strip to form, realized that source/leakage of adjacent mos FET is shared, improved area utilization;
2. in the grid array that the octagon polysilicon strip is formed; Little foursquare net region can be used as the contact of back of the body grid and uses; And only need use through hole with its directly over be connected the source region contact hole metal coiling connect; Solve the contact of back of the body grid and source/big problem of leakage distance in the interdigital structure cleverly, do not increased extra wiring expense, further improved area utilization.
To the structure of the interdigital MOSFET power tube of Fig. 1, the MOSFET power tube major technique advantage of octagon network is embodied in following several aspect:
1. octagon network, because of the ingenious solution of the shared of its source/leakage and back of the body grid contact problems, bigger raising the chip area utilance, and parasitic capacitance decreases with resistance, makes the bigger raising of service behaviour acquisition of MOSFET power tube;
2. all figures are 0 °, 45 °, 90 ° or 135 ° of placements in the octagon fenestral fabric, do not have the figure of other angle, therefore do not have domain lattice point mistake;
3. octagon network area reduces to effectively reduce chip cost;
4. the octagon network is compared than interdigital structure and is had better domain fillibility, and its effect makes the mutual conductance of MOSFET power tube improve, and MOSFET power tube operating efficiency is higher.
Description of drawings
Fig. 1 interdigital structure MOSFET power tube sketch map;
The domain sketch map of the latticed MOSFET power tube of Fig. 2 octagon disclosed by the invention;
In Fig. 3 new structure shown in Figure 2, active area covers the sketch map of polysilicon strip mode;
Fig. 4 is an example with the PMOS pipe, the mode sketch map that the N trap is arranged, P+ injects and N+ injects;
The domain summary step of the latticed MOSFET elementary cell of Fig. 5 octagon disclosed by the invention;
The area efficiency contrast of latticed MOSFET domain structure of Fig. 6 octagon disclosed by the invention and interdigitated domain structure.
Embodiment
Below in conjunction with accompanying drawing, specify the latticed MOSFET power tube of octagon disclosed by the invention domain structure.
The elementary cell of the latticed MOSFET power tube of octagon is made up of active area, polysilicon strip, source region contact hole, drain region contact hole, back of the body grid contact hole and metal coiling, and the domain structure of power MOSFET is realized by the elementary cell splicing.Wherein, polysilicon strip is that a straight flange is longer, and the eight-sided formation that hypotenuse is short overlaps four such splicing of octagon polysilicon strip symmetry and adjacent straight flanges, is formed centrally a less square area of area therein; Active area covers zone and the interior zone of little square in each octagon, and the straight flange of octagon polysilicon strip, but does not cover the hypotenuse of polycrystalline octagon polysilicon strip, and the injection mode of active area is as shown in Figure 3; The source region contact hole is positioned in two diagonal zones in four octagon active areas, and the drain region contact hole is positioned in two other diagonal zones; Metal coiling is as the arrangements of " W ", uses the metal coiling to connect the source region contact hole and as the source electrode of MOSFET, the metal coiling connects the drain electrode of drain region contact hole as MOSFET; Back of the body grid contact hole need be placed in the zone of little square active area, and all place the metal coiling region covered that the little square area of carrying on the back the grid contact hole is all connected the source region contact hole; With the PMOS power tube is example, and for typical N trap CMOS technology, the PMOS pipe need be produced in the N trap, and the injection of P+ will be arranged simultaneously.One of them elementary cell, N trap are arranged as shown in Figure 4 with the injection mode of P+, and the active area in the little square is as the trap contact of PMOS pipe; And need N+ to inject in the little square area; And the ingenious realization of so just trap contact makes that elementary cell can large-area recall, need not extra trap attaching space; Effectively raise area utilization, and these arrange the generation that latch-up has been avoided in trap contact closely to a great extent.
Fig. 5 has provided the summary step in the layout generation procedure of the latticed MOSFET elementary cell of octagon disclosed by the invention.Fig. 5 A figure is the figure after the polysilicon strip placement of completion octagon and the source/leakage/back of the body grid injection, and Fig. 5 B is for accomplishing the figure after metal winds the line, and Fig. 5 C is the figure behind each contact hole of completion.
On the basis of realizing the latticed MOSFET elementary cell of octagon; Utilize the repeatability of elementary cell figure; The latticed MOSFET elementary cell of a plurality of octagons is stitched together; Make its straight flange overlapping, and the both sides of straight flange are respectively the injection region, source and leak the injection region arbitrarily, can realize extendible large scale MOSFET.
Contrast interdigitated MOSFET, the area utilization of octagon fenestral fabric increases substantially.Fig. 6 is under certain CMOS technology, the contrast of the area efficiency of octagon disclosed by the invention latticed MOSFET power tube domain structure and interdigitated domain structure.For the MOSFET of 1000 μ m/0.35 μ m, interdigital structure A adopts the structure of 10 groups every group 10 10 μ m/0.35 μ m MOS, places the contact of back of the body grid between group, and its area overhead is 3100 μ m
2Interdigital structure B adopts the structure of 10 groups every group 20 5 μ m/0.35 μ m MOS, places the contact of back of the body grid between group, and its area overhead is 3300 μ m
2Eight-sided formation A adopts straight flange 3 μ m, the octagon of hypotenuse 1 μ m, and its area overhead is 1650 μ m
2Eight-sided formation B adopts straight flange 2 μ m, and hypotenuse is the octagon of 0.5 μ m, and its area overhead is 1250 μ m
2It is thus clear that the latticed MOSFET domain structure of octagon has significantly improved the area efficiency of domain.
In sum; In view of the low problem of conventional MOSFET power tube domain structure area utilization; The invention discloses the latticed MOSFET power tube of a kind of octagon domain structure, be divided into the grid array to active area, realized that source/leakage of adjacent mos FET is shared through the grid that uses the octagon polysilicon strip to form; Also solved simultaneously the problem of back of the body grid contact among the large scale MOSFET cleverly; Thereby reduced chip area greatly, improved the performance of MOSFET power tube, reduced the cost of chip.
Claims (7)
1. the structure of a power MOSFET domain comprises:
The domain structure of the latticed MOSFET power tube of octagon is repeated to splice and is realized by elementary cell, and elementary cell is made up of active area, polysilicon strip, source region contact hole, drain region contact hole, back of the body grid contact hole and metal coiling;
2. elementary cell according to claim 1 is formed, and polysilicon strip is characterised in that:
Polysilicon strip is that a straight flange is longer, and the eight-sided formation that hypotenuse is short overlaps four such splicing of octagon polysilicon strip symmetry and adjacent straight flanges, wherein is formed centrally a square area that area is less;
3. elementary cell according to claim 1 is formed, polysilicon strip structure according to claim 2, and active area is characterised in that:
Active area covers the zone in the described little square of zone, claim 2 in each octagon, and the straight flange of octagon polysilicon strip, but does not cover the hypotenuse of octagon polysilicon strip;
4. elementary cell according to claim 1 is formed, polysilicon strip structure according to claim 2, and active area constituted mode according to claim 3, source region contact hole, drain region contact hole are characterised in that:
The source region contact hole is placed in the octagon zone, two diagonal angles in four octagon active areas, and the drain region contact hole is placed in two other diagonal zones;
5. the domain structure of elementary cell composition according to claim 1 and MOSFET; Polysilicon strip structure according to claim 2; Active area constituted mode according to claim 3; The arrangement mode of source region according to claim 4 contact hole, drain region contact hole, the metal coiling is characterised in that:
The metal coiling is to be made up of the shape of metal wire as " W ", and the metal coiling connects the source electrode of all source region contact holes as MOSFET, and the metal coiling connects the drain electrode of all drain region contact holes as MOSFET;
6. the domain structure of elementary cell composition according to claim 1 and MOSFET; Polysilicon strip structure according to claim 2; Active area constituted mode according to claim 3; The arrangement mode of source region according to claim 4 contact hole, drain region contact hole, according to the connected mode of claim 5 metal coiling, back of the body grid contact hole is characterised in that:
In the little square area that the metal coiling that connects the source region contact hole covers, place back of the body grid contact hole;
7. the domain structure of elementary cell composition according to claim 1 and MOSFET; Polysilicon strip structure according to claim 2; Active area constituted mode according to claim 3, the arrangement mode of source region according to claim 4 contact hole, drain region contact hole is according to the connected mode of claim 5 metal coiling; According to the arrangement mode of claim 6 back of the body grid contact hole, N+ injects and the P+ injection is characterised in that:
In typical C MOS technology, if be the N+ injection in the back of the body gate contact zone territory, carrying on the back the grid contact so will be as the trap contact of PMOS pipe, and the P+ injection need be carried out in other zone except that back of the body gate contact zone territory; On the contrary, if be the P+ injection in the back of the body gate contact zone territory, carrying on the back the grid contact so will be as the substrate contact of NMOS pipe, and the N+ injection is carried out in other zone except that back of the body gate contact zone territory.
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| CN2010102291145A CN102339850A (en) | 2010-07-19 | 2010-07-19 | Octagonal latticed metal-oxide-semiconductor field-effect transistor (MOSFET) power tube layout structure |
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| CN2010102291145A CN102339850A (en) | 2010-07-19 | 2010-07-19 | Octagonal latticed metal-oxide-semiconductor field-effect transistor (MOSFET) power tube layout structure |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104409459A (en) * | 2014-10-28 | 2015-03-11 | 长沙景嘉微电子股份有限公司 | Octagonal latticed MOSFET power tube layout structure |
| CN104899343A (en) * | 2014-03-04 | 2015-09-09 | 中国科学院上海微***与信息技术研究所 | Layout design of crossing grid structure MOSFET and multi-crossing finger grid structure MOSFET |
| CN107068674A (en) * | 2016-12-29 | 2017-08-18 | 北京时代民芯科技有限公司 | A kind of anti-single particle breech lock reinforced layout structure of area efficient |
| CN107942615A (en) * | 2017-12-22 | 2018-04-20 | 江苏宏微科技股份有限公司 | A kind of IGBT or MOSFET domain structures used for electric vehicle |
| CN109360185A (en) * | 2018-08-28 | 2019-02-19 | 中国科学院微电子研究所 | A kind of domain resolution chart extracting method, device, equipment and medium |
| CN112906337A (en) * | 2021-03-24 | 2021-06-04 | 上海华虹宏力半导体制造有限公司 | Method and system for acquiring compressible region in layout file and electronic equipment |
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| US6097066A (en) * | 1997-10-06 | 2000-08-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Electro-static discharge protection structure for semiconductor devices |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104899343A (en) * | 2014-03-04 | 2015-09-09 | 中国科学院上海微***与信息技术研究所 | Layout design of crossing grid structure MOSFET and multi-crossing finger grid structure MOSFET |
| CN104899343B (en) * | 2014-03-04 | 2018-07-20 | 中国科学院上海微***与信息技术研究所 | Intersect grid structure MOSFET and multi-fork refers to the layout design of grid structure MOSFET |
| CN104409459A (en) * | 2014-10-28 | 2015-03-11 | 长沙景嘉微电子股份有限公司 | Octagonal latticed MOSFET power tube layout structure |
| CN107068674A (en) * | 2016-12-29 | 2017-08-18 | 北京时代民芯科技有限公司 | A kind of anti-single particle breech lock reinforced layout structure of area efficient |
| CN107942615A (en) * | 2017-12-22 | 2018-04-20 | 江苏宏微科技股份有限公司 | A kind of IGBT or MOSFET domain structures used for electric vehicle |
| CN107942615B (en) * | 2017-12-22 | 2024-03-22 | 江苏宏微科技股份有限公司 | IGBT or MOSFET layout structure for electric automobile |
| CN109360185A (en) * | 2018-08-28 | 2019-02-19 | 中国科学院微电子研究所 | A kind of domain resolution chart extracting method, device, equipment and medium |
| CN109360185B (en) * | 2018-08-28 | 2022-07-26 | 中国科学院微电子研究所 | Layout test pattern extraction method, device, equipment and medium |
| CN112906337A (en) * | 2021-03-24 | 2021-06-04 | 上海华虹宏力半导体制造有限公司 | Method and system for acquiring compressible region in layout file and electronic equipment |
| CN112906337B (en) * | 2021-03-24 | 2024-05-17 | 上海华虹宏力半导体制造有限公司 | Method and system for acquiring compressible area in layout file and electronic equipment |
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Application publication date: 20120201 |