CN104899343A - Layout design of crossing grid structure MOSFET and multi-crossing finger grid structure MOSFET - Google Patents
Layout design of crossing grid structure MOSFET and multi-crossing finger grid structure MOSFET Download PDFInfo
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- CN104899343A CN104899343A CN201410077465.7A CN201410077465A CN104899343A CN 104899343 A CN104899343 A CN 104899343A CN 201410077465 A CN201410077465 A CN 201410077465A CN 104899343 A CN104899343 A CN 104899343A
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- 238000013461 design Methods 0.000 title claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims description 17
- 230000010355 oscillation Effects 0.000 abstract description 7
- 238000005192 partition Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 7
- 230000009514 concussion Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229920000742 Cotton Polymers 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides layout design of a crossing grid structure MOSFET and a multi-crossing finger grid structure MOSFET. The layout design of the crossing grid structure MOSFET comprises design of a semiconductor substrate, a crossing grid structure, source regions and drain regions; the crossing grid structure comprises a first strip grid and a second strip grid vertical to the first strip grid; the first strip grid and the second strip grid partition the semiconductor substrate into four regions; and the source regions and the drain regions are alternatively arrayed in the four regions. According to the invention, the utilization rate of the source regions can be improved, a drive current is increased, grid resistance is reduced, and the maximal oscillation frequency is improved; the crossing grid structure is adopted, spirally distributed source electrodes and drain electrodes are adopted, a layout area is fully used, a multi-crossing finger grid structure can be realized, and the requirement of a designed circuit on a device can be met; and meanwhile, if the connection of grids adopts four-end connection, the grid resistance can be effectively reduced, so the power gain and the maximal oscillation frequency of the device can be obviously improved.
Description
Technical field
The present invention relates to a kind of MOSFET layout design, particularly relate to a kind of grid structure MOSFET and multi-fork of intersecting and refer to the layout design of grid structure MOSFET.
Background technology
Along with the development of semiconductor technology, mos field effect transistor (MOSFET) is widely used in integrated circuit (IC) design.MOSFET is voltage-controlled device, and when the threshold voltage of gate bias voltage higher than device, MOSFET raceway groove forms inversion layer, forms conductive channel between source electrode and drain electrode.When grid voltage is lower than threshold voltage, conductive channel close, device by.When break-over of device, apply signal at grid or source electrode, drain electrode has corresponding signal and exports.When semiconductor technology is applied to radio frequency arts, due to ghost effect, as the impact of dead resistance, stray capacitance, the performance of device can be affected.Improving constantly of semiconductor technology technique, makes the cutoff frequency of device also improve constantly.
Radio-frequency technique often requires higher power transfer characteristic.Maximum concussion frequency and ghost effect closely bound up, especially affect huge by gate resistance, source and drain resistance etc.And the reduction of dead resistance needs continuing to optimize of layout design.Therefore for improving constantly device while frequency, needing to be optimized domain, reducing the ghost effect of device, improving constantly power gain and the maximum oscillation frequency of device.
In view of above defect of the prior art, the object of this invention is to provide the layout design that a kind of decussation grid structure MOSFET and multi-fork refer to grid structure MOSFET, to improve the utilization factor of active area, increase drive current, reduce gate resistance, improve maximum concussion frequency.
Summary of the invention
The shortcoming of prior art in view of the above, a kind of grid structure MOSFET and multi-fork of intersecting is the object of the present invention is to provide to refer to the layout design of grid structure MOSFET to improve the utilization factor of active area, increase drive current, reduce gate resistance, improve maximum concussion frequency.
For achieving the above object and other relevant objects, the invention provides a kind of layout design of intersecting grid structure MOSFET, described layout design comprises:
Semiconductor substrate, decussation grid structure, source region and drain region;
Described decussation grid structure comprises the first strip grid and second strip grid vertical with described first strip grid, and described Semiconductor substrate is divided into four regions by described first strip grid and the second strip grid; Described source region and drain region are alternately arranged in described four regions.
As a kind of preferred version of the layout design of intersection grid structure MOSFET of the present invention, the end of described decussation grid structure is two ends interconnection, three end interconnection or the interconnection of four ends.
As a kind of preferred version of the layout design of intersection grid structure MOSFET of the present invention, described decussation grid structure comprises the dielectric layer being incorporated into described semiconductor substrate surface and the electrode layer being incorporated into described dielectric layer surface.
As a kind of preferred version of the layout design of intersection grid structure MOSFET of the present invention, the shape in described source region and drain region is rectangle.
As a kind of preferred version of the layout design of intersection grid structure MOSFET of the present invention, the shape in described source region and drain region is the shaped as frame of the marginal distribution along described decussation grid structure.
As a kind of preferred version of the layout design of intersection grid structure MOSFET of the present invention, respectively this source region is by metal interconnection wire short circuit, and respectively this drain region is by metal interconnection wire short circuit.
The present invention also provides a kind of multi-fork to refer to the layout design of grid structure MOSFET, comprising:
Semiconductor substrate, multi-fork refer to grid structure, source region and drain region;
Described multi-fork refers to that grid structure comprises the first strip grid and multiple second strip grids vertical with described first strip grid, and described Semiconductor substrate is divided into multiple region by described first strip grid and the second strip grid; Described source region and drain region are alternately arranged in described multiple region.
Refer to a kind of preferred version of the layout design of grid structure MOSFET as multi-fork of the present invention, described multi-fork refers to that multiple ends of grid structure interconnect for part or all interconnect.
Refer to a kind of preferred version of the layout design of grid structure MOSFET as multi-fork of the present invention, described multi-fork refers to that grid structure comprises the dielectric layer being incorporated into described semiconductor substrate surface and the electrode layer being incorporated into described dielectric layer surface.
Refer to a kind of preferred version of the layout design of grid structure MOSFET as multi-fork of the present invention, respectively this source region is by metal interconnection wire short circuit, and respectively this drain region is by metal interconnection wire short circuit.
As mentioned above, the invention provides a kind of grid structure MOSFET and multi-fork of intersecting and refer to the layout design of grid structure MOSFET, the layout design of described intersection grid structure MOSFET comprises: Semiconductor substrate, decussation grid structure, source region and drain region; Described decussation grid structure comprises the first strip grid and second strip grid vertical with described first strip grid, and described Semiconductor substrate is divided into four regions by described first strip grid and the second strip grid; Described source region and drain region are alternately arranged in described four regions.The present invention compares common interdigitation device, can improve the utilization factor of active area, increases drive current, reduces gate resistance, improves maximum concussion frequency; The present invention adopts and intersects grid structures, adopts spiral distribution source electrode and drain electrode, takes full advantage of chip area as much as possible, and can realize multi-fork and refer to (multi-finger) structure, can meet the demand of design circuit to device; Simultaneously to the connection of grid, the modes such as one end connection, two ends connection, three-terminal link, four end connections can be adopted; When adopting four ends to connect, can gate resistance be effectively reduced, therefore can significantly improve power gain and the maximum oscillation frequency of device.
Accompanying drawing explanation
Fig. 1 is shown as the structural representation of the layout design of intersection grid structure MOSFET of the present invention.
Fig. 2 is shown as the structural representation in the layout design A-A ' cross section of the intersection grid structure MOSFET in Fig. 1 of the present invention.
Fig. 3 is shown as the structural representation in the layout design B-B ' cross section of the intersection grid structure MOSFET in Fig. 1 of the present invention.
Fig. 4 is shown as the schematic equivalent circuit of the layout design of intersection grid structure MOSFET of the present invention.
Fig. 5 is shown as the structural representation of the layout design another embodiment of intersection grid structure MOSFET of the present invention.
Fig. 6 is shown as the structural representation that multi-fork of the present invention refers to the layout design of grid structure MOSFET.
Element numbers explanation
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this instructions can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this instructions also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 1 ~ Fig. 6.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Embodiment 1
Fig. 1 ~ Fig. 3 is shown as the structural representation of the layout design of the intersection grid structure MOSFET of the present embodiment, and wherein, Fig. 2 is the structural representation in A-A ' cross section in Fig. 1, and Fig. 3 is the structural representation in B-B ' cross section in Fig. 1.
Fig. 4 is then shown as the equivalent circuit diagram of the intersection grid structure MOSFET of the present embodiment.
As shown in Figure 1 to 4, the present embodiment provides a kind of layout design of intersecting grid structure MOSFET, and described layout design comprises:
Semiconductor substrate, decussation grid structure 10, source region 20 and drain region 30;
Described decussation grid structure 10 comprises the first strip grid 101 and second strip grid 102 vertical with described first strip grid 101, and described Semiconductor substrate is divided into four regions by described first strip grid 101 and the second strip grid 102; Described source region 20 and drain region 30 are alternately arranged in described four regions.
Exemplarily, described Semiconductor substrate can be SOI substrate, body silicon substrate, GaAs substrate, GaN substrate, InP substrate etc., and in the present embodiment, described Semiconductor substrate is SOI substrate, and described SOI substrate comprises silicon substrate 90, oxygen buried layer 80 and top layer silicon.It should be noted that, usually, the layout design of the present embodiment goes for designing based on the MOSFET of various material substrate.
Exemplarily, the end of described decussation grid structure 10 is two ends interconnection, three end interconnection or the interconnection of four ends.In the present embodiment, described in, the end of described decussation grid structure 10 is four ends interconnection (this metal interconnecting layer does not give diagram), and this design can effectively reduce gate resistance, can significantly improve power gain and the maximum oscillation frequency of device.
As shown in Figure 2, exemplarily, described decussation grid structure 10 comprises the dielectric layer 103 being incorporated into described semiconductor substrate surface and the electrode layer 104 being incorporated into described dielectric layer 103 surface.Described dielectric layer 103 can be the material such as silicon dioxide, silicon nitride, and described electrode layer 104 can be the material such as metal electrode, polysilicon.It should be noted that, above cited different materials is only several preferred version of the present invention, in the production of reality, is not limited thereto.
As shown in Figure 3, be channel region 70 below described decussation grid structure 10, described channel region 70 by each this source region 20 and respectively this drain region 30 be spaced from each other.
As shown in Figure 1, exemplarily, the shape in described source region 20 and drain region 30 is rectangle.
Exemplarily, respectively this source region 20 is by metal interconnection wire 40 short circuit, and respectively this drain region 30 is by metal interconnection wire 40 short circuit, wherein, described metal interconnection wire 40 by contact hole 50 and each this source region 20 or respectively this drain region 30 be connected.
Exemplarily, the layout design of the present embodiment also comprises and is positioned at device periphery, for the isolation structure 60 of device isolation.Described isolation structure 60 can be as fleet plough groove isolation structure STI etc.
Fig. 4 is shown as the equivalent circuit diagram of the intersection grid structure MOSFET of the present embodiment, adopt the layout design of the intersection grid structure MOSFET of the present embodiment, 4 MOSFET can be equivalent to be connected in parallel, and in fact, the present embodiment only need make two source electrodes and two drain, greatly increase the utilization factor of active area, and add the drive current of MOSFET.
Embodiment 2
As shown in Figure 5, the present embodiment provides a kind of layout design of intersecting grid structure MOSFET, and its basic structure is as embodiment 1, and wherein, the shape in described source region 20 and drain region 30 is the shaped as frame of the marginal distribution along described decussation grid structure 10.The layout design of this structure can realize the source region 20 of different area and drain region 30 is designed, and to meet the various performance requirements of MOSFET, greatly can improve the alternative of MOSFET performance.
Embodiment 3
As shown in Figure 6, the present embodiment provides a kind of multi-fork to refer to the layout design of grid structure MOSFET, comprising:
Semiconductor substrate, multi-fork refer to grid structure, source region 20 and drain region 30;
Described multi-fork refers to that grid structure comprises the first strip grid 101 and multiple second strip grids 102 vertical with described first strip grid 101, and described Semiconductor substrate is divided into multiple region by described first strip grid 101 and the second strip grid 102; Described source region 20 and drain region 30 are alternately arranged in described multiple region.
Exemplarily, described multi-fork refers to that multiple ends of grid structure interconnect for part or all interconnect.Described multi-fork is referred to multiple ends of grid structure carry out part interconnection or all interconnect, when especially all interconnecting, can gate resistance be effectively reduced, power gain and the maximum oscillation frequency of device can be significantly improved.
Exemplarily, described multi-fork refers to that grid structure comprises the dielectric layer 103 being incorporated into described semiconductor substrate surface and the electrode layer 104 being incorporated into described dielectric layer 103 surface.Described dielectric layer 103 can be the material such as silicon dioxide, silicon nitride, and described electrode layer 104 can be the material such as metal electrode, polysilicon.It should be noted that, above cited different materials is only several preferred version of the present invention, in the production of reality, is not limited thereto.
Exemplarily, respectively this source region 20 is by metal interconnection wire short circuit, and respectively this drain region 30 is not by metal interconnection wire short circuit (wherein, peripheral metal interconnection wire gives diagram).
It should be noted that, described in the present embodiment, the quantity of the second strip grid 102 can increase and decrease as required, is not limited thereto, in addition, the multi-fork of the present embodiment refers to that other the parts of layout design of grid structure MOSFET can refer to embodiment 1, no longer wads a quilt with cotton state at this.
As mentioned above, the invention provides a kind of grid structure MOSFET and multi-fork of intersecting and refer to the layout design of grid structure MOSFET, the layout design of described intersection grid structure MOSFET comprises: Semiconductor substrate, decussation grid structure 10, source region 20 and drain region 30; Described decussation grid structure 10 comprises the first strip grid 101 and second strip grid 102 vertical with described first strip grid 101, and described Semiconductor substrate is divided into four regions by described first strip grid 101 and the second strip grid 102; Described source region 20 and drain region 30 are alternately arranged in described four regions.The present invention compares common interdigitation device, can improve the utilization factor of active area, increases drive current, reduces gate resistance, improves maximum concussion frequency; The present invention adopts and intersects grid structures, adopts spiral distribution source electrode and drain electrode, takes full advantage of chip area as much as possible, and can realize multi-fork and refer to (multi-finger) structure, can meet the demand of design circuit to device; Simultaneously to the connection of grid, the modes such as one end connection, two ends connection, three-terminal link, four end connections can be adopted; When adopting four ends to connect, can gate resistance be effectively reduced, therefore can significantly improve power gain and the maximum oscillation frequency of device.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (10)
1. intersect a layout design of grid structure MOSFET, it is characterized in that, comprising:
Semiconductor substrate, decussation grid structure, source region and drain region;
Described decussation grid structure comprises the first strip grid and second strip grid vertical with described first strip grid, and described Semiconductor substrate is divided into four regions by described first strip grid and the second strip grid; Described source region and drain region are alternately arranged in described four regions.
2. the layout design of intersection grid structure MOSFET according to claim 1, is characterized in that: the end of described decussation grid structure is two ends interconnection, three end interconnection or the interconnection of four ends.
3. the layout design of intersection grid structure MOSFET according to claim 1, is characterized in that: described decussation grid structure comprises the dielectric layer being incorporated into described semiconductor substrate surface and the electrode layer being incorporated into described dielectric layer surface.
4. the layout design of intersection grid structure MOSFET according to claim 1, is characterized in that: the shape in described source region and drain region is rectangle.
5. the layout design of intersection grid structure MOSFET according to claim 1, is characterized in that: the shape in described source region and drain region is the shaped as frame of the marginal distribution along described decussation grid structure.
6. the layout design of intersection grid structure MOSFET according to claim 1, is characterized in that: respectively this source region is by metal interconnection wire short circuit, and respectively this drain region is by metal interconnection wire short circuit.
7. multi-fork refers to a layout design of grid structure MOSFET, it is characterized in that, comprising:
Semiconductor substrate, multi-fork refer to grid structure, source region and drain region;
Described multi-fork refers to that grid structure comprises the first strip grid and multiple second strip grids vertical with described first strip grid, and described Semiconductor substrate is divided into multiple region by described first strip grid and the second strip grid; Described source region and drain region are alternately arranged in described multiple region.
8. multi-fork according to claim 7 refers to the layout design of grid structure MOSFET, it is characterized in that: described multi-fork refers to that multiple ends of grid structure interconnect for part or all interconnect.
9. multi-fork according to claim 7 refers to the layout design of grid structure MOSFET, it is characterized in that: described multi-fork refers to that grid structure comprises the dielectric layer being incorporated into described semiconductor substrate surface and the electrode layer being incorporated into described dielectric layer surface.
10. multi-fork according to claim 7 refers to the layout design of grid structure MOSFET, it is characterized in that: respectively this source region is by metal interconnection wire short circuit, and respectively this drain region is by metal interconnection wire short circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410077465.7A CN104899343B (en) | 2014-03-04 | 2014-03-04 | Intersect grid structure MOSFET and multi-fork refers to the layout design of grid structure MOSFET |
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| CN201410077465.7A CN104899343B (en) | 2014-03-04 | 2014-03-04 | Intersect grid structure MOSFET and multi-fork refers to the layout design of grid structure MOSFET |
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| CN104899343A true CN104899343A (en) | 2015-09-09 |
| CN104899343B CN104899343B (en) | 2018-07-20 |
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| JP2006261437A (en) * | 2005-03-17 | 2006-09-28 | Mitsumi Electric Co Ltd | Semiconductor device |
| KR20100067874A (en) * | 2008-12-12 | 2010-06-22 | 주식회사 동부하이텍 | Mosfet device |
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| CN102142462A (en) * | 2011-02-25 | 2011-08-03 | 北京大学 | Power MOS transistor of asymmetric structure and array thereof |
| KR20110128419A (en) * | 2010-05-24 | 2011-11-30 | (주) 트리노테크놀로지 | Power semiconductor device with trench gate structure |
| CN102339850A (en) * | 2010-07-19 | 2012-02-01 | 中国人民解放军国防科学技术大学 | Octagonal latticed metal-oxide-semiconductor field-effect transistor (MOSFET) power tube layout structure |
| CN102956647A (en) * | 2011-08-31 | 2013-03-06 | 中国科学院微电子研究所 | Semiconductor device and manufacture method thereof |
| CN103178116A (en) * | 2013-03-15 | 2013-06-26 | 中国科学院宁波材料技术与工程研究所 | Transistor with modified grid structure |
-
2014
- 2014-03-04 CN CN201410077465.7A patent/CN104899343B/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006261437A (en) * | 2005-03-17 | 2006-09-28 | Mitsumi Electric Co Ltd | Semiconductor device |
| KR20100067874A (en) * | 2008-12-12 | 2010-06-22 | 주식회사 동부하이텍 | Mosfet device |
| CN101764136A (en) * | 2009-12-24 | 2010-06-30 | 中国科学院上海微***与信息技术研究所 | Interdigital structure capable of regulating channel current of vertical gate SOI CMOS devices |
| KR20110128419A (en) * | 2010-05-24 | 2011-11-30 | (주) 트리노테크놀로지 | Power semiconductor device with trench gate structure |
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