CN104409503B - Layout design of MOSFET with multiple interdigital grid electrode structures - Google Patents
Layout design of MOSFET with multiple interdigital grid electrode structures Download PDFInfo
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- CN104409503B CN104409503B CN201410674653.8A CN201410674653A CN104409503B CN 104409503 B CN104409503 B CN 104409503B CN 201410674653 A CN201410674653 A CN 201410674653A CN 104409503 B CN104409503 B CN 104409503B
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- 238000013461 design Methods 0.000 title abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims description 11
- 238000009826 distribution Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 11
- 238000000034 method Methods 0.000 abstract description 10
- 230000005669 field effect Effects 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
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- 238000010586 diagram Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000013329 compounding Methods 0.000 description 1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a layout deign of a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with multiple interdigital grid electrode structures. The MOSFET comprises a semiconductor substrate, a first interdigital grid electrode structure, a second interdigital grid electrode structure, a body contact zone, a source zone and a drain zone; and the body contact zone is shared by the first interdigital grid electrode structure and the second interdigital grid electrode structure. The body contact zone is shared, so that the utilization rate of the body contact zone can be improved and the parasitic capacitance can be reduced. Compared with an ordinary body contact device, the active zone has high utilization rate; under the same total grid width condition, the area of the body contact zone is reduced by half and the integration level is improved. The middle body zone is shared by the active zones at two sides, so that the occupied area of metal connecting wires is reduced and the parasitic capacitance can be reduced. The parallel connection of grid electrodes at two sides is realized without increasing wiring difficulty and the resistance of the grid electrodes is reduced. The parallel connection of the drain electrodes at two sides is realized without increasing wiring difficulty and the resistance of the drain electrodes is reduced. The design method of the layout structure of devices has a certain application value in the radio frequency circuit field.
Description
Technical field
The present invention relates to technical field of semiconductor device, more particularly to a kind of domain of multi-fork finger grid structure MOSFET
Design.
Background technology
With the continuous development of semiconductor technology, mos field effect transistor (MOSFET) is extensively applied
In IC design.Insulation silicon technology (SOI), because with oxygen buried layer, its parasitic capacitance is low, the direct frequency phase of device
It is higher for bulk silicon technology, and, SOI technology realizes the Fully dielectric isolation of individual devices, eliminates latch-up, and lets out
Leakage current is low, is very suitable for low-power consumption, high performance application.It is integrated on insulation silicon substrate with the application of High resistivity substrate
The integrated inductor of high-quality is possibly realized, and integrated level is higher, simultaneously because its resistance to crosstalk ability is strong, in SoC chip field tool
It is advantageous, be conducive to numeral, simulation, radio circuit it is integrated.Relative to widely used compounding techniques in radio-frequency technique, its
It is with low cost, it is more suitable for civilian consumer electronics.Based on above advantage, insulation silicon technology is obtained extensively in radio frequency arts
Concern.Then, the presence of floater effect also limit its application in analog radio frequency field, and body contact technique realizes suppression
Floater effect, obtains extensively application in radio circuit.However, body contact technique introduces extra parasitic parameter, it is such as parasitic
The impact of resistance, parasitic capacitance, can affect the radio-frequency performance of device, especially shake frequency reduce device cut-off frequency and
Frequency of oscillation, the frequency characteristic for how improving device is always the research emphasis that device works.
The content of the invention
In light of the shortcomings of the prior art, it is an object of the invention to provide a kind of new how slotting finger grid structure MOSFET
Layout design, reduce dead resistance and parasitic capacitance, maximum concussion frequency is improved, in particular for the less application of slotting index
Under the conditions of, relative to traditional method for designing, effect is obvious.
For achieving the above object and other related purposes, the present invention provides a kind of domain of multi-fork finger grid structure MOSFET
Design, multi-fork finger grid structure MOFET at least includes：It is Semiconductor substrate, the first multi-fork finger grid structure, more than second interdigital
Grid structure, body contact zone, source region and drain region；The first multi-fork finger grid structure is equal with the second multi-fork finger grid structure
Including：First strip grid of two parallel distributions and multiple between described two first strip grids and with described first
Strip grid the second strip grid connected vertically；The first strip grid and the second strip grid are by the Semiconductor substrate
Multiple regions are divided into, the source region and drain region are alternately distributed in the plurality of region；The body contact zone for multiple, parallel point
It is distributed between the first multi-fork finger grid structure and the second multi-fork finger grid structure, is the first multi-fork finger grid knot
Structure and the second multi-fork finger grid structure are shared；Source region in the first multi-fork finger grid structure and second multi-fork
Source region in finger grid structure is interconnected by metal line layer with the body contact zone.
Preferably, two the first strip grids near the body contact zone are respectively across the body contact zone, institute
State two the first strip grids to partly overlap with the body contact zone, and be separated by between described two first strip grids certain
Spacing.
Preferably, each the described drain region in the first multi-fork finger grid structure is respectively by metal line layer short circuit, institute
Each the described drain region stated in the second multi-fork finger grid structure passes through metal line layer short circuit.
Preferably, the drain region in the drain region in the first multi-fork finger grid structure and the second multi-fork finger grid structure
It is in parallel by metal line layer.
Preferably, the grid in the grid in the first multi-fork finger grid structure and the second multi-fork finger grid structure
It is in parallel by metal line layer.
Preferably, the first multi-fork finger grid structure is distributed in described with the second multi-fork finger grid symmetrical configuration
The two ends of body contact zone.
Preferably, the number of the second strip grid in the quantity of the body contact zone and each multi-fork finger grid structure
Amount is identical, the body contact zone and the first strip gate vertical；And each described body contact zone is located at the described of its two ends
In second strip grid projection join line on the semiconductor substrate.
Preferably, in the first multi-fork finger grid structure in institute's active area, the second multi-fork finger grid structure
Institute's active area and all of body contact zone are interconnected together by metal line layer.
Preferably, the first multi-fork finger grid structure and the second multi-fork finger grid structure include being located at described half
Gate dielectric layer on conductor substrate and the gate material layers on the gate dielectric layer.
Preferably, the layout design of multi-fork finger grid structure MOSFET also includes dummy gate, the dummy gate
The two ends of the first multi-fork finger grid structure and the second multi-fork finger grid structure are located at respectively, and it is how interdigital positioned at each
The region between described two first strip grids in grid structure, with described first in each multi-fork finger grid structure
Shape grid and the second strip grid are separated by certain spacing.
As described above, the layout design of multi-fork finger grid structure MOSFET of the present invention, has the advantages that：(1)
The layout design of more common multi-fork finger grid structure MOSFET is compared, the utilization rate of its active area is high, in identical total grid width
Under the conditions of, body contact zone domain area reduces half, can improve integrated level；(2) body contact zone is public by its both sides active area,
Metal connecting line occupied area is reduced, and can reduce parasitic capacitance；(3) the first multi-fork is realized in the case where wiring difficulty is not increased
The parallel connection of finger grid structure and the second multi-fork finger grid structure, reduces drain region resistance；(4) in the situation for not increasing wiring difficulty
The lower drain region realized in the first multi-fork finger grid structure is in parallel with the drain region in the second multi-fork finger grid structure, reduces drain region
Resistance.
Description of the drawings
Fig. 1 is shown as the overlooking the structure diagram of the layout design of multi-fork finger grid structure MOSFET of the present invention.
Fig. 2 is shown as the structural representation of the layout design along AA ' sections of multi-fork finger grid structure MOSFET of the present invention.
Fig. 3 is shown as the structural representation of the layout design along BB ' sections of multi-fork finger grid structure MOSFET of the present invention.
Component label instructions
10 Semiconductor substrates
101 backing bottoms
102 oxygen buried layers
103 top layer silicons
20 first multi-fork finger grid structures
201 first strip grids
202 second strip grids
21 second multi-fork finger grid structures
22 dummy gates
2021 gate dielectric layers
2022 gate material layers
30 body contact zones
31 body areas
40 source regions
50 drain regions
60 metal line layers
70 contact holes
80 isolation structures
90 first conductive type ion injection regions
91 second conductive type ion injection regions
Specific embodiment
Embodiments of the present invention are illustrated below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands easily other advantages and effect of the present invention.The present invention can also pass through concrete realities different in addition
The mode of applying is carried out or applies, the every details in this specification can also based on different viewpoints with application, without departing from
Various modifications and changes are carried out under the spirit of the present invention.
Refer to Fig. 1 to Fig. 3.It should be noted that the diagram provided in the present embodiment only illustrates in a schematic way this
The basic conception of invention, though only show in diagram with relevant component in the present invention rather than according to package count during actual enforcement
Mesh, shape and size are drawn, and the kenel of each component, quantity and ratio can be a kind of random change during its actual enforcement, and its
Assembly layout kenel is likely to increasingly complex.
Fig. 1 is referred to, the present invention provides a kind of layout design of multi-fork finger grid structure MOSFET, the multi-fork finger grid
Structure MOFET at least includes：Semiconductor substrate 10, the first multi-fork finger grid structure 20, the second multi-fork finger grid structure 21, body connect
Tactile area 30, source region 40 and drain region 50；The first multi-fork finger grid structure 20 is wrapped with the second multi-fork finger grid structure 21
Include：First strip grid 201 of two parallel distributions and it is multiple between described two first strip grids 201 and with it is described
First strip grid 201, second strip grid 202 connected vertically；The first strip grid 201 and second strip grid
The Semiconductor substrate 10 is divided into multiple regions by pole 202, and the source region 40 and drain region 50 are alternately distributed in the plurality of region
It is interior；The body contact zone 30 is parallel to be distributed in the first multi-fork finger grid structure 20 and more than the second interdigital grid for multiple
Between pole structure 21, shared by the first multi-fork finger grid structure 20 and the second multi-fork finger grid structure 21；It is described
Source region 40 in source region 40 in first multi-fork finger grid structure 20 and the second multi-fork finger grid structure 21 is via contact hole
70 are interconnected by metal line layer 60 with the body contact zone 30.By first multi-fork that a body contact zone 30 is both sides
Finger grid structure 20 and the second multi-fork finger grid structure 21 are shared and carry out effectively body contact, compared to traditional multi-fork
The layout design of finger grid structure MOSFET, on the premise of total grid width inconvenience, the area of body contact zone reduces half, section
Device space shared in the chips has been saved, the integrated level of device has been improve；Simultaneously so that the area drop shared by metal connecting line
It is low, and then it is effectively reduced the parasitic capacitance of device.
Specifically, the Semiconductor substrate 10 can be SOI substrate, body silicon substrate, GaAs substrates, GaN substrate, InP linings
Bottom etc., it is preferable that in the present embodiment, the Semiconductor substrate 10 is SOI substrate.It should be noted that usually, the present embodiment
Layout design go for based on various material substrates MOSFET design.
Specifically, the multi-fork finger grid structure also includes the first active area (not shown), the second active area (not shown)
And multiple active area (not shown) of connection first active area and the second active area.The first multi-fork finger grid structure
The the second strip grid 202, source region 40 and the drain region 50 in 20 is respectively positioned on the corresponding area of first active area
Domain；The equal position of the second strip grid 202, source region 40 and the drain region 50 in the second multi-fork finger grid structure 21
In the corresponding region of second active area；The body contact zone 30 is located at the corresponding region of described active area.I.e. described
The the second strip grid 202, source region 40 and the leakage in one active area and the first multi-fork finger grid structure 20
The region that area 50 is located coincides；Second strip in second active area and the second multi-fork finger grid structure 21
The region that grid 202, the source region 40 and the drain region 50 are located coincides；The corresponding region of described active area and the body
The area coincidence that contact area 30 is located.
Specifically, the source region 40 and the drain region 50 are by first in the first conductive type ion injection zone 90
Active area and the second active area carry out the ion implanting of the first conduction type and are formed；The body contact zone 30 to second by leading
An active area in electric types of ion injection zone 91 carries out the ion implanting of the second conduction type and is formed.
Specifically, the first multi-fork finger grid structure 20 is symmetrically dispersed in the second multi-fork finger grid structure 21
The two ends of the body contact zone 30.Second strip in the quantity of the body contact zone 30 and each multi-fork finger grid structure
The quantity of grid 202 is identical, and the body contact zone 30 is vertical with the first strip grid 201；And each described body contact zone
30 are located in the projection join line of the second strip grid 202 in the Semiconductor substrate 10 at its two ends.
Specifically, two the first strip grids 201 near the body contact zone 30 are contacted respectively across the body
Area 30, described two first strip grids 201 partly overlap with the body contact zone 30, and described two first strip grids
It is separated by certain spacing between 201.The first strip grid 201 partly overlaps with the body contact zone 30, can be to institute
State ion when body contact zone 30 carries out ion implanting to injecting to realize stopping, such that it is able to form effectively body contact zone, enter
And suppress floater effect.
Specifically, each the described drain region 50 in the first multi-fork finger grid structure 20 passes through respectively via contact hole 70
The short circuit of metal line layer 60, each described drain region 50 in the second multi-fork finger grid structure 21 passes through metal via contact hole 70
The short circuit of line layer 60；Leakage in drain region 50 in the first multi-fork finger grid structure 20 and the second multi-fork finger grid structure 21
Area 50 is in parallel by metal line layer via contact hole 70.In the case where wiring difficulty is not increased by the first multi-fork finger grid
Drain region 50 in structure 20 is in parallel by metal line layer with the drain region 50 in the second multi-fork finger grid structure 21, can be effective
Ground reduces drain region resistance, improves the performance of device, and reduces electric current to a certain extent in the ohmically power consumption in drain region.
Specifically, in the grid in the first multi-fork finger grid structure 20 and the second multi-fork finger grid structure 21
Grid is in parallel by metal line layer.In the case where wiring difficulty is not increased by the grid in the first multi-fork finger grid structure 20
Pole is in parallel by metal line layer with the grid in the second multi-fork finger grid structure 21, can be effectively reduced the grid of device
Resistance, while device radio-frequency performance is improved, reduces the noise caused by gate resistance；Simultaneously device can be significantly improved
Maximum oscillation frequency.It should be noted that the grid and more than the second interdigital grid in the first multi-fork finger grid structure 20
Grid in pole structure 21 is drawn by the first strip grid 201 away from the body contact zone 30, i.e., connecing away from the body
The top of first strip grid 201 in tactile area 30 forms the contact hole 70 of the connection grid and metal line layer and finally realizes described the
Grid in one multi-fork finger grid structure 20 is in parallel with the grid in the second multi-fork finger grid structure 21.
Specifically, in the first multi-fork finger grid structure 20 institute's active area 40, the second multi-fork finger grid structure
Institute's active area 40 and all of body contact zone 30 in 21 is interconnected together via contact hole 70 by metal line layer 60.Tool
The connected mode of body is that the described body contact zone 30 passes through one parallel to the first strip grid via contact hole 70
201 metal line layer 60 is connected, the interdigital grid more than 40, described second of the institute's active area in the first multi-fork finger grid structure 20
Institute's active area 40 in pole structure 21 is respectively via contact hole 70 by metal line layer 60 and parallel to the first strip grid
201 metal line layer 60 is connected.
Specifically, the layout design of multi-fork finger grid structure MOSFET can also include dummy gate 22, the void
Intend the two ends that grid 22 is located at respectively the first multi-fork finger grid structure 20 and the second multi-fork finger grid structure 21, and position
The region between described two first strip grids 201 in each multi-fork finger grid structure, with each multi-fork finger grid knot
The first strip grid 201 and the second strip grid 202 in structure is separated by certain spacing.
As shown in Fig. 2 Fig. 2 is structural representations of the Fig. 1 along AA ' sections.As shown in Figure 2, the Semiconductor substrate 10 is
SOI substrate, includes successively from the bottom to top backing bottom 101, oxygen buried layer 102 and top layer silicon 103；It is formed with the top layer silicon 103
The body contact zone 30 that body area 31 is connected with the body area 31 and positioned at the body area 31 away from the body contact zone 30 1
The isolation structure 80 of side；Grid is formed with the Semiconductor substrate 10, herein, the grid be the second strip grid 202, institute
Stating the second strip grid 202 includes the gate dielectric layer 2021 being incorporated in the Semiconductor substrate 10 and positioned at the gate dielectric layer
Gate material layers 2022 on 2021；The body contact zone 30 and the grid are respectively by contact hole 70 and the phase of metal line layer 60
Connection.The material of the gate dielectric layer 2021 can be silicon dioxide, silicon nitride or high K medium material etc., the grid material
The material of layer 2022 can be polysilicon or metal etc..It should be noted that different materials enumerated above are only the present invention
Several preferred versions, in actual production, be not limited to this.
It should be noted that the top of the second strip grid 202 and surrounding are formed with spacer medium layer (not shown),
The contact hole 70 is formed in the spacer medium layer, and the metal line layer 60 is formed at spacer medium layer top.
As shown in figure 3, Fig. 3 is structural representations of the Fig. 1 along BB ' sections.From the figure 3, it may be seen that the body area 31 will be each described
Source region 40 and each drain region 50 separate.
The manufacture method of the structure of the layout design of multi-fork finger grid structure MOSFET of the present invention at least includes following step
Suddenly：
Step one：Semi-conductive substrate is provided, active area is formed on the semiconductor substrate；
Step 2：Gate dielectric layer is grown in the Semiconductor substrate for be formed with active area；
Step 3：Gate material layers are formed on the gate dielectric layer；
Step 4：Ion implanting is carried out to the region corresponding to source region and drain region, the ion for being injected is the first conductive-type
The ion of type, the ion implanted regions of the first conduction type are the first conductive type ion injection zone 90 in Fig. 1；
Step 5：Ion implanting is carried out to the corresponding region of body contact zone, the ion for being injected is the second conduction type
Ion, the ion implanted regions of second conduction type are the second conductive type ion injection zone 91 in Fig. 1；
Step 6：Etching forms contact hole；
Step 7：Deposited metal forms the interconnection of metal electrode.
Specifically, the ion of first conduction type can be N-type ion, and now second conduction type from
Son is p-type ion.
Specifically, the ion of first conduction type can be p-type ion, and now second conduction type from
Son is N-type ion.
In sum, the present invention proposes a kind of layout design of multi-fork finger grid structure MOSFET, by being connect using body
The public method in tactile area, can improve body contact zone utilization rate, reduce parasitic capacitance, meanwhile, by the way of polygon connection, can
To realize relatively low gate resistance.More common body-contacted device is compared, the utilization rate of its active area is high, in identical total grid width bar
Under part, body contact zone domain area reduces half, can improve integrated level；Because intermediate area is that both sides active area is public, gold
Category line occupied area is reduced, and can reduce parasitic capacitance；Do not increase wiring difficulty in the case of realize both sides grid and
Connection, reduces resistance；The parallel connection that both sides drain is realized in the case where wiring difficulty is not increased, drain resistance is reduced；
Technique is just capable of achieving without the need for extra change；Described element layout structure method for designing has certain in radio circuit field
Using value.
The principle and its effect of above-described embodiment only illustrative present invention, it is of the invention not for limiting.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and the scope without prejudice to the present invention to above-described embodiment.Cause
This, such as those of ordinary skill in the art is complete with institute under technological thought without departing from disclosed spirit
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. a kind of multi-fork finger grid structure MOSFET, it is characterised in that include：Semiconductor substrate, the first multi-fork finger grid structure,
Second multi-fork finger grid structure, body contact zone, source region and drain region；
The first multi-fork finger grid structure includes with the second multi-fork finger grid structure：First of two parallel distributions
Shape grid and it is multiple between described two first strip grids and with the first strip grid Article 2 connected vertically
Shape grid；The Semiconductor substrate is divided into multiple regions by the first strip grid and the second strip grid, the source region and
Drain region is alternately distributed in the plurality of region；
The body contact zone is parallel to be distributed in the first multi-fork finger grid structure and the second multi-fork finger grid knot for multiple
Between structure, shared by the first multi-fork finger grid structure and the second multi-fork finger grid structure；
Source region in the first multi-fork finger grid structure passes through metal wire with the source region in the second multi-fork finger grid structure
Layer and body contact zone interconnection.
2. multi-fork finger grid structure MOSFET according to claim 1, it is characterised in that：Near the two of the body contact zone
The individual first strip grid is respectively across the body contact zone, described two first strip grids and the body contact zone part
Overlap, and be separated by certain spacing between described two first strip grids.
3. multi-fork finger grid structure MOSFET according to claim 1, it is characterised in that：The first multi-fork finger grid knot
Each described drain region in structure is respectively by metal line layer short circuit, each the described drain region in the second multi-fork finger grid structure
By metal line layer short circuit.
4. multi-fork finger grid structure MOSFET according to claim 3, it is characterised in that：The first multi-fork finger grid knot
Drain region in structure is in parallel by metal line layer with the drain region in the second multi-fork finger grid structure.
5. multi-fork finger grid structure MOSFET according to claim 1, it is characterised in that：The first multi-fork finger grid knot
Grid in structure is in parallel by metal line layer with the grid in the second multi-fork finger grid structure.
6. multi-fork finger grid structure MOSFET according to claim 1, it is characterised in that：The first multi-fork finger grid knot
Structure is distributed in the two ends of the body contact zone with the second multi-fork finger grid symmetrical configuration.
7. multi-fork finger grid structure MOSFET according to claim 6, it is characterised in that：The quantity of the body contact zone with
The quantity of the second strip grid in each multi-fork finger grid structure is identical, the body contact zone and first strip grid
It is extremely vertical；And each described body contact zone is located at the second strip grid projection on the semiconductor substrate at its two ends
On line.
8. multi-fork finger grid structure MOSFET according to claim 1, it is characterised in that：The first multi-fork finger grid knot
The institute's active area in institute's active area, the second multi-fork finger grid structure and all of body contact zone in structure passes through metal
Line layer is interconnected together.
9. multi-fork finger grid structure MOSFET according to claim 1, it is characterised in that：The first multi-fork finger grid knot
Structure and the second multi-fork finger grid structure include the gate dielectric layer being located in the Semiconductor substrate and are situated between positioned at the grid
Gate material layers on matter layer.
10. multi-fork finger grid structure MOSFET according to any one of claim 1 to 9, it is characterised in that：The multi-fork
Finger grid structure MOSFET also includes dummy gate, and the dummy gate is located at respectively the first multi-fork finger grid structure and institute
State the two ends of the second multi-fork finger grid structure, and the described two first strip grids in each multi-fork finger grid structure it
Between region, with each multi-fork finger grid structure in the first strip grid and the second strip grid be separated by necessarily
Spacing.
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| CN108735727B (en) * | 2017-04-14 | 2021-01-01 | 中芯国际集成电路制造(上海)有限公司 | Transistor layout structure, transistor and manufacturing method |
| CN117690923A (en) * | 2022-08-31 | 2024-03-12 | 长鑫存储技术有限公司 | Layout and memory of word line driver |
| CN117558749B (en) * | 2024-01-11 | 2024-05-03 | 英诺赛科（珠海）科技有限公司 | Gallium nitride device structure |
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| CN100433366C (en) * | 2002-03-22 | 2008-11-12 | 西利康尼克斯股份有限公司 | Structure of groove-grid MIS device and producing method thereof |
| CN101657901A (en) * | 2006-12-28 | 2010-02-24 | 马维尔国际贸易有限公司 | Geometry of MOS device with low on-resistance |
| CN101764136A (en) * | 2009-12-24 | 2010-06-30 | 中国科学院上海微***与信息技术研究所 | Interdigital structure capable of regulating channel current of vertical gate SOI CMOS devices |
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| US7851889B2 (en) * | 2007-04-30 | 2010-12-14 | Freescale Semiconductor, Inc. | MOSFET device including a source with alternating P-type and N-type regions |
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| CN100433366C (en) * | 2002-03-22 | 2008-11-12 | 西利康尼克斯股份有限公司 | Structure of groove-grid MIS device and producing method thereof |
| CN101657901A (en) * | 2006-12-28 | 2010-02-24 | 马维尔国际贸易有限公司 | Geometry of MOS device with low on-resistance |
| CN101764136A (en) * | 2009-12-24 | 2010-06-30 | 中国科学院上海微***与信息技术研究所 | Interdigital structure capable of regulating channel current of vertical gate SOI CMOS devices |
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