CN104899343B - Intersect grid structure MOSFET and multi-fork refers to the layout design of grid structure MOSFET - Google Patents
Intersect grid structure MOSFET and multi-fork refers to the layout design of grid structure MOSFET Download PDFInfo
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- CN104899343B CN104899343B CN201410077465.7A CN201410077465A CN104899343B CN 104899343 B CN104899343 B CN 104899343B CN 201410077465 A CN201410077465 A CN 201410077465A CN 104899343 B CN104899343 B CN 104899343B
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- 238000013461 design Methods 0.000 title abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 230000009514 concussion Effects 0.000 abstract description 6
- 230000010355 oscillation Effects 0.000 abstract description 6
- 230000008901 benefit Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of intersection grid structure MOSFET and multi-fork refers to the layout design of grid structure MOSFET, and the layout design for intersecting grid structure MOSFET includes：Semiconductor substrate, decussation grid structure, source region and drain region；The decussation grid structure includes the first strip grid and second strip grid vertical with first strip grid, and the semiconductor substrate is divided into four regions by first strip grid and the second strip grid；The source region and drain region are alternately arranged in four regions.The present invention can improve the utilization rate of active area, increase driving current, reduce gate resistance, improve maximum concussion frequency；Using grid structure is intersected, using spiral distribution source electrode and drain electrode, chip area is taken full advantage of, and can realize that multi-fork refers to grid structure, can meet the needs of design circuit is to device；If connected simultaneously using four ends to the connection of grid, gate resistance can be effectively reduced, to significantly improve the power gain and maximum oscillation frequency of device.
Description
Technical field
The present invention relates to a kind of MOSFET layout designs, refer to grid more particularly to a kind of intersection grid structure MOSFET and multi-fork
The layout design of structure MOSFET.
Background technology
With the continuous development of semiconductor technology, mos field effect transistor（MOSFET）Extensive use
In IC design.MOSFET is voltage-controlled device, when gate bias voltage is higher than the threshold voltage of device, MOSFET ditches
Road forms inversion layer, and conductive channel is formed between source electrode and drain electrode.When grid voltage is less than threshold voltage, conductive channel closes
Close, device by.In break-over of device, apply signal in grid or source electrode, drain electrode has corresponding signal output.Semiconductor skill
When art is applied to radio frequency arts, since ghost effect can influence the property of device such as the influence of dead resistance, parasitic capacitance
Energy.The continuous improvement of semiconductor technology technique so that the cutoff frequency of device is also continuously improved.
Radio-frequency technique often requires that higher power transfer characteristic.Maximum concussion frequency and ghost effect are closely bound up, especially
It is influenced by gate resistance, source and drain resistance etc. it is huge.And the reduction of dead resistance needs continuing to optimize for layout design.Therefore right
It in while device is continuously improved by frequency, needs to optimize domain, reduces the ghost effect of device, be continuously improved
The power gain and maximum oscillation frequency of device.
In view of disadvantages described above in the prior art, the object of the present invention is to provide a kind of decussation grid structure MOSFET
And multi-fork refers to the layout design of grid structure MOSFET, to improve the utilization rate of active area, increases driving current, reduces gate resistance,
Improve maximum concussion frequency.
Invention content
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of intersection grid structure MOSFET and
Multi-fork refers to the layout design of grid structure MOSFET, to improve the utilization rate of active area, increases driving current, reduces gate resistance, carry
High maximum concussion frequency.
In order to achieve the above objects and other related objects, the present invention provides a kind of domain of intersection grid structure MOSFET and sets
Meter, the layout design include：
Semiconductor substrate, decussation grid structure, source region and drain region；
The decussation grid structure includes the first strip grid and second strip grid vertical with first strip grid,
The semiconductor substrate is divided into four regions by first strip grid and the second strip grid；The source region and drain region are alternately arranged
In four regions.
A kind of preferred embodiment of the layout design of intersection grid structure MOSFET as the present invention, the decussation grid
The end of structure is both ends interconnection, the interconnection of three ends or the interconnection of four ends.
A kind of preferred embodiment of the layout design of intersection grid structure MOSFET as the present invention, the decussation grid
Structure includes the electrode layer for being incorporated into the dielectric layer of the semiconductor substrate surface and being incorporated into the dielectric layer surface.
A kind of preferred embodiment of the layout design of intersection grid structure MOSFET as the present invention, the source region and drain region
Shape is rectangle.
A kind of preferred embodiment of the layout design of intersection grid structure MOSFET as the present invention, the source region and drain region
Shape is the frame shape of the edge distribution along the decussation grid structure.
As the present invention intersection grid structure MOSFET layout design a kind of preferred embodiment, respectively the source region pass through metal
Interconnection line short circuit, respectively the drain region pass through metal interconnection wire short circuit.
The present invention also provides the layout designs that a kind of multi-fork refers to grid structure MOSFET, including：
Semiconductor substrate, multi-fork refer to grid structure, source region and drain region；
It includes the first strip grid and multiple second strip grids vertical with first strip grid that the multi-fork, which refers to grid structure,
The semiconductor substrate is divided into multiple regions by first strip grid and the second strip grid；The source region and drain region are alternately arranged
In the multiple region.
Multi-fork as the present invention refers to a kind of preferred embodiment of the layout design of grid structure MOSFET, and the multi-fork refers to grid knot
Multiple ends of structure are part interconnection or all interconnection.
Multi-fork as the present invention refers to a kind of preferred embodiment of the layout design of grid structure MOSFET, and the multi-fork refers to grid knot
Structure includes the electrode layer for being incorporated into the dielectric layer of the semiconductor substrate surface and being incorporated into the dielectric layer surface.
Multi-fork as the present invention refers to a kind of preferred embodiment of the layout design of grid structure MOSFET, and respectively the source region passes through gold
Belong to interconnection line short circuit, respectively the drain region passes through metal interconnection wire short circuit.
As described above, the present invention provides a kind of intersection grid structure MOSFET and multi-fork refers to the domain of grid structure MOSFET and sets
Meter, the layout design for intersecting grid structure MOSFET include：Semiconductor substrate, decussation grid structure, source region and drain region；
The decussation grid structure includes the first strip grid and second strip grid vertical with first strip grid, and described first
The semiconductor substrate is divided into four regions by strip grid and the second strip grid；The source region and drain region are alternately arranged in described four
A region.The present invention compares common interdigitation device, can improve the utilization rate of active area, increases driving current, reduces grid
Resistance improves maximum concussion frequency；The present invention is using grid structure is intersected, using spiral distribution source electrode and drain electrode, as far as possible
Chip area is taken full advantage of, and can realize that multi-fork refers to（multi-finger）Structure can meet design circuit to device
Demand；The modes such as one end connection, both ends connection, the connection of three ends, the connection of four ends may be used in connection to grid simultaneously；Using four
When the connection of end, gate resistance can be effectively reduced, therefore the power gain and maximum oscillation frequency of device can be significantly improved.
Description of the drawings
Fig. 1 is shown as the structural schematic diagram of the layout design of the intersection grid structure MOSFET of the present invention.
Fig. 2 is shown as the structural schematic diagram in the sections layout design A-A ' of the intersection grid structure MOSFET in Fig. 1 of the present invention.
Fig. 3 is shown as the structural schematic diagram in the sections layout design B-B ' of the intersection grid structure MOSFET in Fig. 1 of the present invention.
Fig. 4 is shown as the schematic equivalent circuit of the layout design of the intersection grid structure MOSFET of the present invention.
Fig. 5 is shown as the structural representation of the layout design another embodiment of the intersection grid structure MOSFET of the present invention
Figure.
Fig. 6 is shown as the structural schematic diagram that multi-fork of the invention refers to the layout design of grid structure MOSFET.
Component label instructions
Specific implementation mode
Illustrate that embodiments of the present invention, those skilled in the art can be by this specification below by way of specific specific example
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Please refer to Fig.1~Fig. 6.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, package count when only display is with related component in the present invention rather than according to actual implementation in schema then
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can be a kind of random change, and its
Assembly layout kenel may also be increasingly complex.
Embodiment 1
Fig. 1~Fig. 3 is shown as the structural schematic diagram of the layout design of the intersection grid structure MOSFET of the present embodiment, wherein
Fig. 2 is the structural schematic diagram in the sections A-A ' in Fig. 1, and Fig. 3 is the structural schematic diagram in the sections B-B ' in Fig. 1.
Fig. 4 is then shown as the equivalent circuit diagram of the intersection grid structure MOSFET of the present embodiment.
As shown in Figure 1 to 4, the present embodiment provides a kind of layout design of intersection grid structure MOSFET, the domain is set
Meter includes：
Semiconductor substrate, decussation grid structure 10, source region 20 and drain region 30；
The decussation grid structure 10 includes the first strip grid 101 and vertical with first strip grid 101 the
The semiconductor substrate is divided into four regions by two strip grids 102, first strip grid, 101 and second strip grid 102；It is described
Source region 20 and drain region 30 are alternately arranged in four regions.
As an example, the semiconductor substrate can be SOI substrate, body silicon substrate, GaAs substrates, GaN substrate, InP linings
Bottom etc., in the present embodiment, the semiconductor substrate be SOI substrate, the SOI substrate include silicon substrate 90, oxygen buried layer 80 with
And top layer silicon.It should be noted that usually, the layout design of the present embodiment can be adapted for based on a variety of materials substrate
MOSFET is designed.
As an example, the end of the decussation grid structure 10 is both ends interconnection, the interconnection of three ends or the interconnection of four ends.
Described in the present embodiment, the end of the decussation grid structure 10 interconnects for four ends（The metal interconnecting layer is unillustrated）,
This design can effectively reduce gate resistance, can significantly improve the power gain and maximum oscillation frequency of device.
As shown in Fig. 2, as an example, the decussation grid structure 10 includes being incorporated into the semiconductor substrate surface
Dielectric layer 103 and be incorporated into the electrode layer 104 on 103 surface of the dielectric layer.The dielectric layer 103 can be titanium dioxide
The materials such as silicon, silicon nitride, the electrode layer 104 can be the materials such as metal electrode, polysilicon.It should be noted that the above institute
The different materials enumerated are only several preferred embodiments of the present invention, and in actual production, it's not limited to that.
As shown in figure 3, the lower section of the decussation grid structure 10 is channel region 70, the channel region 70 will each source region
20 and respectively the drain region 30 is spaced from each other.
As shown in Figure 1, as an example, the source region 20 and the shape in drain region 30 are rectangle.
As an example, respectively the source region 20 is by 40 short circuit of metal interconnection wire, respectively the drain region 30 is short by metal interconnection wire 40
It connects, wherein the metal interconnection wire 40 is by contact hole 50 and the respectively source region 20 or respectively the drain region 30 is connect.
As an example, the layout design of the present embodiment further includes being located at device periphery, it to be used for the isolation structure of device isolation
60.The isolation structure 60 can be such as fleet plough groove isolation structure STI.
Fig. 4 is shown as the equivalent circuit diagram of the intersection grid structure MOSFET of the present embodiment, using the intersection grid of the present embodiment
The layout design of structure MOSFET can be equivalent to 4 MOSFET and be connected in parallel, and in fact, the present embodiment only needs to make
Two source electrodes and two drain electrodes, greatly increase the utilization rate of active area, and increase the driving current of MOSFET.
Embodiment 2
As shown in figure 5, the present embodiment provides a kind of layout design of intersection grid structure MOSFET, basic structure is as implemented
Example 1, wherein the source region 20 and the frame shape that the shape in drain region 30 is the edge distribution along the decussation grid structure 10.
The source region 20 of different area may be implemented in the layout design of this structure and drain region 30 is designed, to meet the various performances of MOSFET
It is required that the alternative of MOSFET performances can be greatly improved.
Embodiment 3
As shown in fig. 6, the present embodiment provides the layout designs that a kind of multi-fork refers to grid structure MOSFET, including：
Semiconductor substrate, multi-fork refer to grid structure, source region 20 and drain region 30；
It includes the first strip grid 101 and vertical with first strip grid 101 multiple second that the multi-fork, which refers to grid structure,
The semiconductor substrate is divided into multiple regions by strip grid 102, first strip grid, 101 and second strip grid 102；The source
Area 20 and drain region 30 are alternately arranged in the multiple region.
As an example, multiple ends that the multi-fork refers to grid structure are part interconnection or all interconnection.The multi-fork is referred to
When multiple ends of grid structure carry out part interconnection or all interconnection, especially whole interconnection, gate resistance can be effectively reduced,
The power gain and maximum oscillation frequency of device can be significantly improved.
As an example, the multi-fork refer to grid structure include be incorporated into the semiconductor substrate surface dielectric layer 103 and
It is incorporated into the electrode layer 104 on 103 surface of the dielectric layer.The dielectric layer 103 can be the materials such as silica, silicon nitride,
The electrode layer 104 can be the materials such as metal electrode, polysilicon.It should be noted that different materials enumerated above are only
For several preferred embodiments of the present invention, in actual production, it's not limited to that.
As an example, respectively the source region 20 is by metal interconnection wire short circuit, respectively the drain region 30 passes through metal interconnection wire short circuit（Its
In, peripheral metal interconnection wire is unillustrated）.
It should be noted that the quantity of the second strip grid 102 described in the present embodiment can be increased and decreased as needed, and
It is not limited to this, in addition, the layout design others component that the multi-fork of the present embodiment refers to grid structure MOSFET can refer to embodiment
1, no longer wadding is stated herein.
As described above, the present invention provides a kind of intersection grid structure MOSFET and multi-fork refers to the domain of grid structure MOSFET and sets
Meter, the layout design for intersecting grid structure MOSFET include：Semiconductor substrate, decussation grid structure 10, source region 20 and
Drain region 30；The decussation grid structure 10 includes the first strip grid 101 and vertical with first strip grid 101 second
The semiconductor substrate is divided into four regions by strip grid 102, first strip grid, 101 and second strip grid 102；The source
Area 20 and drain region 30 are alternately arranged in four regions.The present invention compares common interdigitation device, can improve active area
Utilization rate, increase driving current, reduce gate resistance, improve maximum concussion frequency；The present invention is using grid structure is intersected, using spiral shell
Shape distribution source electrode and drain electrode are revolved, takes full advantage of chip area as far as possible, and can realize that multi-fork refers to（multi-finger）Knot
Structure can meet the needs of design circuit is to device；One end connection, both ends connection, three ends may be used in connection to grid simultaneously
The modes such as connection, the connection of four ends；When being connected using four ends, gate resistance can be effectively reduced, therefore device can be significantly improved
Power gain and maximum oscillation frequency.So the present invention effectively overcomes various shortcoming in the prior art and has height and produce
Industry utility value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology can all carry out modifications and changes to above-described embodiment without violating the spirit and scope of the present invention.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. a kind of domain intersecting grid structure MOSFET, which is characterized in that including：
Semiconductor substrate, decussation grid structure, source region and drain region；
The decussation grid structure includes the first strip grid and second strip grid vertical with first strip grid, described
The semiconductor substrate is divided into four regions by the first strip grid and the second strip grid；The source region and drain region are alternately arranged in institute
State four regions.
2. the domain according to claim 1 for intersecting grid structure MOSFET, it is characterised in that：The decussation grid knot
The end of structure is both ends interconnection, the interconnection of three ends or the interconnection of four ends.
3. the domain according to claim 1 for intersecting grid structure MOSFET, it is characterised in that：The decussation grid knot
Structure includes the electrode layer for being incorporated into the dielectric layer of the semiconductor substrate surface and being incorporated into the dielectric layer surface.
4. the domain according to claim 1 for intersecting grid structure MOSFET, it is characterised in that：The source region and the shape in drain region
Shape is rectangle.
5. the domain according to claim 1 for intersecting grid structure MOSFET, it is characterised in that：The source region and the shape in drain region
Shape is the frame shape of the edge distribution along the decussation grid structure.
6. the domain according to claim 1 for intersecting grid structure MOSFET, it is characterised in that：Respectively the source region is mutual by metal
On line short circuit, respectively the drain region pass through metal interconnection wire short circuit.
7. a kind of multi-fork refers to the domain of grid structure MOSFET, which is characterized in that including：
Semiconductor substrate, multi-fork refer to grid structure, source region and drain region；
It includes the first strip grid and multiple second strip grids vertical with first strip grid that the multi-fork, which refers to grid structure, described
The semiconductor substrate is divided into multiple regions by the first strip grid and the second strip grid；The source region and drain region are alternately arranged in institute
State multiple regions.
8. multi-fork according to claim 7 refers to the domain of grid structure MOSFET, it is characterised in that：The multi-fork refers to grid structure
Multiple ends be part interconnection or all interconnection.
9. multi-fork according to claim 7 refers to the domain of grid structure MOSFET, it is characterised in that：The multi-fork refers to grid structure
Including being incorporated into the dielectric layer of the semiconductor substrate surface and being incorporated into the electrode layer of the dielectric layer surface.
10. multi-fork according to claim 7 refers to the domain of grid structure MOSFET, it is characterised in that：Respectively the source region passes through gold
Belong to interconnection line short circuit, respectively the drain region passes through metal interconnection wire short circuit.
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| CN101764136A (en) * | 2009-12-24 | 2010-06-30 | 中国科学院上海微***与信息技术研究所 | Interdigital structure capable of regulating channel current of vertical gate SOI CMOS devices |
| CN102142462A (en) * | 2011-02-25 | 2011-08-03 | 北京大学 | Power MOS transistor of asymmetric structure and array thereof |
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| CN102956647A (en) * | 2011-08-31 | 2013-03-06 | 中国科学院微电子研究所 | Semiconductor device and manufacture method thereof |
| CN103178116A (en) * | 2013-03-15 | 2013-06-26 | 中国科学院宁波材料技术与工程研究所 | Transistor with modified grid structure |
Family Cites Families (3)
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|---|---|---|---|---|
| JP2006261437A (en) * | 2005-03-17 | 2006-09-28 | Mitsumi Electric Co Ltd | Semiconductor device |
| KR20100067874A (en) * | 2008-12-12 | 2010-06-22 | 주식회사 동부하이텍 | Mosfet device |
| KR101127501B1 (en) * | 2010-05-24 | 2012-03-26 | (주) 트리노테크놀로지 | Power semiconductor device with trench gate structure |
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- 2014-03-04 CN CN201410077465.7A patent/CN104899343B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101764136A (en) * | 2009-12-24 | 2010-06-30 | 中国科学院上海微***与信息技术研究所 | Interdigital structure capable of regulating channel current of vertical gate SOI CMOS devices |
| CN102339850A (en) * | 2010-07-19 | 2012-02-01 | 中国人民解放军国防科学技术大学 | Octagonal latticed metal-oxide-semiconductor field-effect transistor (MOSFET) power tube layout structure |
| CN102142462A (en) * | 2011-02-25 | 2011-08-03 | 北京大学 | Power MOS transistor of asymmetric structure and array thereof |
| CN102956647A (en) * | 2011-08-31 | 2013-03-06 | 中国科学院微电子研究所 | Semiconductor device and manufacture method thereof |
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