CN101728382A - Power device chip - Google Patents
Power device chip Download PDFInfo
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- CN101728382A CN101728382A CN200810224582A CN200810224582A CN101728382A CN 101728382 A CN101728382 A CN 101728382A CN 200810224582 A CN200810224582 A CN 200810224582A CN 200810224582 A CN200810224582 A CN 200810224582A CN 101728382 A CN101728382 A CN 101728382A
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Abstract
The embodiment of the invention discloses a power device chip and aims to improve the current capability of the power device chip. The chip comprises a plurality of unit cells which are in the same shape and are seamlessly jointed on a plane; a unit cell grid medium layer on the plane is in a shape that the perimeter of the unit cell grid medium layer is larger than the perimeter of a square when the area of the unit cell grid medium layer is same as that of the square, because the ratio of the width to the length of a groove in a unit area is an important factor for deciding the current capability of the chip. Under the condition that the process is fixed, the length of the groove is fixed and the width of the groove is approximately similar to the perimeter of the unit cells, thus the scheme provided by the embodiment of the invention improves the current capability of the power device chip.
Description
Technical field
The present invention relates to the chip manufacturing field, relate in particular to a kind of power device chip.
Background technology
It is basic structure that cellular is adopted in design of some chip at present and manufacturing, as DMOS device DMOS is the popular Power MOSFET of current semiconductor circle (Power metallic oxidesemiconductor field effecttransistor, power transistor) chip fabrication techniques, its basic structure are cellular.Adopting cellular is that the chip of basic structure is also just like IGBT (Insulated Gate BipolarTransistor), insulated gate bipolar power tube etc.Two types of kind closed Cell of cellular (closo cellular) and striped cell (bar shaped cellular).In the DMOS design, common closed cellular is: the cellular of regular hexagon in the plane as shown in Figure 1, or square cellular as shown in Figure 2.As foursquare housing, Source (source region barrier zones 14), Contact (contact hole 16) are then in the centre of gate dielectric layer 12 with gate dielectric layer 12.Chip comprises a plurality of cellulars 10 that are shaped as square (or regular hexagon) and seamless connection in the plane, and shown in Fig. 4 A or 4B, each adjacent cellular gate dielectric layer 12 each other is that the public grid dielectric layer of adjacent cellular is shared.
The cellular that in the prior art no matter is chip is regular hexagon or square, the power device chip current capacity all a little less than.
Summary of the invention
The embodiment of the invention provides a kind of power device chip, to improve the power device chip current capacity.
The embodiment of the invention provides following technical scheme:
A kind of power device chip comprises the identical and cellular of seamless connection in the plane of a plurality of shapes, described in the plane cellular gate dielectric layer be shaped as when identical girth greater than the shape of square girth with area.
The breadth length ratio of raceway groove is the key factor of decision chip current ability in the unit are.Under the certain situation of technology, because the length of raceway groove is fixed, the width of raceway groove can be approximated to be the girth of cellular, so scheme that adopts the embodiment of the invention to provide, promptly in the plane the cellular gate dielectric layer be shaped as when identical girth greater than the shape of square girth with area, make the breadth length ratio of raceway groove become big, therefore improve the power device chip current capacity.
Description of drawings
Fig. 1 is the bottom view of regular hexagon cellular in the prior art;
Fig. 2 is the bottom view of square cellular in the prior art;
Fig. 3 is the profile of square cellular in the prior art;
Fig. 4 A, 4B are the chip bottom view that comprises a plurality of square cellulars in the prior art;
Fig. 5 is the bottom view of parallelogram B cellular in the example of the present invention;
Fig. 6 is the bottom view of rectangle cellular in the example of the present invention;
Fig. 7 is the bottom view of trapezoidal cellular in the example of the present invention;
Fig. 8 is the bottom view of example intermediate cam shape cellular of the present invention;
Fig. 9 is the bottom view of equilateral triangle cellular in the example of the present invention.
Embodiment
The embodiment of the invention provides a kind of chip, this chip comprises the identical and cellular of seamless connection in the plane of a plurality of shapes, the cellular gate dielectric layer is shaped as when identical with area girth greater than the shape of square girth in the plane, as: the parallelogram except that square, triangle, shape such as trapezoidal, these shapes when identical with area girth greater than the shape of square girth.The shape of cellular gate dielectric layer 12 as shown in Figure 5, for adjacent both sides angle be 45 the degree or 135 the degree parallelogram B, the area of square A parallelogram B equally all is a
2, the foursquare length of side is 4a, parallelogram B is under the precondition of a in a pair of length of side, if area is a equally
2Then parallelogram B girth is about 4.828a, under the certain situation of technology, the length of the raceway groove of square and parallelogram B is identical (being the height h among Fig. 3), like this under area identical, it is about 20.7% that the girth of parallelogram B has increased, and the raceway groove length-width ratio of parallelogram B is bigger by 20.7% than the raceway groove length-width ratio of square A, so the MOSFET current capacity is improved.
Be that example is analyzed explanation only above, and remove the parallelogram outside the square, be under the identical situation of area with parallelogram B, girth is all greater than square, rectangle as shown in Figure 6, thus cellular be shaped as rectangle the time, the MOSFET current capacity also is improved.As shown in Figure 7 trapezoidal under the situation identical with area, girth is greater than square, and the MOSFET current capacity also is improved.Be triangle as shown in Figure 8 under the identical situation of area, girth is also greater than square, and the MOSFET current capacity also is improved.In order to reduce processing technology, the shape of cellular can be equilateral triangle as shown in Figure 9.
Cellular in the embodiment of the invention can be closo cellular or bar shaped cellular, and the gate dielectric layer of cellular can be polycrystalline silicon medium layer or Alpha's silicon dielectric layer.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. a power device chip is characterized in that, described chip comprises the identical and cellular of seamless connection in the plane of a plurality of shapes, described in the plane cellular gate dielectric layer be shaped as when identical girth greater than the shape of square girth with area.
2. chip as claimed in claim 1 is characterized in that, described cellular gate dielectric layer be shaped as parallelogram except that square.
3. chip as claimed in claim 2 is characterized in that, the adjacent both sides angle that is shaped as of described cellular gate dielectric layer is 45 degree or 135 parallelogram of spending.
4. chip as claimed in claim 2 is characterized in that, described cellular gate dielectric layer be shaped as rectangle.
5. chip as claimed in claim 1 is characterized in that being shaped as of described cellular gate dielectric layer is trapezoidal.
6. chip as claimed in claim 1 is characterized in that, described cellular gate dielectric layer be shaped as triangle.
7. chip as claimed in claim 6 is characterized in that, described cellular gate dielectric layer be shaped as equilateral triangle.
8. chip as claimed in claim 1 is characterized in that, described cellular is closo cellular or bar shaped cellular.
9. chip as claimed in claim 1 is characterized in that, the gate dielectric layer of described cellular is polycrystalline silicon medium layer or Alpha's silicon dielectric layer.
10. chip as claimed in claim 1 is characterized in that, also comprises: Resistance, source region and contact hole, Resistance, described source region and contact hole are in the centre of gate dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810224582A CN101728382A (en) | 2008-10-21 | 2008-10-21 | Power device chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810224582A CN101728382A (en) | 2008-10-21 | 2008-10-21 | Power device chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101728382A true CN101728382A (en) | 2010-06-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810224582A Pending CN101728382A (en) | 2008-10-21 | 2008-10-21 | Power device chip |
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| CN (1) | CN101728382A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102339850A (en) * | 2010-07-19 | 2012-02-01 | 中国人民解放军国防科学技术大学 | Octagonal latticed metal-oxide-semiconductor field-effect transistor (MOSFET) power tube layout structure |
| CN103636002A (en) * | 2011-05-19 | 2014-03-12 | 惠普发展公司，有限责任合伙企业 | Device active channel length/width greater than channel length/width |
| CN103579323B (en) * | 2013-11-14 | 2016-01-20 | 电子科技大学 | A kind of wide cellular insulated gate bipolar transistor |
| CN107680967A (en) * | 2017-10-25 | 2018-02-09 | 嘉兴奥罗拉电子科技有限公司 | Power semiconductor chip and forming method thereof |
-
2008
- 2008-10-21 CN CN200810224582A patent/CN101728382A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102339850A (en) * | 2010-07-19 | 2012-02-01 | 中国人民解放军国防科学技术大学 | Octagonal latticed metal-oxide-semiconductor field-effect transistor (MOSFET) power tube layout structure |
| CN103636002A (en) * | 2011-05-19 | 2014-03-12 | 惠普发展公司，有限责任合伙企业 | Device active channel length/width greater than channel length/width |
| CN103636002B (en) * | 2011-05-19 | 2016-10-26 | 惠普发展公司，有限责任合伙企业 | Device active channel length-width ratio more than raceway groove length-width ratio |
| US9773782B2 (en) | 2011-05-19 | 2017-09-26 | Hewlett-Packard Development Company, L.P. | Transistor having an active channel region |
| US10170466B2 (en) | 2011-05-19 | 2019-01-01 | Hewlett-Packard Development Company, L.P. | Device having an active channel region |
| CN103579323B (en) * | 2013-11-14 | 2016-01-20 | 电子科技大学 | A kind of wide cellular insulated gate bipolar transistor |
| CN107680967A (en) * | 2017-10-25 | 2018-02-09 | 嘉兴奥罗拉电子科技有限公司 | Power semiconductor chip and forming method thereof |
| CN107680967B (en) * | 2017-10-25 | 2024-04-26 | 嘉兴奥罗拉电子科技有限公司 | Power semiconductor chip and forming method thereof |
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Application publication date: 20100609 |