CN104409459A

CN104409459A - Octagonal latticed MOSFET power tube layout structure

Info

Publication number: CN104409459A
Application number: CN201410585226.2A
Authority: CN
Inventors: 王志鹏
Original assignee: CHANGSHA JINGJIA MICROELECTRONIC Co Ltd
Current assignee: CHANGSHA JINGJIA MICROELECTRONIC Co Ltd
Priority date: 2014-10-28
Filing date: 2014-10-28
Publication date: 2015-03-11

Abstract

A large-dimension MOSFET is usually used in an integrated circuit as a power device, and a conventional interdigital MOSFET power tube layout structure is quite low in area efficiency and also has the defects of large conduction resistance, large parasitic capacitance, incapability of satisfying layout design rules and the like. For the purpose of solving the problems, the invention discloses an octagonal latticed MOSFET power tube layout structure. An active area is divided into grid arrays by use of a grid composed of octagonal polysilicon strips, the sources/drains of adjacent MOSFETs in each direction can be shared, the area utilization rate is improved, and the problem of contact of back gates in a MOSFET is ingeniously solved by use of the area composed of adjacent octagonal bevel edges at the same time. The basis units of the octagonal latticed MOSFET power tube disclosed by the invention are each composed of the active area, source area contact holes, drain area contact holes, back gate contact holes, the polysilicon strips and metal coils, and the integral MOSFET layout structure is realized by splicing the multiple basic units.

Description

A kind of octagon latticed MOSFET power tube domain structure

Technical field

The invention belongs to IC Layout field, relate generally to a kind of domain topological structure of large scale MOSFET power tube, refer in particular to the domain implementation of the latticed MOSFET power tube of a kind of octagon.

Background technology

In the integrated circuit such as Switching Power Supply, low dropout voltage regulator, large-sized transistor is through being often used as high-current switch or high power device.In order to be distinguished with low-power or small signal device, the device designed for this kind of application is specially called power tube, mainly contains bipolar transistor and field-effect transistor two kinds.Compared with bipolar transistor, field-effect transistor has that required driving power is little, device power capacity is large and the advantage such as processing compatibility is good, applies very extensive.

The MOSFET used as power device needs larger size usually.Analyzed to be used as the MOSFET power tube of switch, MOSFET is input as capacitive network, must carry out charge and discharge during driving element to input capacitance, driving be capacitive load.Therefore, the essence of driven MOS FET is exactly that drive circuit produces pulse signal source, carries out charge and discharge to its grid capacitance, and makes the control procedure that it opens or turn off under the gate charge of regulation or corresponding threshold voltage of the grid.Certainly exist certain conducting resistance due to during power tube conducting, this can bring certain conduction loss, thus affects the conversion efficiency of power supply.In order to obtain higher conversion efficiency, then must adopt the switching tube of low on-resistance, low conducting resistance be obtained and just must adopt large-sized power tube.And in fact, when doing other function and using, there is above-mentioned problem in MOSFET power tube too.

The area efficiency of MOSFET domain is very important.Use large-sized MOSFET power tube, although reduce the conducting resistance of power tube in theory, but MOSFET power tube will take very large chip area in domain manufacturing process, metal connecting line and bonding wire resistance affect very large on final conduction resistance value, also can introduce larger parasitic capacitance simultaneously, have a strong impact on the response speed of MOSFET power tube.The MOSFET power tube domain of conventional interdigital structure, as shown in Figure 1, its performance no doubt increases, but has to sacrifice the problem that larger area solves source/drain contact and backgate contact, adds the cost of chip.

Summary of the invention

As mentioned before, the interdigital MOSFET power tube of the routine shown in Fig. 1 structure, chip area utilance is lower, parasitic capacitance and resistance larger.For this problem, the invention discloses a kind of octagon latticed MOSFET power tube domain structure, as shown in Figure 2, its major technique thought is presented as its structural representation:

1, by using the grid of octagon polysilicon strip composition that active area is divided into grid array, the source/drain achieving adjacent mos FET shares, and improves area utilization;

2, in the grid array that octagon polysilicon strip forms, little foursquare net region can use as backgate contact, and only need the metal wound wire using through hole to be connected source contact hole with directly over it to connect, solve backgate contact and the larger problem of source/drain distance in interdigital structure cleverly, do not increase extra wiring expenditure, further increase area utilization.

For the structure of the interdigital MOSFET power tube of Fig. 1, the MOSFET power tube major technique Advantages found of octagon network following several in:

1, octagon network, because of sharing and the ingenious solution of backgate contact problems of its source/drain, larger improves chip area utilance, and parasitic capacitance and resistance decrease, and makes the service behaviour of MOSFET power tube obtain larger raising;

2, in octagon fenestral fabric, all figures are 0 °, 45 °, 90 ° or 135 ° of placements, there is not the figure of other angle, therefore there is not domain lattice point mistake;

3, the reduction of octagon network area effectively reduces chip cost;

4, octagon network comparatively interdigital structure compare there is better domain fillibility, its effect makes the mutual conductance of MOSFET power tube improve, and MOSFET power tube operating efficiency is higher.

Accompanying drawing explanation

Fig. 1 interdigital structure MOSFET power tube schematic diagram;

The domain schematic diagram of the latticed MOSFET power tube of Fig. 2 octagon disclosed by the invention;

In new structure shown in Fig. 3 Fig. 2, active area covers the schematic diagram of polysilicon strip mode;

Fig. 4 is for PMOS, and N trap is arranged, P+ injects and the mode schematic diagram of N+ injection;

The domain summary step of the latticed MOSFET elementary cell of Fig. 5 octagon disclosed by the invention;

The area efficiency of the latticed MOSFET domain structure of Fig. 6 octagon disclosed by the invention and interdigitated domain structure contrasts.

Embodiment

Below in conjunction with accompanying drawing, describe octagon disclosed by the invention latticed MOSFET power tube domain structure in detail.

The elementary cell of the latticed MOSFET power tube of octagon is made up of active area, polysilicon strip, source contact hole, drain contact hole, backgate contact hole and metal wound wire, and the domain structure of power MOSFET splices realization by elementary cell.Wherein, polysilicon strip is that a straight flange is longer, the eight-sided formation that hypotenuse is shorter, by the splicing of four such octagon polysilicon strip symmetries and adjacent straight flange overlap, be formed centrally a less square area of area wherein; Active area covers the region in each octagon and the region in little square, and the straight flange of octagon polysilicon strip, but does not cover the hypotenuse of polycrystalline octagon polysilicon strip, and the injection mode of active area as shown in Figure 3; Be positioned in source contact hole in two diagonal zones in four octagon active areas, drain contact hole is positioned in two other diagonal zones; Metal wound wire, as the arrangements of " W ", uses metal wound wire to connect source contact hole and as the source electrode of MOSFET, metal wound wire connects the drain electrode of drain contact hole as MOSFET; Backgate contact hole need be placed in the region of little square active area, and the little square area of all placement backgate contact holes is all the region that the metal wound wire being connected source contact hole covers; For PMOS power tube, for typical N trap CMOS technology, PMOS needs to be produced in N trap, will have the injection of P+ simultaneously.One of them elementary cell, the injection mode of the arrangement of N trap and P+ as shown in Figure 4, active area in little square contacts as the trap of PMOS, and need N+ to inject in little square area, and the ingenious realization of such trap contact just, make elementary cell large-arealy to repeat to call, without the need to extra trap attaching space, effectively raise area utilization, and these arrange the generation that trap contact closely largely avoid latch-up.

Fig. 5 gives the summary step in the layout generation procedure of the latticed MOSFET elementary cell of octagon disclosed by the invention.Fig. 5 A has been the figure after the placement of octagon polysilicon strip and source/drain/backgate are injected, and Fig. 5 B has been the figure after metal wound wire, and Fig. 5 C has been the figure after each contact hole.

On the basis realizing the latticed MOSFET elementary cell of octagon, utilize the repeatability of elementary cell figure, latticed for multiple octagon MOSFET elementary cell is stitched together, make its straight flange overlapping, and the both sides of straight flange are respectively injection region, source and leak injection region arbitrarily, can realize extendible large scale MOSFET.

Contrast interdigitated MOSFET, the area utilization of octagon fenestral fabric increases substantially.Fig. 6 is under certain CMOS technology, and the area efficiency of octagon disclosed by the invention latticed MOSFET power tube domain structure and interdigitated domain structure contrasts.Adopt 10 groups of structures often organizing 10 10 μm/0.35 μm of MOSFET for the MOSFET of 1000 μm/0.35 μm, interdigital structure A, place backgate contact between group, its area overhead is 3100 μm ²; Interdigital structure B adopts 10 groups of structures often organizing 20 5 μm/0.35 μm of MOSFET, and place backgate contact between group, its area overhead is 3300 μm ²; Eight-sided formation A adopts straight flange 3 μm, and the octagon that hypotenuse is 1 μm, its area overhead is 1650 μm ²; Eight-sided formation B adopts straight flange 2 μm, and hypotenuse is the octagon of 0.5 μm, and its area overhead is 1250 μm ².Visible, the latticed MOSFET domain structure of octagon significantly improves the area efficiency of domain.

In sum, in view of the problem that conventional MOSFET power tube domain structure area utilization is low, the invention discloses a kind of octagon latticed MOSFET power tube domain structure, by using the grid of octagon polysilicon strip composition, active area is divided into grid array, the source/drain achieving adjacent mos FET shares, also solve the problem of backgate contact in large scale MOSFET cleverly simultaneously, thus reduce chip area greatly, improve the performance of MOSFET power tube, reduce the cost of chip.

Claims

1. a structure for power MOSFET domain, comprising:

The domain structure of the latticed MOSFET power tube of octagon is repeated to splice realized by elementary cell, and elementary cell is made up of active area, polysilicon strip, source contact hole, drain contact hole, backgate contact hole and metal wound wire.

2. elementary cell composition according to claim 1, the feature of polysilicon strip is:

Polysilicon strip is that a straight flange is longer, the eight-sided formation that hypotenuse is shorter, by the splicing of four such octagon polysilicon strip symmetries and adjacent straight flange overlap, be wherein formed centrally the square area that an area is less.

3. elementary cell composition according to claim 1, polysilicon strip structure according to claim 2, the feature of active area is:

Active area covers the region in each octagon, the region in little square according to claim 2, and the straight flange of octagon polysilicon strip, but does not cover the hypotenuse of octagon polysilicon strip.

4. elementary cell composition according to claim 1, polysilicon strip structure according to claim 2, active area according to claim 3 constituted mode, the feature in source contact hole, drain contact hole is:

Source contact hole is placed in the octagon region, two diagonal angles in four octagon active areas, and drain contact hole is placed in two other diagonal zones.

5. the domain structure of elementary cell composition according to claim 1 and MOSFET, polysilicon strip structure according to claim 2, active area according to claim 3 constituted mode, the arrangement mode in source contact hole according to claim 4, drain contact hole, the feature of metal wound wire is:

Metal wound wire is made up of the shape of metal wire as " W ", and metal wound wire connects the source electrode of all source contact holes as MOSFET, and metal wound wire connects the drain electrode of all drain contact holes as MOSFET.

6. the domain structure of elementary cell composition according to claim 1 and MOSFET, polysilicon strip structure according to claim 2, active area according to claim 3 constituted mode, the arrangement mode in source contact hole according to claim 4, drain contact hole, according to the connected mode of claim 5 metal wound wire, the feature of backgate contact hole is:

In the little square area that the metal wound wire connecting source contact hole covers, place backgate contact hole.

7. the domain structure of elementary cell composition according to claim 1 and MOSFET, polysilicon strip structure according to claim 2, active area according to claim 3 constituted mode, the arrangement mode in source contact hole according to claim 4, drain contact hole, according to the connected mode of claim 5 metal wound wire, according to the arrangement mode of claim 6 backgate contact hole, the feature that N+ injects and P+ injects is:

In typical CMOS technology, if for N+ injects in backgate contact area, so the trap as PMOS contacts by backgate contact, and P+ injection need be carried out in other region except backgate contact area; On the contrary, if for P+ injects in backgate contact area, so backgate contact is using the substrate contact as NMOS tube, and N+ injection is carried out in other region except backgate contact area.