CN101911201B - 存储器单元、存储器单元编程方法、存储器单元读取方法、存储器单元操作方法及存储器装置 - Google Patents
存储器单元、存储器单元编程方法、存储器单元读取方法、存储器单元操作方法及存储器装置 Download PDFInfo
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Abstract
所揭示实施例包含存储器单元操作方法、存储器单元编程方法、存储器单元读取方法、存储器单元及存储器装置。在一个实施例中,存储器单元包含字线、第一位线、第二位线及存储器元件。所述存储器元件电连接到所述字线且选择性地电连接到所述第一位线及所述第二位线。所述存储器元件经由所述存储器元件的电阻状态存储信息。所述存储器单元经配置以经由从所述第一位线穿过所述存储器元件流到所述字线的第一电流或从所述字线穿过所述存储器元件流到所述第二位线的第二电流传达所述存储器元件的所述电阻状态。
Description
技术领域
本文所揭示实施例涉及存储器单元、存储器单元编程方法、存储器单元读取方法、存储器单元操作方法及存储器装置。
背景技术
电阻式随机存取存储器可使用能够配置于两种不同电阻状态中的一者中的材料来存储信息。当配置于所述电阻状态中的一者中时,所述材料可对电流具有高电阻。相反,当配置于另一电阻状态中时,所述材料可对电流具有低电阻。可使用电信号来改变所述材料被配置于其中的电阻状态。举例来说,如果所述材料处于高电阻状态中,那么可通过跨越所述材料施加电压将所述材料配置于低电阻状态中。
所述电阻状态可以是持久的。举例来说,一旦配置于电阻状态中,所述材料则可保持所述电阻状态,即使无电流或电压施加到所述材料。此外,对所述材料的配置可重复地从高电阻状态改变为低电阻状态或从低电阻状态改变为高电阻状态。
附图说明
图1是图解说明电压/电流关系的曲线图。
图2是图解说明其它电压/电流关系的曲线图。
图3是存储器单元的示意图。
图4是存储器装置的示意图。
图5是存储器装置的示意图,其图解说明电流。
图6是存储器装置的示意图,其图解说明另一电流。
具体实施方式
本发明的实施例涵盖存储器单元操作方法、存储器单元编程方法、存储器单元读取方法、存储器单元及存储器装置。将参照图1到6描述此类方法、存储器单元及存储器装置的实例性实施例。
随机存取存储器可使用存储器元件的电阻状态来存储一个或一个以上信息位。举例来说,通过使位值“1”与低电阻状态及位值“0”与高电阻状态相关联,能够配置于高电阻状态或低电阻状态中的存储器元件可存储一个信息位。另一选择为,可使位值“1”与高电阻相关联且可使位值“0”与低电阻状态相关联。
所述存储器元件可包含双极存储器材料。跨越所述双极存储器材料施加的正电压可将所述双极存储器材料的配置从高电阻状态改变为低电阻状态。此外,跨越所述双极存储器材料施加的负电压可将所述双极存储器材料的配置从低电阻状态改变为高电阻状态。
另一选择为,跨越所述双极存储器材料施加的负电压可将所述双极存储器材料的配置从高电阻状态改变为低电阻状态且跨越所述双极存储器材料施加的正电压可将所述双极存储器材料的配置从低电阻状态改变为高电阻。因此,可使用具有第一极性的电压将双极存储器材料配置于第一电阻状态中且可使用其极性与所述第一极性相反的电压将其配置于第二电阻状态中。
双极存储器材料的实例包含离子导电型硫族化合物、二元金属氧化物、钙钛矿氧化物、巨磁阻物及聚合物。可用作双极存储器材料的实例性离子导电型硫族化合物包含GeS、GeSe以及经掺杂Ag或Cu的GeS及GeSe。可用作双极存储器材料的实例性二元金属氧化物包含HfOx、Nb2O5、Al2O3、WOx、Ta2O5、TiOx、ZrOx、CuxO及NixO。可用作双极存储器材料的实例性离子型钙钛矿氧化物包含经掺杂或未经掺杂的SrTiO3、SrZrO3、BaTiO3。
可用作双极存储器材料的实例性巨磁阻物包含Pr1-xCaxMnO3(PCMO)、La1-xCaxMnO3(LCMO)及Ba1-xSrxTiO3。可用作双极存储器材料的实例性聚合物包含BengalaRose、AlQ3Ag、Cu-TCNQ、DDQ、TAPA及基于萤光物的聚合物。当然,其它材料也可用作双极存储器材料。上文所列出材料仅以举例方式提供而非作为双极存储器材料的穷尽列表。
参照图1,曲线图100描绘施加到最初呈高电阻状态的存储器元件的电压与由所述电压产生穿过所述存储器元件的电流之间的关系102的一个实例。所述存储器元件可包括上述双极存储器材料中的一者或一者以上。曲线图100图解说明,当施加到所述存储器元件的电压从-0.6V增加到0.2V时,无电流或可忽略不计的电流量(举例来说,小于1微安)流过所述存储器元件。然而,在大致等于接通电压104的电压下,所述存储器元件开始传导电流。当跨越所述存储器元件的电压增加到超过接通电压104时,由所述存储器元件传导的电流量在无电流箝位情况下随所述电压增加。图1中所描绘的电流与电压的整平由测量电路的电流箝位产生。
因此,曲线图100图解说明所述存储器元件的电阻状态的改变。最初,所述存储器元件处于高电阻状态中,此可由以下事实证明:当将小于接通电压的电压施加到所述存储器元件时,所述存储器元件不传导电流或传导可忽略不计的电流量。在此高电阻状态下,所述存储器元件可具有约为或高于109欧姆的电阻。然而,一旦将大于或等于接通电压104的电压施加到所述存储器元件,所述存储器元件本身则配置于低电阻状态中,此可由以下事实证明:所述存储器元件开始传导电流。在此低电阻状态下,所述存储器元件可以是高导电性且具有约为几千欧姆的电阻。
参照图2,曲线图200描绘施加到最初呈上述低电阻状态的存储器元件的电压与由所述电压产生流过所述存储器元件的电流之间的关系202的一个实例。曲线图200图解说明,由大于约0.25V的电压产生的电流大致相同,此由测量电路的电流箝位产生。在无电流箝位的情况下,所述电流随电压增加。当所述电压减小到低于约0.25V时,穿过所述存储器元件的电流相应地减小。当跨越所述存储器元件施加的电压变为负时,穿过所述存储器元件的电流也是负的。然而,当跨越所述存储器元件施加的电压大致等于接通电压204时,穿过所述存储器元件的电流量大致为零。当所述电压进一步减小到低于所述接通电压时,穿过所述存储器元件的电流大致保持为零。
因此,曲线图200图解说明所述存储器元件的电阻状态的改变。最初,所述存储器元件处于低电阻状态中,此可由以下事实证明:当将大于接通电压204的电压施加到所述存储器元件时,所述存储器元件传导电流。然而,一旦将小于或等于接通电压204的电压施加到所述存储器元件,所述存储器元件本身则配置于上述高电阻状态中,此可由以下事实证明:所述存储器元件停止传导电流或仅传导可忽略不计的电流量。
在一些情况中,一旦配置于高电阻状态中,所述存储器元件则可保持所述高电阻状态,只要不将大于或等于接通电压104的电压施加到所述存储器元件即可。即使无电压施加到所述存储器元件,所述存储器元件也可保持所述高电阻状态。因此,可将所述存储器元件的高电阻状态描述为非易失性,因为只要不将大于或等于接通电压104的电压施加到所述存储器元件,所述高电阻状态则可不随时间改变。
类似地,在一些情况中,一旦配置于低电阻状态中,所述存储器元件则可保持所述低电阻状态,只要不将小于或等于接通电压204的电压施加到所述存储器元件即可。实际上,即使无电压施加到存储器元件,所述存储器元件也可保持所述低电阻状态。因此,也可将所述存储器元件的低电阻状态描述为非易失性,因为只要不将小于或等于接通电压204的电压施加到所述存储器元件,所述低电阻状态则可不随时间改变。
由于所述高电阻状态及所述低电阻状态可以是非易失性,因此可使用所述存储器元件来存储一个位信息。举例来说,存储器元件可在配置于高电阻状态中时表示位值“0”且可在配置于低电阻状态中时表示位值“1”。此外,所述存储器元件的电阻状态可随时间重复改变。因此,所述存储器元件可在一个时刻时处于表示位值“0”的高电阻状态中且所述存储器元件可在另一时刻时处于表示位值“1”的低电阻状态中。类似地,以电阻状态来表示位值可与上述方式相反。
参照图3,图中图解说明存储器单元300。存储器单元300包含具有电极306与304的存储器元件302。存储器元件302可包括双极存储器材料,例如上述双极存储器材料中的一者或一者以上。存储器单元300还包含字线308及两个位线314与316。存储器元件302的电极304连接到字线308。
位线314可选择性地电连接到存储器元件302。举例来说,二极管310可连接到位线314且连接到电极306。当二极管310受到正向偏置时(例如,受到超过二极管310的开启电压的正向偏置),二极管310可从位线314向存储器元件302传导电流,由此将位线314电连接到存储器元件302。相反,当二极管310未受到正向偏置时(例如,当二极管310受到反向偏置时),二极管310可阻止电流从存储器元件302流到位线314或从位线314流到存储器元件302,使得存储器元件302不电连接到位线314。
类似地,位线316可选择性地电连接到存储器元件302。举例来说,二极管312可连接到位线316且连接到电极306。当二极管312受到正向偏置时(例如,受到超过二极管312的开启电压的正向偏置),二极管312可从存储器元件302向位线316传导电流,由此将存储器元件302电连接到位线316。相反,当二极管312未受到正向偏置时(例如,当二极管312受到反向偏置时),二极管312可阻止电流从位线316流到存储器元件302或从存储器元件302流到位线316,使得存储器元件302不电连接到位线316。
在一些配置中,替代二极管,存储器单元可包括选择性地将存储器元件电连接到第一位线及/或第二位线的一个或一个以上装置。举例来说,在一个配置中,存储器元件300可使用第一晶体管来替换二极管310且使用第二晶体管来替换二极管312。当接通时,所述第一晶体管可允许电流在位线314与存储器元件302之间流动以电连接位线314与存储器元件302。当关断时,所述第一晶体管可阻止电流在位线314与存储器元件302之间流动,由此将位线314与存储器元件302切断电连接。
类似地,所述第二晶体管可选择性地将存储器元件302电连接到位线316。可替代地使用除二极管或晶体管以外的装置来选择性地将存储器元件302电连接到位线314与316。
存储器单元300可经由存储器元件302的电阻状态存储信息位。在一个配置中,所述位可具有值“0”或值“1”。举例来说,根据一个惯例,如果存储器元件302处于高电阻状态中,由存储器单元300存储的位的值可为“0”而如果存储器元件302处于低电阻状态中,由存储器单元300存储的位的值可为“1”。当然,可替代地使用高电阻状态表示位值“1”且低电阻状态表示位值“0”的惯例。
可使用读取操作来确定由存储器单元300存储的位的值。根据一个读取操作,可在字线308与位线316之间施加第一正电压以使得字线308较位线316处于较高电位且使得二极管312受到正向偏置。所述第一正电压可大于二极管312的开启电压但小于二极管312的开启电压与存储器元件302的关断电压(上文已结合图2描述所述关断电压)的总和以使得存储器元件302的电阻状态不受改动。可同时在字线308与位线314之间施加第二正电压以使得字线308较位线314处于较高电位且使得二极管310受到反向偏置。所述第二电压可低于二极管310的击穿电压。在一些情况中,所述第一电压与所述第二电压可以是大致相同的电压。
如果存储器元件302配置于低电阻状态中,那么电流可从字线308穿过存储器元件302及受到正向偏置的二极管312流到位线316。基于所述电流,包括存储器单元300的存储器装置可确定存储器元件302处于低电阻状态中且因此由存储器单元300存储的值为“1”。举例来说,所述存储器装置可将位线316上的电流与参考电流相比较或所述存储器装置可使用位线316上的电流来产生电压且随后可将所述电压与参考电压相比较。
相反,如果存储器元件302配置于高电阻状态中,那么存储器元件302可阻止电流从字线308穿过存储器元件302及受到正向偏置的二极管312流到位线316。另一选择为,存储器元件302可将从字线308穿过存储器元件302及受到正向偏置的二极管312流到位线316的电流量限制于可忽略不计的电流量内,其可明显不同于存储器元件302处于低电阻状态中时所允许流动的电流量。基于缺乏电流或非常小的电流量,包括存储器单元300的存储器装置可确定存储器元件302处于高电阻状态中且因此由存储器单元300存储的值为“0”。
可替代地使用另一种读取存储器单元300的方法。根据此方法,可在位线314与字线308之间施加第一正电压以使得位线314较字线308处于较高电位且使得二极管310受到正向偏置。所述第一正电压可大于二极管310的开启电压但小于二极管310的开启电压与存储器元件302的接通电压(上文已结合图1描述所述接通电压)的总和以使得存储器元件302的电阻状态不受改动。可同时在位线316与字线308之间施加第二正电压以使得位线316较字线308处于较高电位且使得二极管312受到反向偏置。所述第二电压可低于二极管312的击穿电压。在一些情况中,所述第一电压与所述第二电压可以是大致相同的电压。
如果存储器元件302配置于低电阻状态中,那么电流可从位线314穿过受到正向偏置的二极管310及存储器元件302流到字线308。基于字线308上的电流,包括存储器单元300的存储器装置可确定存储器元件302处于低电阻状态中且因此由存储器单元300存储的值为“1”。
相反,如果存储器元件302配置于高电阻状态中,那么存储器元件302可阻止电流从位线314穿过受到正向偏置的二极管310及存储器元件302流到字线308。另一选择为,存储器元件302可将从位线314穿过受到正向偏置的二极管310及存储器元件302流到字线308的电流量限制于可忽略不计的量内,其可明显不同于存储器元件302处于低电阻状态中时所允许流动的电流量。基于缺乏电流或非常小的电流量,包括存储器单元300的存储器装置可确定存储器元件302处于高电阻状态中且因此由存储器单元300存储的值为“0”。
除了从存储器单元300读取位值以外,还可将位值写入到存储器单元300。为将位值“1”写入到存储器单元300,可在位线314与字线308之间施加第一正电压以使得位线314较字线308处于较高电位且使得二极管310受到正向偏置。所述第一正电压可大于二极管310的开启电压与存储器元件302的接通电压的总和。如果存储器元件302处于高电阻状态中,那么所述第一电压(或由所述第一电压产生的电流)可将存储器元件302重新配置于低电阻状态中。如果存储器元件302已处于低电阻状态中,那么存储器元件302可保持所述低电阻状态。因此,由于所述第一电压,存储器元件302可配置于与位值“1”对应的低电阻状态中。
第二正电压可与所述第一电压同时施加。可在位线316与字线308之间施加所述第二正电压以使得位线316较字线308处于较高电位且使得二极管312受到反向偏置。所述第二电压可阻止电流从位线314流到位线316。所述第二电压可低于二极管312的击穿电压。
所述第一电压可由第一电压脉冲产生而所述第二电压可由第二电压脉冲产生。在一些情况中,所述第一电压与所述第二电压可以是大致相同的电压。
另一选择为,可将位值“0”写入到存储器单元300。为将位值“0”写入到存储器单元300,可在字线308与位线316之间施加第一正电压以使得字线308较位线316处于较高电位且使得二极管312受到正向偏置。所述第一正电压可大于二极管312的开启电压与存储器元件302的关断电压的总和。如果存储器元件302处于低电阻状态中,那么所述第一电压(或由所述第一电压产生的电流)可将存储器元件302重新配置于高电阻状态中。如果存储器元件302已处于高电阻状态中,那么存储器元件302可保持所述高电阻状态。因此,由于所述第一电压,存储器元件302可配置于与位值“0”对应的高电阻状态中。
第二正电压可与所述第一电压同时施加。可在字线308与位线314之间施加所述第二正电压以使得字线308较位线314处于较高电位且使得二极管310受到反向偏置。所述第二电压可阻止电流从位线314流到位线316。所述第二电压可低于二极管310的击穿电压。
所述第一电压可由第一电压脉冲产生而所述第二电压可由第二电压脉冲产生。在一些情况中,所述第一电压与所述第二电压可以是大致相同的电压。
可重复使用将“0”写入到存储器单元300及将“1”写入到存储器单元300的方法以使得存储器单元300随时间存储不同的位值。在一些情况中,可在不损坏存储器元件302的情况下数百万次地使用这些方法来覆写存储器元件302。由于如上文已结合图1所论述,存储器元件302可在无需将电压或电流施加到存储器元件302的情况下保持电阻状态,因此可称存储器元件302以非易失性方式保存位值。因此,存储器单元300可在无需被频繁刷新的情况下存储信息位或存储器单元300可以低于用来刷新易失性存储器单元的速率的速率被刷新。
参照图4,图中图解说明存储器装置的一部分的示意图400。所述存储器装置包含存储器单元300以及额外存储器单元402、404、406、408、410、412、414及416。所述存储器装置可存储多个位。举例来说,所述存储器装置可在所述存储器装置的每一存储器单元中存储一个位。
所述存储器装置的存储器单元可经布置以共享位线及字线。在图400中,存储器单元402、408及412共享字线418;存储器单元404、300及414共享字线308;且存储器单元406、410及416共享字线420。此外,在图400中,存储器单元402、404及406共享位线424及426;存储器单元408、300及410共享位线314及316;且存储器单元412、414及416共享位线428及430。
参照图5,图中图解说明示意图500,其图解说明图4的存储器装置的配置。可使用所述配置将位值“1”写入到存储器单元300或从存储器单元300读取信息位。根据所述配置,跨越位线314与字线308施加第一正电压。跨越位线316与字线308施加第二正电压。因此,如箭头502所图解说明且如上文已结合图3所描述,电流可从位线314穿过存储器单元300流到字线308。如果所述第一电压大于二极管310的开启电压与存储器元件302的接通电压的总和,那么如上文已结合图3所描述,可将“1”写入到存储器单元300。
另一选择为,如果所述第一电压大于二极管310的开启电压但小于所述二极管的开启电压与存储器元件302的接通电压的总和,那么如上文已结合图3所描述,所述存储器装置可基于从位线314流到字线308的电流确定由存储器单元300存储的位的值。
可能期望确保由存储器单元402、404、406、408、410、412、414及416存储的值在写入或读取存储器单元300时不受干扰。为避免干扰,可以特定电压来配置所述存储器装置的位线及字线。
举例来说,当将“1”写入到存储器单元300中时,位线314及316可较字线308处于较高电位。由于存储器单元408与410也连接到位线314与316,因此字线418与420可经配置以与位线314及316处于大致相同的电位来阻止电流从位线314及/或位线316流到字线418及/或字线420。
此外,可能期望阻止电流从存储器单元404及414流到字线308上以使得字线308上电流可正确地被认为是由存储器单元300造成的。为此,位线424及428可经配置以与字线308处于大致相同的电位来阻止电流从位线424经由存储器单元404流到字线308且阻止电流从位线428经由存储器单元414流到字线308。另外,位线426及430可经配置以较字线308处于较高电位以便阻止电流从位线426穿过存储器单元404流到字线308及从位线430穿过存储器单元414流到字线308。
未连接到字线308或位线314及316的其它存储器单元(即,存储器单元402、406、412及416)可经配置以阻止电流消耗。举例来说,可以致使存储器单元402及406的二极管受到反向偏置的电压来配置位线424及426与字线418及420。类似地,可以致使存储器单元412及416的二极管受到反向偏置的电压来配置位线428及430与字线418及420。
参照图6,图中图解说明示意图600,其图解说明图4的存储器装置的配置。可使用所述配置将位值“0”写入到存储器单元300或从存储器单元300读取信息位。根据所述配置,跨越字线308与位线316施加第一正电压。跨越字线308与位线314施加第二正电压。因此,如箭头602所指示且如上文已结合图3所描述,电流可从字线308穿过存储器单元300流到位线316。如果所述第一电压大于二极管312的开启电压与存储器元件302的关断电压的总和,那么如上文已结合图3所描述,可将“0”写入到存储器单元300。
另一选择为,如果所述第一电压大于二极管312的开启电压但小于二极管的开启电压与存储器元件302的关断电压的总和,那么如上文已结合图3所描述,所述存储器装置可基于从字线308流到位线316的电流确定由存储器单元300存储的位的值。
可能期望确保由存储器单元402、404、406、408、410、412、414及416存储的值在写入或读取存储器单元300时不受干扰。为避免干扰,可以特定电压来配置所述存储器装置的位线及字线。
举例来说,当将“0”写入到存储器单元300中时,位线314及316可较字线308处于较低电位。由于存储器单元408及410也连接到位线314及316,因此字线418与420可经配置以与位线314及316处于大致相同的电位来阻止电流从字线418及/或字线420流到位线314及/或位线316。
此外,可能期望阻止电流从字线308流到存储器单元404及414中。为此,位线426及430可经配置以与字线308处于大致相同的电位来阻止电流从字线308经由存储器单元404流到位线426且阻止电流从字线308经由存储器单元414流到位线430。另外,位线424及428可经配置以较字线308处于较低电位以便阻止电流从位线424穿过存储器单元404流到字线308及从位线428穿过存储器单元414流到字线308。
如图6中所图解说明,未连接到字线308或位线314及316的其它存储器单元(即,存储器单元402、406、412及416)可经配置以阻止电流消耗。举例来说,位线424及428可经配置以与字线418及420处于相同电位来阻止电流流过存储器单元402、406、412及416的左手侧二极管。此外,位线426及430与字线418及420可经配置以反向偏置存储器单元402、406、412及416的右手侧二极管。
上文论述已假设:当在电极306与304之间施加大于存储器元件302的接通电压的电压以使得电极306较电极304处于较高电位时,存储器元件302经配置以使得存储器元件302改变为低电阻状态。类似地,上文论述已假设:当跨越电极304与306施加大于存储器元件302的关断电压的电压以使得电极304较电极306处于较高电位时,存储器元件302改变为高电阻状态。
然而,可反置存储器元件302以便当在电极306与304之间施加大于存储器元件302的关断电压的电压以使得电极306较电极304处于较高电位时,存储器元件302改变为高电阻状态。在此配置中,当跨越电极304与306施加大于存储器元件302的接通电压的电压以使得电极304较电极306处于较高电位时,存储器元件302可改变为低电阻状态。
此外,上文论述已假设:存储器元件302的高电阻状态对应于位值“0”且存储器元件302的低电阻状态对应于位值“1”。然而,如上文所提及,可基于以下理解来构造存储器装置:存储器元件302的高电阻状态对应于位值“1”且存储器元件302的低电阻状态对应于位值“0”,此无需改变写入及读取存储器单元300的原理。
上文论述已论及一种具有高电阻状态及低电阻状态的存储器元件。然而,在本发明的一些实施例中,存储器元件可以是可配置于两个以上的不同电阻状态中。此存储器元件可存储一个以上的信息位且可用于例如存储器单元300等存储器单元中。多个不同编程电压中的每一者可对应于所述存储器元件的多个不同电阻状态中的不同状态。
上述编程存储器单元300的方法可通过将所述多个编程电压中的一者施加到所述存储器元件以将所述存储器元件配置于对应于所述所施加编程电压的电阻状态中而适于编程具有一个以上电阻状态的存储器元件。此外,上述读取存储器单元300的方法可通过将由施加到存储器元件的电压产生的电流与多个不同参考电流相比较以确定所述存储器单元配置于所述多个不同电阻状态中的哪一者中而适于读取所述存储器元件。
Claims (25)
1.一种存储器单元,其包括:
字线;
第一位线;
第二位线;及
存储器元件,其直接电连接到所述字线且选择性地电连接到所述第一位线且选择性地电连接到所述第二位线,所述存储器元件经由所述存储器元件的电阻状态来存储一个位信息;
其中所述存储器单元经配置以经由从所述第一位线穿过所述存储器元件流到所述字线的第一电流传达所述存储器元件的所述电阻状态,且经配置以经由从所述字线穿过所述存储器元件流到所述第二位线的第二电流传达所述存储器元件的所述电阻状态。
2.如权利要求1所述的存储器单元,其中:
所述存储器单元进一步包括第一二极管及第二二极管;
所述存储器元件包括:第一电极,其经由所述第一二极管连接到所述第一位线且经由所述第二二极管连接到所述第二位线;及第二电极,其连接到所述字线;且
所述存储器元件在所述第一二极管受到正向偏置时经由所述第一二极管电连接到所述第一位线且在所述第一二极管未受到正向偏置时与所述第一位线电断开;且
所述存储器元件在所述第二二极管受到正向偏置时经由所述第二二极管电连接到所述第二位线且在所述第二二极管未受到正向偏置时与所述第二位线电断开。
3.如权利要求1所述的存储器单元,其中所述存储器元件包括离子导电型硫族化合物、二元金属氧化物、钙钛矿氧化物、巨磁阻物或聚合物中的至少一者。
4.如权利要求1所述的存储器单元,其中所述存储器元件经配置以在不存在电压或电流的情况下以非易失性方式存储所述信息。
5.一种存储器单元编程方法,其包括:
提供包括字线、第一与第二位线及存储器元件的存储器单元,所述存储器元件直接电连接到所述字线且选择性地电连接到所述第一位线且选择性地电连接到所述第二位线;
使用所述存储器元件,经由所述存储器元件的第一电阻状态来存储一个位信息;
跨越所述第二位线与所述字线施加第一电压以有效地将所述第二位线与所述存储器元件电断开;及
跨越所述第一位线及所述字线施加第二电压以有效地将所述第一位线电连接到所述存储器元件且将所述存储器元件配置于不同的第二电阻状态中,在施加所述第二电压期间所述第一位线处于比所述字线高的电位。
6.如权利要求5所述的方法,其进一步包括:
提供连接到所述存储器元件的第一电极且连接到所述第一位线的第一二极管,
提供连接到所述存储器元件的第二电极且连接到所述第二位线的第二二极管,所述第二二极管由于所述第一电压而受到反向偏置且所述第一电压小于所述第二二极管的击穿电压;及
其中;
将所述存储器元件的第二电极连接到所述字线;
当所述存储器元件处于所述第一电阻状态中时,所述存储器元件对所述第二电极与所述第一电极之间的电流具有高传导性;且
当所述存储器元件处于所述第二电阻状态中时,所述存储器元件对所述第二电极与所述第一电极之间的电流具有高电阻性。
7.如权利要求6所述的方法,其中所述所施加第二电压大于所述存储器元件的关断电压与所述第一二极管的开启电压的总和。
8.如权利要求5所述的方法,其中所述所施加第一电压与所述所施加第二电压大致相同。
9.如权利要求5所述的方法,其进一步包括在所述第一电压的所述施加及所述第二电压的所述施加之后:
跨越所述第一位线与所述字线施加第三电压以有效地将所述第一位线与所述存储器元件电断开;及
跨越所述字线与所述第二位线施加第四电压以有效地将所述第二位线电连接到所述存储器元件且将所述存储器元件配置于所述第一电阻状态中。
10.如权利要求9所述的方法,其中所述所施加第三电压与所述所施加第四电压大致相同。
11.一种存储器单元读取方法,其包括:
提供包括字线、第一与第二位线及存储器元件的存储器单元,且所述存储器元件直接电连接到所述字线且选择性地电连接到所述第一位线且选择性地电连接到所述第二位线,所述存储器元件被安置成选择性地配置于多个不同电阻状态中的任一者中,所述存储器元件经由所述存储器元件的电阻状态来存储一个位信息;
跨越所述字线与所述第一位线施加第一电压以有效地将所述第一位线与所述存储器元件电断开,在施加所述第一电压期间所述字线处于比所述第一位线高的电位;
跨越所述字线与所述第二位线施加第二电压以有效地致使电流从所述字线穿过所述存储器元件流到所述第二位线;及
基于所述电流,确定所述存储器元件配置于所述多个不同电阻状态中的特定一者中。
12.如权利要求11所述的方法,其中使所述多个不同电阻状态中的所述特定一者与信息位的值相关联。
13.如权利要求11所述的方法,其中将所述存储器元件安置成选择性地配置于高电阻状态或低电阻状态中。
14.如权利要求11所述的方法,其进一步包括:
提供连接到所述存储器元件的第一电极且连接到所述第一位线的第一二极管;及
提供连接到所述存储器元件的所述第一电极且连接到所述第二位线的第二二极管;
其中所述所施加第二电压大于所述第二二极管的开启电压但小于所述第二二极管的所述开启电压与所述存储器元件的关断电压的总和且所述存储器元件包括连接到所述字线的第二电极。
15.如权利要求11所述的方法,其中所述确定包括将所述电流与参考电流相比较。
16.如权利要求11所述的方法,其中所述确定包括确定所述电流为不可测量且所述存储器元件处于高电阻状态中。
17.一种存储器装置,其包括:
第一位线;
第二位线;
存储器元件,其经安置以选择性地且可逆地配置于两个不同电阻状态中的一者中,所述存储器元件经由所述存储器元件的所述电阻状态来存储一个位信息;
第一二极管,其使所述第一位线连接到所述存储器元件的第一电极;
第二二极管,其使所述第二位线连接到所述存储器元件的所述第一电极;及
字线,其直接连接到所述存储器元件的第二电极。
18.如权利要求17所述的装置,其中所述第一二极管经配置以在所述第一二极管受到正向偏置时从所述第一位线向所述第一电极传导电流且所述第二二极管经配置以在所述第二二极管受到正向偏置时从所述第一电极向所述第二位线传导电流。
19.如权利要求17所述的装置,其中所述存储器元件包括第一存储器元件,所述字线包括第一字线,且所述存储器装置进一步包括:
第二存储器元件,其经安置以选择性地且可逆地配置于两个不同电阻状态中的一者中;
第二字线,其连接到所述第二存储器元件的第二电极;
第三二极管,其连接于所述第一位线与所述第二存储器元件的第一电极之间;及
第四二极管,其连接于所述第二位线与所述第二存储器元件的所述第一电极之间。
20.如权利要求19所述的装置,其中所述存储器装置经配置以:
经由从所述第一字线穿过所述第一存储器元件流到所述第二位线的第一电流传达所述第一存储器元件的所述电阻状态;及
当正通过所述第一电流传达所述第一存储器元件的所述电阻状态时,阻止第二电流从所述第二字线穿过所述第二存储器元件流到所述第二位线。
21.如权利要求19所述的装置,其中所述存储器装置经配置以:
经由所述第一位线与所述第一字线之间的第一电压改变所述第一存储器元件的所述电阻状态;及
当在所述第一位线与所述第一字线之间正施加所述第一电压时,阻止所述第一位线与所述第二字线之间的第二电压改变所述第二存储器元件的所述电阻状态。
22.一种存储器单元操作方法,其包括:
提供包括字线、第一与第二位线、存储器元件及第一与第二二极管的存储器单元,所述存储器元件直接电连接到所述字线且在所述第一二极管受到正向偏置时经由所述第一二极管选择性地电连接到所述第一位线且在所述第二二极管受到正向偏置时经由所述第二二极管选择性地电连接到所述第二位线;
跨越所述字线与所述第一位线施加第一电压以有效地将所述第一位线与所述存储器元件电断开;
当施加所述第一电压时,跨越所述字线与所述第二位线施加第二电压以有效地将所述第二位线电连接到所述存储器元件且将所述存储器元件配置于高电阻状态中;
当施加所述第一电压但不施加所述第二电压时,跨越所述字线与所述第二位线施加第三电压;
基于缺乏从所述字线穿过所述存储器元件及所述第二二极管流到所述第二位线的电流,确定所述存储器元件配置于所述高电阻状态中;
跨越所述第二位线与所述字线施加第四电压以有效地将所述第二位线与所述存储器元件电断开;
当施加所述第四电压时,跨越所述第一位线与所述字线施加第五电压以有效地将所述第一位线电连接到所述存储器元件且将所述存储器元件配置于低电阻状态中;
当施加所述第一电压但不施加所述第二电压时且在所述存储器元件配置于所述低电阻状态中之后,跨越所述字线与所述第二位线施加所述第三电压以有效地致使电流从所述字线穿过所述存储器元件及所述第二二极管流到所述第二位线;及
基于所述电流,确定所述存储器元件配置于所述低电阻状态中;
其中所述存储器元件经由所述存储器元件的电阻状态来存储一个位信息。
23.如权利要求22所述的方法,其中所述所施加第二电压大于所述第三电压。
24.如权利要求22所述的方法,其中所述存储器元件包括离子导电型硫族化合物、二元金属氧化物、钙钛矿氧化物、巨磁阻物或聚合物中的至少一者。
25.如权利要求22所述的方法,其中所述所施加第三电压大于所述第二二极管的开启电压但小于所述第二二极管的所述开启电压与所述存储器元件的关断电压的总和。
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Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7768812B2 (en) | 2008-01-15 | 2010-08-03 | Micron Technology, Inc. | Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices |
US8034655B2 (en) | 2008-04-08 | 2011-10-11 | Micron Technology, Inc. | Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays |
US8211743B2 (en) | 2008-05-02 | 2012-07-03 | Micron Technology, Inc. | Methods of forming non-volatile memory cells having multi-resistive state material between conductive electrodes |
US8134137B2 (en) | 2008-06-18 | 2012-03-13 | Micron Technology, Inc. | Memory device constructions, memory cell forming methods, and semiconductor construction forming methods |
US9343665B2 (en) | 2008-07-02 | 2016-05-17 | Micron Technology, Inc. | Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array |
US8014185B2 (en) * | 2008-07-09 | 2011-09-06 | Sandisk 3D Llc | Multiple series passive element matrix cell for three-dimensional arrays |
US7733685B2 (en) * | 2008-07-09 | 2010-06-08 | Sandisk 3D Llc | Cross point memory cell with distributed diodes and method of making same |
US7923812B2 (en) * | 2008-12-19 | 2011-04-12 | Sandisk 3D Llc | Quad memory cell and method of making same |
US7910407B2 (en) | 2008-12-19 | 2011-03-22 | Sandisk 3D Llc | Quad memory cell and method of making same |
US8461566B2 (en) | 2009-11-02 | 2013-06-11 | Micron Technology, Inc. | Methods, structures and devices for increasing memory density |
US8427859B2 (en) | 2010-04-22 | 2013-04-23 | Micron Technology, Inc. | Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells |
US8411477B2 (en) | 2010-04-22 | 2013-04-02 | Micron Technology, Inc. | Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells |
US8289763B2 (en) | 2010-06-07 | 2012-10-16 | Micron Technology, Inc. | Memory arrays |
US8351242B2 (en) | 2010-09-29 | 2013-01-08 | Micron Technology, Inc. | Electronic devices, memory devices and memory arrays |
US8759809B2 (en) | 2010-10-21 | 2014-06-24 | Micron Technology, Inc. | Integrated circuitry comprising nonvolatile memory cells having platelike electrode and ion conductive material layer |
US8796661B2 (en) | 2010-11-01 | 2014-08-05 | Micron Technology, Inc. | Nonvolatile memory cells and methods of forming nonvolatile memory cell |
US8526213B2 (en) | 2010-11-01 | 2013-09-03 | Micron Technology, Inc. | Memory cells, methods of programming memory cells, and methods of forming memory cells |
US8502185B2 (en) * | 2011-05-31 | 2013-08-06 | Crossbar, Inc. | Switching device having a non-linear element |
US9454997B2 (en) | 2010-12-02 | 2016-09-27 | Micron Technology, Inc. | Array of nonvolatile memory cells having at least five memory cells per unit cell, having a plurality of the unit cells which individually comprise three elevational regions of programmable material, and/or having a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells; array of vertically stacked tiers of nonvolatile memory cells |
US8431458B2 (en) | 2010-12-27 | 2013-04-30 | Micron Technology, Inc. | Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells |
US8791447B2 (en) | 2011-01-20 | 2014-07-29 | Micron Technology, Inc. | Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells |
US8488365B2 (en) | 2011-02-24 | 2013-07-16 | Micron Technology, Inc. | Memory cells |
US8537592B2 (en) | 2011-04-15 | 2013-09-17 | Micron Technology, Inc. | Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells |
JP2013069928A (ja) * | 2011-09-22 | 2013-04-18 | Toshiba Corp | 不揮発性半導体記憶装置 |
US9514814B1 (en) * | 2015-08-13 | 2016-12-06 | Arm Ltd. | Memory write driver, method and system |
US10739186B2 (en) * | 2017-11-20 | 2020-08-11 | Samsung Electronics Co., Ltd. | Bi-directional weight cell |
CN110619907B (zh) * | 2019-08-28 | 2021-06-04 | 中国科学院上海微***与信息技术研究所 | 一种突触电路、突触阵列及基于突触电路的数据处理方法 |
JP2021047937A (ja) * | 2019-09-17 | 2021-03-25 | キオクシア株式会社 | 半導体記憶装置 |
RU2737794C1 (ru) * | 2019-12-10 | 2020-12-03 | Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский Нижегородский государственный университет им. Н.И. Лобачевского" | Способ управления работой мемристора и устройство для его осуществления |
RU2744246C1 (ru) * | 2019-12-10 | 2021-03-04 | Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский Нижегородский государственный университет им. Н.И. Лобачевского" | Устройство для переключения мемристора |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1444284A (zh) * | 2002-03-12 | 2003-09-24 | 三菱电机株式会社 | 具有电位控制电路的半导体存储器 |
CN1459792A (zh) * | 2002-05-22 | 2003-12-03 | 惠普公司 | 具有串联二极管的磁随机存取存储器的三次取样读出 |
US6693846B2 (en) * | 2002-05-24 | 2004-02-17 | Infineon Technologies Ag | Command controller for an integrated circuit memory device and test circuitry thereof |
CN1624803A (zh) * | 2003-12-05 | 2005-06-08 | 株式会社瑞萨科技 | 半导体集成电路装置 |
Family Cites Families (294)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1266513A (zh) * | 1969-05-19 | 1972-03-08 | ||
AU562641B2 (en) * | 1983-01-18 | 1987-06-18 | Energy Conversion Devices Inc. | Electronic matrix array |
US4715685A (en) * | 1985-03-04 | 1987-12-29 | Energy Conversion Devices, Inc. | Liquid crystal display having potential source in a diode ring |
JPH01130552A (ja) | 1987-11-17 | 1989-05-23 | Sharp Corp | 高抵抗素子 |
US4964080A (en) | 1990-03-09 | 1990-10-16 | Intel Corporation | Three-dimensional memory cell with integral select transistor |
US5057888A (en) | 1991-01-28 | 1991-10-15 | Micron Technology, Inc. | Double DRAM cell |
US6432767B2 (en) | 1995-12-05 | 2002-08-13 | Hitachi, Ltd. | Method of fabricating semiconductor device |
US6271131B1 (en) | 1998-08-26 | 2001-08-07 | Micron Technology, Inc. | Methods for forming rhodium-containing layers such as platinum-rhodium barrier layers |
US6197628B1 (en) | 1998-08-27 | 2001-03-06 | Micron Technology, Inc. | Ruthenium silicide diffusion barrier layers and methods of forming same |
US6483736B2 (en) | 1998-11-16 | 2002-11-19 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US6034882A (en) | 1998-11-16 | 2000-03-07 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US6635914B2 (en) | 2000-09-08 | 2003-10-21 | Axon Technologies Corp. | Microelectronic programmable device and methods of forming and programming the same |
US6218696B1 (en) | 1999-06-07 | 2001-04-17 | Infineon Technologies North America Corp. | Layout and wiring scheme for memory cells with vertical transistors |
US20040124407A1 (en) | 2000-02-11 | 2004-07-01 | Kozicki Michael N. | Scalable programmable structure, an array including the structure, and methods of forming the same |
US7247876B2 (en) | 2000-06-30 | 2007-07-24 | Intel Corporation | Three dimensional programmable device and method for fabricating the same |
US6451646B1 (en) | 2000-08-30 | 2002-09-17 | Micron Technology, Inc. | High-k dielectric materials and processes for manufacturing them |
KR100451096B1 (ko) | 2000-09-19 | 2004-10-02 | 엔이씨 일렉트로닉스 가부시키가이샤 | 자기메모리셀어레이를 갖는 비휘발성 반도체메모리장치 |
DE60126310T2 (de) | 2000-11-01 | 2007-06-06 | Japan Science And Technology Agency, Kawaguchi | Punktkontaktarray, Not-Schaltung und elektronische Schaltung damit |
US6534357B1 (en) | 2000-11-09 | 2003-03-18 | Micron Technology, Inc. | Methods for forming conductive structures and structures regarding same |
US6646297B2 (en) | 2000-12-26 | 2003-11-11 | Ovonyx, Inc. | Lower electrode isolation in a double-wide trench |
US6524867B2 (en) | 2000-12-28 | 2003-02-25 | Micron Technology, Inc. | Method for forming platinum-rhodium stack as an oxygen barrier |
US6440753B1 (en) | 2001-01-24 | 2002-08-27 | Infineon Technologies North America Corp. | Metal hard mask for ILD RIE processing of semiconductor memory devices to prevent oxidation of conductive lines |
JP4818519B2 (ja) | 2001-02-06 | 2011-11-16 | ルネサスエレクトロニクス株式会社 | 磁気記憶装置 |
US7102150B2 (en) | 2001-05-11 | 2006-09-05 | Harshfield Steven T | PCRAM memory cell and method of making same |
ITMI20011150A1 (it) | 2001-05-30 | 2002-11-30 | St Microelectronics Srl | Multiplatore di colonna per memorie a semiconduttore |
US6693821B2 (en) | 2001-06-28 | 2004-02-17 | Sharp Laboratories Of America, Inc. | Low cross-talk electrically programmable resistance cross point memory |
US7193267B2 (en) | 2001-06-28 | 2007-03-20 | Sharp Laboratories Of America, Inc. | Cross-point resistor memory array |
US6905937B2 (en) | 2001-06-28 | 2005-06-14 | Sharp Laboratories Of America, Inc. | Methods of fabricating a cross-point resistor memory array |
US6825058B2 (en) | 2001-06-28 | 2004-11-30 | Sharp Laboratories Of America, Inc. | Methods of fabricating trench isolated cross-point memory array |
US6747286B2 (en) | 2001-06-30 | 2004-06-08 | Ovonyx, Inc. | Pore structure for programmable device |
US6567301B2 (en) | 2001-08-09 | 2003-05-20 | Hewlett-Packard Development Company, L.P. | One-time programmable unit memory cell based on vertically oriented fuse and diode and one-time programmable memory using the same |
US6946712B2 (en) * | 2001-11-07 | 2005-09-20 | Kabushiki Kaisha Toshiba | Magnetic memory device using SOI substrate |
US20030143853A1 (en) | 2002-01-31 | 2003-07-31 | Celii Francis G. | FeRAM capacitor stack etch |
US6778421B2 (en) * | 2002-03-14 | 2004-08-17 | Hewlett-Packard Development Company, Lp. | Memory device array having a pair of magnetic bits sharing a common conductor line |
US6687147B2 (en) | 2002-04-02 | 2004-02-03 | Hewlett-Packard Development Company, L.P. | Cubic memory array with diagonal select lines |
JP4047615B2 (ja) * | 2002-04-03 | 2008-02-13 | 株式会社ルネサステクノロジ | 磁気記憶装置 |
CN1459398A (zh) | 2002-05-21 | 2003-12-03 | 日本精工股份有限公司 | 方向盘柱装置 |
US6952043B2 (en) | 2002-06-27 | 2005-10-04 | Matrix Semiconductor, Inc. | Electrically isolated pillars in active devices |
TWI233204B (en) | 2002-07-26 | 2005-05-21 | Infineon Technologies Ag | Nonvolatile memory element and associated production methods and memory element arrangements |
US6859382B2 (en) | 2002-08-02 | 2005-02-22 | Unity Semiconductor Corporation | Memory array of a non-volatile ram |
US6753561B1 (en) | 2002-08-02 | 2004-06-22 | Unity Semiconductor Corporation | Cross point memory array using multiple thin films |
US6917539B2 (en) * | 2002-08-02 | 2005-07-12 | Unity Semiconductor Corporation | High-density NVRAM |
US7067862B2 (en) | 2002-08-02 | 2006-06-27 | Unity Semiconductor Corporation | Conductive memory device with conductive oxide electrodes |
US6834008B2 (en) | 2002-08-02 | 2004-12-21 | Unity Semiconductor Corporation | Cross point memory array using multiple modes of operation |
US6970375B2 (en) | 2002-08-02 | 2005-11-29 | Unity Semiconductor Corporation | Providing a reference voltage to a cross point memory array |
US6785159B2 (en) | 2002-08-29 | 2004-08-31 | Micron Technology, Inc. | Combination etch stop and in situ resistor in a magnetoresistive memory and methods for fabricating same |
US7184301B2 (en) * | 2002-11-27 | 2007-02-27 | Nec Corporation | Magnetic memory cell and magnetic random access memory using the same |
WO2004061851A2 (en) | 2002-12-19 | 2004-07-22 | Matrix Semiconductor, Inc | An improved method for making high-density nonvolatile memory |
US7005350B2 (en) | 2002-12-31 | 2006-02-28 | Matrix Semiconductor, Inc. | Method for fabricating programmable memory array structures incorporating series-connected transistor strings |
DE10261457B3 (de) | 2002-12-31 | 2004-03-25 | Infineon Technologies Ag | Integrierte Schaltungsanordnung mit einem Transistorarray aus vertikalen FET-Auswahltransistoren |
JP2004220740A (ja) | 2003-01-17 | 2004-08-05 | Seiko Epson Corp | 強誘電体記憶装置 |
DE10306281B4 (de) | 2003-02-14 | 2007-02-15 | Infineon Technologies Ag | Anordnung und Verfahren zur Herstellung von vertikalen Transistorzellen und transistorgesteuerten Speicherzellen |
US6958273B2 (en) | 2003-03-21 | 2005-10-25 | Silicon Storage Technology, Inc. | Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region, and a memory array made thereby |
US6753562B1 (en) | 2003-03-27 | 2004-06-22 | Sharp Laboratories Of America, Inc. | Spin transistor magnetic random access memory device |
US6879505B2 (en) | 2003-03-31 | 2005-04-12 | Matrix Semiconductor, Inc. | Word line arrangement having multi-layer word line segments for three-dimensional memory array |
US7233024B2 (en) | 2003-03-31 | 2007-06-19 | Sandisk 3D Llc | Three-dimensional memory device incorporating segmented bit line memory array |
US7459715B2 (en) | 2003-04-03 | 2008-12-02 | Kabushiki Kaisha Toshiba | Resistance change memory device |
US7335906B2 (en) | 2003-04-03 | 2008-02-26 | Kabushiki Kaisha Toshiba | Phase change memory device |
US6806531B1 (en) | 2003-04-07 | 2004-10-19 | Silicon Storage Technology, Inc. | Non-volatile floating gate memory cell with floating gates formed in cavities, and array thereof, and method of formation |
US7001846B2 (en) | 2003-05-20 | 2006-02-21 | Sharp Laboratories Of America, Inc. | High-density SOI cross-point memory array and method for fabricating same |
TW589753B (en) | 2003-06-03 | 2004-06-01 | Winbond Electronics Corp | Resistance random access memory and method for fabricating the same |
US7291878B2 (en) | 2003-06-03 | 2007-11-06 | Hitachi Global Storage Technologies Netherlands B.V. | Ultra low-cost solid-state memory |
US7416911B2 (en) | 2003-06-24 | 2008-08-26 | California Institute Of Technology | Electrochemical method for attaching molecular and biomolecular structures to semiconductor microstructures and nanostructures |
KR100507205B1 (ko) | 2003-07-15 | 2005-08-10 | 현대자동차주식회사 | 노킹 센서 장착 위치 설정 방법 |
US7050346B2 (en) * | 2003-07-29 | 2006-05-23 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and electric device with the same |
US7029924B2 (en) | 2003-09-05 | 2006-04-18 | Sharp Laboratories Of America, Inc. | Buffered-layer memory cell |
US6955992B2 (en) | 2003-09-30 | 2005-10-18 | Sharp Laboratories Of America, Inc. | One mask PT/PCMO/PT stack etching process for RRAM applications |
WO2005041303A1 (ja) | 2003-10-23 | 2005-05-06 | Matsushita Electric Industrial Co., Ltd. | 抵抗変化素子、その製造方法、その素子を含むメモリ、およびそのメモリの駆動方法 |
US7098438B1 (en) * | 2003-11-19 | 2006-08-29 | Raytheon Company | Method and apparatus for resetting a high speed latch circuit |
US7009278B2 (en) | 2003-11-24 | 2006-03-07 | Sharp Laboratories Of America, Inc. | 3d rram |
US6937507B2 (en) * | 2003-12-05 | 2005-08-30 | Silicon Storage Technology, Inc. | Memory device and method of operating same |
US6849891B1 (en) | 2003-12-08 | 2005-02-01 | Sharp Laboratories Of America, Inc. | RRAM memory cell electrodes |
US7002197B2 (en) | 2004-01-23 | 2006-02-21 | Hewlett-Packard Development Company, L.P. | Cross point resistive memory array |
US7138687B2 (en) | 2004-01-26 | 2006-11-21 | Macronix International Co., Ltd. | Thin film phase-change memory |
US7538338B2 (en) | 2004-09-03 | 2009-05-26 | Unity Semiconductor Corporation | Memory using variable tunnel barrier widths |
US20060171200A1 (en) | 2004-02-06 | 2006-08-03 | Unity Semiconductor Corporation | Memory using mixed valence conductive oxides |
US7082052B2 (en) | 2004-02-06 | 2006-07-25 | Unity Semiconductor Corporation | Multi-resistive state element with reactive metal |
US7050316B1 (en) * | 2004-03-09 | 2006-05-23 | Silicon Storage Technology, Inc. | Differential non-volatile content addressable memory cell and array using phase changing resistor storage elements |
US7476945B2 (en) | 2004-03-17 | 2009-01-13 | Sanyo Electric Co., Ltd. | Memory having reduced memory cell size |
DE102004020297B4 (de) | 2004-04-26 | 2007-06-21 | Infineon Technologies Ag | Verfahren zur Herstellung resistiv schaltender Speicherbauelemente |
DE102004026003B3 (de) | 2004-05-27 | 2006-01-19 | Infineon Technologies Ag | Resistive Speicherzellen-Anordnung |
JP4377751B2 (ja) | 2004-06-10 | 2009-12-02 | シャープ株式会社 | クロスポイント構造の半導体記憶装置及びその製造方法 |
KR100614240B1 (ko) | 2004-06-10 | 2006-08-18 | 삼성전자주식회사 | 전계 효과 트랜지스터를 포함하는 반도체 소자 및 그 형성방법 |
US7187201B1 (en) | 2004-06-24 | 2007-03-06 | Xilinx, Inc. | Programmable logic device suitable for implementation in molecular electronics |
US7091091B2 (en) | 2004-06-28 | 2006-08-15 | Promos Technologies Inc. | Nonvolatile memory fabrication methods in which a dielectric layer underlying a floating gate layer is spaced from an edge of an isolation trench and/or an edge of the floating gate layer |
CN101010793B (zh) | 2004-06-30 | 2011-09-28 | Nxp股份有限公司 | 制造具有通过纳米线接触的导电材料层的电子器件的方法 |
US20060002330A1 (en) | 2004-07-01 | 2006-01-05 | Lila Madour | Method and system for providing network access to protocol for carrying authentication for network access (PANA) mobile terminals and point-to-point protocol (PPP) mobile terminals packet data network |
US7791141B2 (en) | 2004-07-09 | 2010-09-07 | International Business Machines Corporation | Field-enhanced programmable resistance memory cell |
JP2006032729A (ja) | 2004-07-16 | 2006-02-02 | Matsushita Electric Ind Co Ltd | 不揮発性メモリとその製造方法 |
JP4827074B2 (ja) | 2004-07-22 | 2011-11-30 | シャープ株式会社 | 高密度soiクロスポイントメモリアレイおよびそれを製造するための方法 |
US7180160B2 (en) | 2004-07-30 | 2007-02-20 | Infineon Technologies Ag | MRAM storage device |
JPWO2006022302A1 (ja) | 2004-08-24 | 2008-05-08 | 国立大学法人大阪大学 | 窒化アルミニウム結晶の製造方法およびそれにより得られた窒化アルミニウム結晶 |
KR100568543B1 (ko) | 2004-08-31 | 2006-04-07 | 삼성전자주식회사 | 작은 접점을 갖는 상변화 기억 소자의 제조방법 |
KR100645044B1 (ko) | 2004-09-17 | 2006-11-10 | 삼성전자주식회사 | 높은 신뢰도를 갖는 불 휘발성 메모리 장치의 프로그램 방법 |
FR2875995B1 (fr) | 2004-09-24 | 2014-10-24 | Oberthur Card Syst Sa | Procede de montage d'un composant electronique sur un support, de preference mou, et entite electronique ainsi obtenue, telle q'un passeport |
US7205238B2 (en) | 2004-10-21 | 2007-04-17 | Sharp Laboratories Of America, Inc. | Chemical mechanical polish of PCMO thin films for RRAM applications |
US7189626B2 (en) | 2004-11-03 | 2007-03-13 | Micron Technology, Inc. | Electroless plating of metal caps for chalcogenide-based memory devices |
US7035141B1 (en) * | 2004-11-17 | 2006-04-25 | Spansion Llc | Diode array architecture for addressing nanoscale resistive memory arrays |
US20060108667A1 (en) | 2004-11-22 | 2006-05-25 | Macronix International Co., Ltd. | Method for manufacturing a small pin on integrated circuits or other devices |
US7960712B2 (en) | 2004-12-27 | 2011-06-14 | Nec Corporation | Switching element, switching element drive method and fabrication method, reconfigurable logic integrated circuit, and memory element |
US7046550B1 (en) * | 2005-01-18 | 2006-05-16 | International Business Machines Corporation | Cross-point memory architecture with improved selectivity |
US7208372B2 (en) | 2005-01-19 | 2007-04-24 | Sharp Laboratories Of America, Inc. | Non-volatile memory resistor cell with nanotip electrode |
KR100682926B1 (ko) | 2005-01-31 | 2007-02-15 | 삼성전자주식회사 | 저항체를 이용한 비휘발성 메모리 소자 및 그 제조방법 |
DE102005005938B4 (de) | 2005-02-09 | 2009-04-30 | Qimonda Ag | Resistives Speicherelement mit verkürzter Löschzeit, Verfahren zur Herstellung und Speicherzellen-Anordnung |
JP4924419B2 (ja) | 2005-02-18 | 2012-04-25 | 富士通セミコンダクター株式会社 | 記憶素子マトリックス、及び、その記憶素子マトリックスを用いた半導体回路装置 |
FR2882828B1 (fr) * | 2005-03-03 | 2007-04-06 | Saint Gobain | Procede d'alimentation d'un dispositif electrocommandable a proprietes optiques et/ou energetiques variables |
JP2006267411A (ja) | 2005-03-23 | 2006-10-05 | Victor Co Of Japan Ltd | 液晶表示装置及び液晶表示方法。 |
KR100697282B1 (ko) | 2005-03-28 | 2007-03-20 | 삼성전자주식회사 | 저항 메모리 셀, 그 형성 방법 및 이를 이용한 저항 메모리배열 |
US7154774B2 (en) | 2005-03-30 | 2006-12-26 | Ovonyx, Inc. | Detecting switching of access elements of phase change memory cells |
US8031509B2 (en) | 2008-12-19 | 2011-10-04 | Unity Semiconductor Corporation | Conductive metal oxide structures in non-volatile re-writable memory devices |
US7323349B2 (en) | 2005-05-02 | 2008-01-29 | Sharp Laboratories Of America, Inc. | Self-aligned cross point resistor memory array |
US7782650B2 (en) * | 2005-05-09 | 2010-08-24 | Nantero, Inc. | Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same |
US9196615B2 (en) | 2005-05-09 | 2015-11-24 | Nantero Inc. | Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same |
US7585724B2 (en) | 2005-05-10 | 2009-09-08 | Elite Semiconductor Memory Technology, Inc. | FLASH memory device and method of manufacture |
KR100655447B1 (ko) | 2005-06-07 | 2006-12-08 | 삼성전자주식회사 | 플로팅 게이트를 갖는 비휘발성 기억 소자 및 그 형성 방법 |
US7238994B2 (en) | 2005-06-17 | 2007-07-03 | Macronix International Co., Ltd. | Thin film plate phase change ram circuit and manufacturing method |
US7321130B2 (en) | 2005-06-17 | 2008-01-22 | Macronix International Co., Ltd. | Thin film fuse phase change RAM and manufacturing method |
US7514288B2 (en) | 2005-06-17 | 2009-04-07 | Macronix International Co., Ltd. | Manufacturing methods for thin film fuse phase change ram |
US7167397B2 (en) * | 2005-06-21 | 2007-01-23 | Intel Corporation | Apparatus and method for programming a memory array |
US20070010082A1 (en) | 2005-07-05 | 2007-01-11 | Cay-Uwe Pinnow | Structure and method for manufacturing phase change memories with particular switching characteristics |
US7446010B2 (en) | 2005-07-18 | 2008-11-04 | Sharp Laboratories Of America, Inc. | Metal/semiconductor/metal (MSM) back-to-back Schottky diode |
CN101228092A (zh) | 2005-07-22 | 2008-07-23 | 高通股份有限公司 | 用于mems装置的支撑结构及其方法 |
US7521705B2 (en) | 2005-08-15 | 2009-04-21 | Micron Technology, Inc. | Reproducible resistance variable insulating memory devices having a shaped bottom electrode |
JP4309877B2 (ja) | 2005-08-17 | 2009-08-05 | シャープ株式会社 | 半導体記憶装置 |
US20070048990A1 (en) | 2005-08-30 | 2007-03-01 | Sharp Laboratories Of America, Inc. | Method of buffer layer formation for RRAM thin film deposition |
KR100630437B1 (ko) | 2005-08-31 | 2006-10-02 | 삼성전자주식회사 | 비휘발성 유기물 저항 메모리 장치 및 그 제조 방법 |
KR100665227B1 (ko) * | 2005-10-18 | 2007-01-09 | 삼성전자주식회사 | 상변화 메모리 장치 및 그 제조 방법 |
US7236389B2 (en) | 2005-11-17 | 2007-06-26 | Sharp Laboratories Of America, Inc. | Cross-point RRAM memory array having low bit line crosstalk |
US8106375B2 (en) | 2005-11-30 | 2012-01-31 | The Trustees Of The University Of Pennsylvania | Resistance-switching memory based on semiconductor composition of perovskite conductor doped perovskite insulator |
US7666526B2 (en) | 2005-11-30 | 2010-02-23 | The Trustees Of The University Of Pennsylvania | Non-volatile resistance-switching oxide thin film devices |
US20070132049A1 (en) | 2005-12-12 | 2007-06-14 | Stipe Barry C | Unipolar resistance random access memory (RRAM) device and vertically stacked architecture |
PL204873B1 (pl) | 2005-12-15 | 2010-02-26 | Wagony & Sacute Widnica Spo & | Mechanizm rozładowczy klap zsypowych wagonu |
JP4054347B2 (ja) | 2005-12-16 | 2008-02-27 | シャープ株式会社 | 不揮発性半導体記憶装置 |
ATE480873T1 (de) | 2005-12-20 | 2010-09-15 | Nxp Bv | Vertikale phasenwechsel-speicherzelle und herstellungsverfahren dafür |
KR100655082B1 (ko) | 2005-12-23 | 2006-12-08 | 삼성전자주식회사 | 상변화 메모리 소자 및 그 제조방법 |
US7531825B2 (en) | 2005-12-27 | 2009-05-12 | Macronix International Co., Ltd. | Method for forming self-aligned thermal isolation cell for a variable resistance memory array |
US7560337B2 (en) | 2006-01-09 | 2009-07-14 | Macronix International Co., Ltd. | Programmable resistive RAM and manufacturing method |
KR101186293B1 (ko) | 2006-01-19 | 2012-09-27 | 삼성전자주식회사 | 배리스터를 포함하는 저항성 메모리 소자 및 그 동작 방법 |
JP2007201081A (ja) | 2006-01-25 | 2007-08-09 | Elpida Memory Inc | 半導体記憶装置 |
US7456421B2 (en) | 2006-01-30 | 2008-11-25 | Macronix International Co., Ltd. | Vertical side wall active pin structures in a phase change memory and manufacturing methods |
JP2007213639A (ja) * | 2006-02-07 | 2007-08-23 | Renesas Technology Corp | 不揮発性半導体記憶装置 |
KR100723420B1 (ko) | 2006-02-20 | 2007-05-30 | 삼성전자주식회사 | 비정질 합금 산화층을 포함하는 비휘발성 메모리 소자 |
KR100707212B1 (ko) | 2006-03-08 | 2007-04-13 | 삼성전자주식회사 | 나노 와이어 메모리 소자 및 그 제조 방법 |
KR100745764B1 (ko) | 2006-03-09 | 2007-08-02 | 삼성전자주식회사 | 나노 와이어 메모리 소자의 제조 방법 및 이 방법에사용되는 나노 와이어 형성 제어 시스템 |
KR101176543B1 (ko) | 2006-03-10 | 2012-08-28 | 삼성전자주식회사 | 저항성 메모리소자 |
US8395199B2 (en) | 2006-03-25 | 2013-03-12 | 4D-S Pty Ltd. | Systems and methods for fabricating self-aligned memory cell |
US20070246795A1 (en) | 2006-04-20 | 2007-10-25 | Micron Technology, Inc. | Dual depth shallow trench isolation and methods to form same |
KR101213702B1 (ko) | 2006-04-21 | 2012-12-18 | 삼성전자주식회사 | 비휘발성 메모리 소자, 그 동작 방법, 및 그 제조 방법 |
US7606055B2 (en) | 2006-05-18 | 2009-10-20 | Micron Technology, Inc. | Memory architecture and cell design employing two access transistors |
KR101206034B1 (ko) | 2006-05-19 | 2012-11-28 | 삼성전자주식회사 | 산소결핍 금속산화물을 이용한 비휘발성 메모리 소자 및 그제조방법 |
KR100833903B1 (ko) | 2006-06-13 | 2008-06-03 | 광주과학기술원 | 비휘발성 기억소자, 그 제조방법 및 그 제조장치 |
KR100818271B1 (ko) | 2006-06-27 | 2008-03-31 | 삼성전자주식회사 | 펄스전압을 인가하는 비휘발성 메모리 소자의 문턱 스위칭동작 방법 |
KR101159075B1 (ko) | 2006-06-27 | 2012-06-25 | 삼성전자주식회사 | n+ 계면층을 구비한 가변 저항 랜덤 액세스 메모리 소자 |
US7569459B2 (en) | 2006-06-30 | 2009-08-04 | International Business Machines Corporation | Nonvolatile programmable resistor memory cell |
ATE493522T1 (de) | 2006-07-04 | 2011-01-15 | Basf Se | Elektrochemische herstellung sterisch gehinderter amine |
US7696077B2 (en) | 2006-07-14 | 2010-04-13 | Micron Technology, Inc. | Bottom electrode contacts for semiconductor devices and methods of forming same |
US7932548B2 (en) | 2006-07-14 | 2011-04-26 | 4D-S Pty Ltd. | Systems and methods for fabricating self-aligned memory cell |
JP2008028228A (ja) | 2006-07-24 | 2008-02-07 | Seiko Epson Corp | 可変抵抗素子および抵抗変化型メモリ装置 |
JP4526587B2 (ja) | 2006-07-27 | 2010-08-18 | パナソニック株式会社 | 不揮発性半導体記憶装置およびその製造方法 |
KR101309111B1 (ko) | 2006-07-27 | 2013-09-17 | 삼성전자주식회사 | 폴리실리콘 패턴의 형성방법과 폴리실리콘 패턴을 포함한다층 교차점 저항성 메모리 소자 및 그의 제조방법 |
KR100749740B1 (ko) | 2006-08-01 | 2007-08-17 | 삼성전자주식회사 | 상변화 메모리 장치의 제조 방법 |
US7515454B2 (en) | 2006-08-02 | 2009-04-07 | Infineon Technologies Ag | CBRAM cell and CBRAM array, and method of operating thereof |
US7727908B2 (en) | 2006-08-03 | 2010-06-01 | Micron Technology, Inc. | Deposition of ZrA1ON films |
JP4344372B2 (ja) | 2006-08-22 | 2009-10-14 | シャープ株式会社 | 半導体記憶装置及びその駆動方法 |
KR100755409B1 (ko) | 2006-08-28 | 2007-09-04 | 삼성전자주식회사 | 저항 메모리 소자의 프로그래밍 방법 |
JP4823316B2 (ja) | 2006-09-05 | 2011-11-24 | 富士通株式会社 | 不揮発性半導体記憶装置の書き込み方法 |
US7553758B2 (en) | 2006-09-18 | 2009-06-30 | Samsung Electronics Co., Ltd. | Method of fabricating interconnections of microelectronic device using dual damascene process |
JP2008078404A (ja) | 2006-09-21 | 2008-04-03 | Toshiba Corp | 半導体メモリ及びその製造方法 |
US7751163B2 (en) | 2006-09-29 | 2010-07-06 | Qimonda Ag | Electric device protection circuit and method for protecting an electric device |
US8058643B2 (en) | 2006-09-29 | 2011-11-15 | The Board Of Trustees Of The Leland Stanford Junior University | Electrochemical memory with internal boundary |
KR100819099B1 (ko) | 2006-10-02 | 2008-04-03 | 삼성전자주식회사 | 가변저항 반도체 메모리 장치 |
KR100772904B1 (ko) | 2006-10-02 | 2007-11-05 | 삼성전자주식회사 | 가변저항 메모리 장치 및 그 제조 방법 |
KR100858083B1 (ko) | 2006-10-18 | 2008-09-10 | 삼성전자주식회사 | 하부전극 콘택층과 상변화층 사이에 넓은 접촉면적을 갖는상변화 메모리 소자 및 그 제조 방법 |
US10134985B2 (en) | 2006-10-20 | 2018-11-20 | The Regents Of The University Of Michigan | Non-volatile solid state resistive switching devices |
US20080102278A1 (en) | 2006-10-27 | 2008-05-01 | Franz Kreupl | Carbon filament memory and method for fabrication |
KR100827661B1 (ko) | 2006-10-31 | 2008-05-07 | 삼성전자주식회사 | 이중의 하부 전극을 갖는 상변화 기억소자 및 그 제조방법 |
US7639523B2 (en) | 2006-11-08 | 2009-12-29 | Symetrix Corporation | Stabilized resistive switching memory |
US7872900B2 (en) | 2006-11-08 | 2011-01-18 | Symetrix Corporation | Correlated electron memory |
KR100827697B1 (ko) | 2006-11-10 | 2008-05-07 | 삼성전자주식회사 | 3차원 구조를 가지는 반도체 메모리 장치 및 셀 어레이구조 |
KR101196392B1 (ko) | 2006-11-28 | 2012-11-02 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조 방법 |
US7864568B2 (en) | 2006-12-07 | 2011-01-04 | Renesas Electronics Corporation | Semiconductor storage device |
US7557424B2 (en) | 2007-01-03 | 2009-07-07 | International Business Machines Corporation | Reversible electric fuse and antifuse structures for semiconductor devices |
US8675571B2 (en) | 2007-01-04 | 2014-03-18 | Nokia Corporation | Apparatus, methods and computer program products providing a common signaling entry for a modular control channel structure |
KR100881292B1 (ko) | 2007-01-23 | 2009-02-04 | 삼성전자주식회사 | 3차원 적층구조를 가지는 저항성 반도체 메모리 장치 및그의 제어방법 |
JP5091491B2 (ja) | 2007-01-23 | 2012-12-05 | 株式会社東芝 | 不揮発性半導体記憶装置 |
KR100885184B1 (ko) | 2007-01-30 | 2009-02-23 | 삼성전자주식회사 | 전기장 및 자기장에 의해 독립적으로 제어될 수 있는 저항특성을 갖는 메모리 장치 및 그 동작 방법 |
US7800093B2 (en) | 2007-02-01 | 2010-09-21 | Qimonda North America Corp. | Resistive memory including buried word lines |
JP2008192995A (ja) | 2007-02-07 | 2008-08-21 | Matsushita Electric Ind Co Ltd | 抵抗変化素子とその製造方法ならびにそれを用いた抵抗変化型メモリ |
US20080185687A1 (en) | 2007-02-07 | 2008-08-07 | Industry-University Cooperation Foundation Hanyang University | Memory device and method for fabricating the same |
WO2008102320A2 (en) | 2007-02-21 | 2008-08-28 | L'air Liquide-Societe Anonyme Pour L'etude Et L'exploitation Des Procedes Georges Claude | Methods for forming a ruthenium-based film on a substrate |
US7382647B1 (en) | 2007-02-27 | 2008-06-03 | International Business Machines Corporation | Rectifying element for a crosspoint based memory array architecture |
KR100852206B1 (ko) | 2007-04-04 | 2008-08-13 | 삼성전자주식회사 | 저항 메모리 소자 및 그 제조 방법. |
US7723786B2 (en) | 2007-04-11 | 2010-05-25 | Ronald Kakoschke | Apparatus of memory array using FinFETs |
US7569844B2 (en) | 2007-04-17 | 2009-08-04 | Macronix International Co., Ltd. | Memory cell sidewall contacting side electrode |
US7755076B2 (en) | 2007-04-17 | 2010-07-13 | Macronix International Co., Ltd. | 4F2 self align side wall active phase change memory |
CN100521278C (zh) | 2007-04-19 | 2009-07-29 | 复旦大学 | 以CuxO为存储介质的RRAM的制备方法 |
CN101542632B (zh) | 2007-06-01 | 2012-12-26 | 松下电器产业株式会社 | 电阻变化型存储装置 |
US7459716B2 (en) * | 2007-06-11 | 2008-12-02 | Kabushiki Kaisha Toshiba | Resistance change memory device |
US7920408B2 (en) | 2007-06-22 | 2011-04-05 | Panasonic Corporation | Resistance change nonvolatile memory device |
US8513637B2 (en) | 2007-07-13 | 2013-08-20 | Macronix International Co., Ltd. | 4F2 self align fin bottom electrodes FET drive phase change memory |
TWI402980B (zh) | 2007-07-20 | 2013-07-21 | Macronix Int Co Ltd | 具有緩衝層之電阻式記憶結構 |
KR101344346B1 (ko) | 2007-07-25 | 2013-12-24 | 삼성전자주식회사 | 상변화 기억 소자 및 그 형성 방법 |
JP5088036B2 (ja) | 2007-08-06 | 2012-12-05 | ソニー株式会社 | 記憶素子および記憶装置 |
US7772580B2 (en) | 2007-08-10 | 2010-08-10 | Qimonda Ag | Integrated circuit having a cell with a resistivity changing layer |
JP2009059735A (ja) | 2007-08-29 | 2009-03-19 | Elpida Memory Inc | 半導体記憶装置 |
TW200913249A (en) | 2007-09-04 | 2009-03-16 | Ind Tech Res Inst | Phase-change memory and fabrication method thereof |
US7838861B2 (en) | 2007-09-17 | 2010-11-23 | Qimonda Ag | Integrated circuits; methods for manufacturing an integrated circuit and memory module |
JP2009081251A (ja) | 2007-09-26 | 2009-04-16 | Panasonic Corp | 抵抗変化素子とその製造方法ならびに抵抗変化型メモリ |
US8665629B2 (en) | 2007-09-28 | 2014-03-04 | Qimonda Ag | Condensed memory cell structure using a FinFET |
KR20090055874A (ko) | 2007-11-29 | 2009-06-03 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조 방법 |
JP4466738B2 (ja) | 2008-01-09 | 2010-05-26 | ソニー株式会社 | 記憶素子および記憶装置 |
JP2009168867A (ja) | 2008-01-11 | 2009-07-30 | Hitachi Displays Ltd | 表示装置 |
US7768812B2 (en) | 2008-01-15 | 2010-08-03 | Micron Technology, Inc. | Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices |
JP5049814B2 (ja) | 2008-02-14 | 2012-10-17 | 株式会社東芝 | 不揮発性半導体記憶装置のデータ書き込み方法 |
US7742324B2 (en) | 2008-02-19 | 2010-06-22 | Micron Technology, Inc. | Systems and devices including local data lines and methods of using, making, and operating the same |
KR100978911B1 (ko) * | 2008-02-28 | 2010-08-31 | 삼성전자주식회사 | 반도체 장치 및 그의 형성방법 |
JP2009212202A (ja) | 2008-03-03 | 2009-09-17 | Elpida Memory Inc | 相変化メモリ装置およびその製造方法 |
US7960216B2 (en) | 2008-05-10 | 2011-06-14 | Intermolecular, Inc. | Confinement techniques for non-volatile resistive-switching memories |
US8343813B2 (en) | 2009-04-10 | 2013-01-01 | Intermolecular, Inc. | Resistive-switching memory elements having improved switching characteristics |
CN101546602B (zh) | 2008-03-27 | 2014-05-14 | 三星电子株式会社 | 使用可变电阻元件的非易失性存储器设备 |
US7969776B2 (en) | 2008-04-03 | 2011-06-28 | Micron Technology, Inc. | Data cells with drivers and methods of making and operating the same |
US8034655B2 (en) | 2008-04-08 | 2011-10-11 | Micron Technology, Inc. | Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays |
KR20090108804A (ko) | 2008-04-14 | 2009-10-19 | 윤진수 | 김치 분말을 포함하는 식품 제조 방법 |
DE102008019860B4 (de) | 2008-04-15 | 2010-10-07 | Technische Universität Dresden | Vorrichtung, Verfahren und Verwendung des Verfahrens zur Erzeugung von schaltbarem temporärem Magnetismus in oxidischen Materialien mittels elektrischer Felder |
KR20090109804A (ko) | 2008-04-16 | 2009-10-21 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조 방법 |
US8098520B2 (en) | 2008-04-25 | 2012-01-17 | Seagate Technology Llc | Storage device including a memory cell having multiple memory layers |
US7969806B2 (en) | 2008-04-28 | 2011-06-28 | Qimonda Ag | Systems and methods for writing to a memory |
JP2009267219A (ja) | 2008-04-28 | 2009-11-12 | Hitachi Ltd | 半導体記憶装置およびその製造方法 |
US8053364B2 (en) | 2008-05-01 | 2011-11-08 | Intermolecular, Inc. | Closed-loop sputtering controlled to enhance electrical characteristics in deposited layer |
US8062918B2 (en) | 2008-05-01 | 2011-11-22 | Intermolecular, Inc. | Surface treatment to improve resistive-switching characteristics |
US8129704B2 (en) | 2008-05-01 | 2012-03-06 | Intermolecular, Inc. | Non-volatile resistive-switching memories |
US8551809B2 (en) | 2008-05-01 | 2013-10-08 | Intermolecular, Inc. | Reduction of forming voltage in semiconductor devices |
US8211743B2 (en) | 2008-05-02 | 2012-07-03 | Micron Technology, Inc. | Methods of forming non-volatile memory cells having multi-resistive state material between conductive electrodes |
US8284596B2 (en) | 2008-06-09 | 2012-10-09 | Qimonda Ag | Integrated circuit including an array of diodes coupled to a layer of resistance changing material |
US8134137B2 (en) | 2008-06-18 | 2012-03-13 | Micron Technology, Inc. | Memory device constructions, memory cell forming methods, and semiconductor construction forming methods |
US8114468B2 (en) | 2008-06-18 | 2012-02-14 | Boise Technology, Inc. | Methods of forming a non-volatile resistive oxide memory array |
KR101407362B1 (ko) | 2008-06-23 | 2014-06-16 | 삼성전자주식회사 | 상 변화 메모리 장치 |
US7795109B2 (en) | 2008-06-23 | 2010-09-14 | Qimonda Ag | Isolation trenches with conductive plates |
JP2010009669A (ja) | 2008-06-26 | 2010-01-14 | Toshiba Corp | 半導体記憶装置 |
KR20100001260A (ko) | 2008-06-26 | 2010-01-06 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조 방법 |
US7732235B2 (en) | 2008-06-30 | 2010-06-08 | Sandisk 3D Llc | Method for fabricating high density pillar structures by double patterning using positive photoresist |
US9343665B2 (en) | 2008-07-02 | 2016-05-17 | Micron Technology, Inc. | Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array |
JP5100555B2 (ja) | 2008-07-30 | 2012-12-19 | 株式会社東芝 | 半導体記憶装置 |
CN101350360B (zh) | 2008-08-29 | 2011-06-01 | 中国科学院上海微***与信息技术研究所 | 一种三维堆叠非相变所致电阻转换存储装置及其制造方法 |
KR20100032572A (ko) | 2008-09-18 | 2010-03-26 | 주식회사 하이닉스반도체 | 저항성 메모리 소자 및 그 제조 방법 |
KR101424138B1 (ko) | 2008-09-19 | 2014-08-04 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조 방법 |
US8355274B2 (en) | 2008-09-19 | 2013-01-15 | Panasonic Corporation | Current steering element, storage element, storage device, and method for manufacturing current steering element |
JP5702725B2 (ja) | 2008-10-08 | 2015-04-15 | ザ・リージェンツ・オブ・ザ・ユニバーシティ・オブ・ミシガンThe Regents Of The University Of Michigan | 調整可能な抵抗を備えたシリコン系ナノスケール抵抗素子 |
US8063394B2 (en) | 2008-10-08 | 2011-11-22 | Qimonda Ag | Integrated circuit |
KR20100041155A (ko) | 2008-10-13 | 2010-04-22 | 삼성전자주식회사 | 저항성 메모리 소자 |
US7897955B2 (en) | 2008-11-03 | 2011-03-01 | Seagate Technology Llc | Programmable resistive memory cell with filament placement structure |
US8022547B2 (en) | 2008-11-18 | 2011-09-20 | Seagate Technology Llc | Non-volatile memory cells including small volume electrical contact regions |
US20100135061A1 (en) | 2008-12-02 | 2010-06-03 | Shaoping Li | Non-Volatile Memory Cell with Ferroelectric Layer Configurations |
US20100140578A1 (en) | 2008-12-05 | 2010-06-10 | Seagate Technology Llc | Non volatile memory cells including a composite solid electrolyte layer |
WO2010068221A1 (en) | 2008-12-12 | 2010-06-17 | Hewlett-Packard Development Company, L.P. | Memristive device |
KR20100076274A (ko) | 2008-12-26 | 2010-07-06 | 주식회사 하이닉스반도체 | 상변화 메모리 소자 및 그 제조방법 |
TWI401796B (zh) | 2008-12-30 | 2013-07-11 | Ind Tech Res Inst | 導通微通道記憶體元件及其製造方法 |
KR20100078808A (ko) | 2008-12-30 | 2010-07-08 | 삼성전자주식회사 | 저항성 메모리소자 |
WO2010082923A2 (en) | 2009-01-13 | 2010-07-22 | Hewlett-Packard Development Company, L.P. | Programmable bipolar electronic device |
US8431921B2 (en) | 2009-01-13 | 2013-04-30 | Hewlett-Packard Development Company, L.P. | Memristor having a triangular shaped electrode |
KR101583717B1 (ko) | 2009-01-13 | 2016-01-11 | 삼성전자주식회사 | 저항 메모리 장치의 제조방법 |
JP2010165803A (ja) | 2009-01-14 | 2010-07-29 | Toshiba Corp | 半導体記憶装置の製造方法及び半導体記憶装置 |
US8614432B2 (en) | 2009-01-15 | 2013-12-24 | Hewlett-Packard Development Company, L.P. | Crystalline silicon-based memristive device with multiple mobile dopant species |
WO2010085241A1 (en) | 2009-01-20 | 2010-07-29 | Hewlett-Packard Development Company, L.P. | Multilayer memristive devices |
WO2010087854A1 (en) | 2009-01-30 | 2010-08-05 | Hewlett-Packard Development Company, L.P. | Memristive transistor memory |
US8487291B2 (en) | 2009-01-30 | 2013-07-16 | Seagate Technology Llc | Programmable metallization memory cell with layered solid electrolyte structure |
US8134138B2 (en) | 2009-01-30 | 2012-03-13 | Seagate Technology Llc | Programmable metallization memory cell with planarized silver electrode |
TWI394231B (zh) | 2009-02-03 | 2013-04-21 | Nanya Technology Corp | 非揮發性記憶體胞元及其製造方法 |
JP2010192569A (ja) | 2009-02-17 | 2010-09-02 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2010192646A (ja) | 2009-02-18 | 2010-09-02 | Toshiba Corp | 半導体装置及びその製造方法 |
US8021897B2 (en) | 2009-02-19 | 2011-09-20 | Micron Technology, Inc. | Methods of fabricating a cross point memory array |
WO2010101340A1 (ko) | 2009-03-05 | 2010-09-10 | 광주과학기술원 | 3차원 구조를 갖는 저항 변화 메모리 소자, 저항 변화 메모리 소자 어레이, 전자제품 및 상기 소자 제조방법 |
US8773881B2 (en) | 2009-03-10 | 2014-07-08 | Contour Semiconductor, Inc. | Vertical switch three-dimensional memory array |
US8410559B2 (en) | 2009-03-19 | 2013-04-02 | International Business Machines Corporation | Selectively self-assembling oxygen diffusion barrier |
JP4810581B2 (ja) | 2009-03-25 | 2011-11-09 | 株式会社東芝 | 不揮発性記憶装置 |
US8420478B2 (en) | 2009-03-31 | 2013-04-16 | Intermolecular, Inc. | Controlled localized defect paths for resistive memories |
US7983065B2 (en) | 2009-04-08 | 2011-07-19 | Sandisk 3D Llc | Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines |
US8199576B2 (en) | 2009-04-08 | 2012-06-12 | Sandisk 3D Llc | Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a double-global-bit-line architecture |
US8351236B2 (en) | 2009-04-08 | 2013-01-08 | Sandisk 3D Llc | Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture |
JP2010263211A (ja) | 2009-05-04 | 2010-11-18 | Samsung Electronics Co Ltd | 積層メモリ素子 |
CN102026154B (zh) | 2009-09-23 | 2014-11-05 | 中兴通讯股份有限公司 | 一种媒体修改方法及*** |
US8578317B2 (en) | 2009-10-30 | 2013-11-05 | Synopsys, Inc. | Routing method for flip chip package and apparatus using the same |
KR20120120110A (ko) | 2009-11-16 | 2012-11-01 | 가부시키가이샤 우에하라 오티이씨 겐큐쇼 | 플라스틱 처리 장치 |
CN101703051B (zh) | 2009-12-03 | 2012-10-17 | 湖南化工研究院 | 含氰虫酰胺和杀虫单的杀虫组合物及其用途 |
TWI492432B (zh) | 2009-12-17 | 2015-07-11 | Hitachi Ltd | Semiconductor memory device and manufacturing method thereof |
US8048755B2 (en) | 2010-02-08 | 2011-11-01 | Micron Technology, Inc. | Resistive memory and methods of processing resistive memory |
US8427859B2 (en) | 2010-04-22 | 2013-04-23 | Micron Technology, Inc. | Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells |
US8411477B2 (en) | 2010-04-22 | 2013-04-02 | Micron Technology, Inc. | Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells |
WO2012021168A1 (en) | 2010-08-09 | 2012-02-16 | Ck Technologies, Inc. | Cable / harness test connector |
US9454997B2 (en) | 2010-12-02 | 2016-09-27 | Micron Technology, Inc. | Array of nonvolatile memory cells having at least five memory cells per unit cell, having a plurality of the unit cells which individually comprise three elevational regions of programmable material, and/or having a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells; array of vertically stacked tiers of nonvolatile memory cells |
CN104040633B (zh) | 2010-12-14 | 2017-06-13 | 桑迪士克科技有限责任公司 | 用于具有垂直位线的三维非易失性存储器的架构 |
US8431458B2 (en) | 2010-12-27 | 2013-04-30 | Micron Technology, Inc. | Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells |
US8791447B2 (en) | 2011-01-20 | 2014-07-29 | Micron Technology, Inc. | Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells |
US8537592B2 (en) | 2011-04-15 | 2013-09-17 | Micron Technology, Inc. | Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells |
-
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1444284A (zh) * | 2002-03-12 | 2003-09-24 | 三菱电机株式会社 | 具有电位控制电路的半导体存储器 |
CN1459792A (zh) * | 2002-05-22 | 2003-12-03 | 惠普公司 | 具有串联二极管的磁随机存取存储器的三次取样读出 |
US6693846B2 (en) * | 2002-05-24 | 2004-02-17 | Infineon Technologies Ag | Command controller for an integrated circuit memory device and test circuitry thereof |
CN1624803A (zh) * | 2003-12-05 | 2005-06-08 | 株式会社瑞萨科技 | 半导体集成电路装置 |
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