CN101894829A - 堆叠式封装结构 - Google Patents

堆叠式封装结构 Download PDF

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CN101894829A
CN101894829A CN2009101074891A CN200910107489A CN101894829A CN 101894829 A CN101894829 A CN 101894829A CN 2009101074891 A CN2009101074891 A CN 2009101074891A CN 200910107489 A CN200910107489 A CN 200910107489A CN 101894829 A CN101894829 A CN 101894829A
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weld pad
substrate
chip
packaging body
base plate
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CN101894829B (zh
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傅敬尧
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- Core Of Electronic Science And Technology (zhongshan) Co Ltd
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AMBIT ELECTRONICS (ZHONGSHAN) Co Ltd
Hon Hai Precision Industry Co Ltd
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Abstract

一种堆叠式封装结构，包括N(N≥2)个呈堆叠式设置的封装体，每一个封装体包括基板及封装在所述基板上的芯片，所述基板包括上表面及下表面。其中，所述基板的上表面包括N-1个焊垫，所述基板的下表面包括N个焊垫，所述基板的上表面的第K(K＝1，2，...(N-1))个焊垫与下表面的第K个焊垫相对设置，且所述上表面的第K个焊垫与所述下表面的第K+1个焊垫电性连接；每一个封装体的芯片与基板下表面的第1个焊垫电性连接。每相邻上下两层基板中上层基板的下表面的第K(K＝(1，2，...N-1))个焊垫与下层基板上表面的第K(K＝(1，2，...N-1))个焊垫分别相对设置，并通过锡球连通。

Description

堆叠式封装结构
技术领域
本发明涉及一种封装结构，尤其涉及一种堆叠式封装结构。
背景技术
在电子产品功能不断增加而体积又必须轻薄短小的趋势下，将若干个芯片堆叠式封装使用，可以达到轻、薄、短小的目的。
图1所示为习知堆叠式封装结构10。所述堆叠式封装结构10包括3个封装体11、12、13。每一个封装体均包括基板15及设于基板15上表面的芯片16。基板15上设有3对焊垫151、152、153，每一对焊垫分别相对设置在基板15的上、下表面并电性连接(如图2所示)。在堆叠的过程中，相邻两个基板的焊垫分别相对设置并通过锡球17相互连通。当通过控制器20的3个引脚21、22、23控制所述3个芯片时，引脚21、22、23分别连接位于底层的封装体13的基板15上的3对焊垫151、152、153以分别控制3个封装体11、12、13(如图3所示)。其中，第一个封装体11的芯片16控制端则需与基板15的第一对焊垫151电性连接，第二个封装体12的芯片16的控制端需与基板15的第二对焊垫152电性连接，第三封装体13的芯片16的控制端需与基板15的第三对焊垫153电性连接，换言之，所述3个封装体11、12、13必须为不同的封装形式，即每一个芯片必须有不同的走线设计，且位置不能相互替换。此种堆叠式封装结构中每一个芯片的封装形式均不相同，不利于规模化制造。
发明内容
有鉴于此，需提供一种能使制程简单，且成品尺寸较小的堆叠式封装结构。
本发明实施方式中的堆叠式封装结构包括N(N≥2)个呈堆叠式设置的封装体，每一个封装体包括基板及封装在所述基板上的芯片，所述基板包括上表面及下表面。其中，所述基板的上表面包括N-1个焊垫，所述基板的下表面包括N个焊垫，所述基板上表面的第K(K＝1，2，...(N-1))个焊垫与下表面的第K个焊垫相对设置，且所述上表面的第K个焊垫与所述下表面的第K+1个焊垫电性连接；每一个封装体的芯片与基板下表面的第1个焊垫电性连接。每相邻上下两层基板中的上层基板下表面的第K(K＝(1，2，...N-1))个焊垫与下层基板上表面的第K(K＝(1，2，...N-1))个焊垫分别相对设置，并通过锡球连通。
作为本发明的进一步改进，所述N个芯片的控制端分别与所述N个基板的下表面的第1个焊垫电性连接，当控制器通过N个引脚分别控制所述芯片时，所述控制器的第1个至第N个引脚分别连接第N层至第1层基板上的芯片控制端以控制第N层至第1层基板上的芯片。
作为本发明的进一步改进，每一个基板还包括一对电性连接焊垫，分别相对设置于所述基板的上下表面且电性连接。
作为本发明的进一步改进，所述基板的上表面均设置凹槽，所述芯片分别容置在所述凹槽中。
本发明提供的堆叠式封装结构，每一个芯片的封装结构均相同，当通过控制器的引脚控制所述芯片时，所述芯片的堆叠位置可以相互替换，从而大大简化了堆叠式封装电路的制程，降低了生产成本。
附图说明
图1是习知堆叠式封装结构的剖面示意图。
图2是图1所示的堆叠式封装结构的侧面剖面示意图。
图3是控制器的引脚控制图1所示的堆叠式封装结构的示意图。
图4是本发明的堆叠式封装结构的剖面示意图。
图5是图4所示的堆叠式封装结构的侧面剖面示意图。
图6是本发明中单个封装体的剖面示意图。
图7是图6中单个封装体的侧面剖面示意图。
图8是本发明一具体实施方式中堆叠式封装结构的剖面示意图。
图9是图8中单个封装体的侧面剖面示意图。
图10是图8中堆叠式封装结构的侧面剖面示意图。
图11是控制器的引脚控制图8所示的堆叠式封装结构的示意图。
具体实施方式
图4是本发明的堆叠式封装结构100的剖视示意图。本发明的堆叠式封装结构100包括N(N≥2)个呈堆叠式设置的封装体30，每一个封装体30均包括芯片32，所述芯片32于所述封装体30中的走线设计均相同，本实施方式中，所述芯片32均相同且具有相同的封装形式。
请同时参阅图6及图7，封装体30包括基板31，芯片32设置于基板31上。基板31为印刷电路板，包括上表面311及下表面312。其中基板31的上表面设凹槽313，芯片32通过黏着剂33及封胶34容置在凹槽313内。
基板31的上表面311包括N-1个焊垫A，下表面312包括N个焊垫B。上表面311的第K(K＝(1，2，...N-1))个焊垫A(K)与下表面312的第K个焊垫B(K)相对设置，且上表面311的第K个焊垫A(K)与下表面312的第K+1个焊垫B(K+1)电性连接。每一个基板31上的芯片32的控制端与基板31下表面的第1个焊垫B1电性连接。
作为进一步改进，基板31上还包括一对电性连接焊垫C，相对设置于基板31的上表面311及下表面312且相互电性连接。
请参阅图5，当将N个封装体30做堆叠式封装时，所述N个基板31呈堆叠式设置，每两个相邻的基板31之间的电性连接焊垫C通过锡球40相互连通以使所述N个基板31电性连接。每相邻上下两层基板31之间的上层基板下表面的第K(K＝(1，2，...N-1))个焊垫B(K)与下层基板上表面的第K(K＝(1，2，...N-1))个焊垫A(K)分别相对设置，且通过锡球40相互连接。换言之，第X(X＝1，2，...(N-1))层基板31(X)的下表面312(X)的N-1个焊垫B分别与第X+1层基板31(X+1)的上表面311(X+1)的N-1个焊垫A相对设置，并通过锡球40相互连通。
当控制器50的N个引脚分别控制所述N个芯片时(未图示)，所述控制器50的N个引脚分别连接第N层基板31(N)的下表面312(N)的N个焊垫B，又，所述N个芯片32的控制端均分别与所述N个基板31下表面的第1个焊垫B1电性连接，因此，控制器50的第1个至第N个引脚分别连接第N层至第1层基板31上的芯片32的控制端以控制第N层至第1层基板31上的芯片32。由于所述N个芯片32一体化设计制造，封装形式均相同，因此，所述N个芯片32在封装时，其堆叠的位置可以相互替换。
为说明的简化，本实施方式中以堆叠式封装结构200包括三个封装体30举例说明，分别为第一个封装体30(1)、第二个封装体30(2)及第三个封装体30(3)(如图8所示)。
请参阅图9，基板31的上表面311的焊垫数量为2个，分别标示为第一个焊垫A1、第二个焊垫A2，基板31的下表面312的焊垫数量为3个，分别标示为第三个焊垫B1、第四个焊垫B2及第五个焊垫B3。其中，上表面311的第一个焊垫A1、第二个焊垫A2分别与下表面312的第三个焊垫B1、第四个焊垫B2相对设置；上表面311的第一个焊垫A1与下表面的第四个焊垫B2连通，上表面311的第二个焊垫A2与下表面312的第五个焊垫B3连通。
请参阅图10，本实施方式中，三个封装体30(1)、30(2)、30(3)的基板31(1)、31(2)、31(3)呈堆叠式设置，第一层基板31(1)的下表面第三个焊垫B1(1)及第四个焊垫B2(1)分别与第二层基板31(2)的上表面第一个焊垫A1(2)，第二个焊垫A2(2)相对设置；第二层基板31(2)的下表面的第三个焊垫B1(2)，第四个焊垫B2(2)分别与第三层基板31(3)的上表面的第一个焊垫A1(3)，第二个焊垫A2(3)相对设置。相邻两基板之相对的焊垫通过锡球40连通。如上所述，基板31的上表面311的第一个焊垫A1与下表面312的第四个焊垫B2连通，上表面311的第二个焊垫A2与下表面312的第五个焊垫B3连通，因此，从图10中可以看到，第三个封装体30(3)的第四个焊垫B2(3)与第二个封装体30(2)的第三个焊垫B1(2)连通；第三个封装体30(3)的第五个焊垫B3(3)与第一个封装体30(1)的第三个焊垫B1(1)连通。
请参阅图11，当控制器50通过引脚51、52、53分别控制三个芯片32(1)、32(2)、32(3)时，控制器50的引脚51、52、53分别连接第三个封装体30(3)的基板31(3)的下表面312(3)的三个焊垫B1(3)、B2(3)及B3(3)，又，每一个芯片32的控制端均与其基板31的下表面312的第三个焊垫B1电性连接，因此，控制器50的三个引脚51、52、53分别连接所述三个芯片32(1)、32(2)、32(3)的控制端以控制所述三个芯片32(1)、32(2)、32(3)。由于所述三个芯片32的封装形式完全相同，因此，所述三个封装体30的位置可以随意互换，大大简化了制程，降低了生产成本。
本发明提供的堆叠式封装结构，N个封装体堆叠式设置，基板上表面的第K(K＝1，2，...(N-1))个焊垫与下表面的第K个焊垫相对设置，且上表面的第K个焊垫与下表面的第K+1个焊垫相通，在芯片堆叠的过程中，每相邻上下两个基板之间的上层基板的下表面的第K(K＝(1，2，...N-1))个焊垫与下层基板的上表面的第K(K＝(1，2，...N-1))个焊垫分别相对设置，且通过锡球相互连接。当通过控制器的N个引脚分别控制所述N个芯片，因每一个芯片的控制端均与基板下表面的第一个焊垫电性连接，因此，控制器的第1个至第N个引脚分别连接第N层至第1层基板上的芯片的控制端以控制第N层至第1层基板上的芯片。由于每一个芯片具有相同的走线设计，因此，所述芯片在封装时，其堆叠位置可以相互替换，从而大大简化堆叠式封装电路的封装制程，降低了生产成本，同时，将芯片容置在基板的凹槽中，降低了产品高度，有效缩小了产品的体积。

Claims (4)

1.一种堆叠式封装结构，包括N(N≥2)个封装体，每一个封装体包括基板及封装在所述基板上的芯片，所述基板包括上表面及下表面；其特征在于：
所述基板的上表面包括N-1个焊垫，下表面包括N个焊垫，所述基板上表面的第K(K＝1，2，...(N-1))个焊垫与下表面的第K个焊垫相对设置，且所述上表面的第K个焊垫与所述下表面的第K+1个焊垫电性连接，每一个封装体的芯片与基板下表面的第1个焊垫电性连接；
所述N个封装体呈堆叠式设置，每相邻上下两层基板的上层基板的下表面的第K(K＝(1，2，...N-1))个焊垫与下层基板的上表面的第K(K＝(1，2，...N-1))个焊垫分别相对设置，并通过锡球相互电性连接。
2.如权利要求1所述的堆叠式封装结构，其特征在于，所述N个芯片的控制端分别与所述N个基板的下表面的第1个焊垫电性连接，当控制器通过N个引脚分别控制所述芯片时，所述控制器的第1个至第N个引脚分别连接第N层至第1层基板上的芯片的控制端以控制第N层至第1层基板上的芯片。
3.如权利要求1所述的堆叠式封装结构，其特征在于，每一个基板还包括一对电性连接焊垫，分别相对设置于所述基板的上下表面且电性连接。
4.如权利要求1所述的堆叠式封装结构，其特征在于，所述基板的上表面均设置凹槽，所述芯片分别容置在所述凹槽中。
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