CN101359659A - 半导体封装及制造方法、半导体模块和包括该模块的装置 - Google Patents

半导体封装及制造方法、半导体模块和包括该模块的装置 Download PDF

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CN101359659A
CN101359659A CNA2008101358884A CN200810135888A CN101359659A CN 101359659 A CN101359659 A CN 101359659A CN A2008101358884 A CNA2008101358884 A CN A2008101358884A CN 200810135888 A CN200810135888 A CN 200810135888A CN 101359659 A CN101359659 A CN 101359659A
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Prior art keywords
substrate
solder bump
semiconductor
semiconductor chip
cavity
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金承宇
梁世暎
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN101359659A publication Critical patent/CN101359659A/zh
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Abstract

本发明公开了一种半导体封装及制造方法、半导体堆叠模块和包括该模块的装置，该模块具有上半导体封装，所述封装包括具有相对的第一和第二表面的基底。由第二表面限定的空腔容纳安装在下半导体封装的基底上的半导体的至少一部分。布置在第一和第二封装之间的多个焊料凸点将两个基底相连。

Description

半导体封装及制造方法、半导体模块和包括该模块的装置
本中请要求于2007年7月31日提交到韩国知识产权局的第10-2007-0077177号韩国专利申请的优先权，该申请的公开通过引用完全包含于此。
技术领域
本发明总体涉及一种堆叠半导体模块和包括该模块的装置，更具体地说，本发明涉及一种由球栅阵列电连接的基底形成的堆叠模块。
背景技术
随着电子产品变得尺寸更小、密度更高并且性能更好，半导体也相应地变得更小，且半导体的组件和连接也变得更密。这又导致了***封装(SIP)和层叠封装(POP，package on package)的发展，在SIP中，多个集成电路被封闭在单个封装或模块中，在POP中，利用焊料凸点(即，球栅阵列(BGA))将单独的半导体封装垂直地堆叠。
在这种POP中，由于通过焊料凸点将上半导体封装连接到下半导体封装的外部区域，所以需要紧密排列焊料凸点。例如，在图1和图2中，传统的半导体堆叠模块10和12分别具有用相同的标号指示的相应的结构。
第一封装14包括一对以已知方式堆叠在一起的半导体芯片16和18。半导体芯片18通过粘合剂安装在基底20上，半导体芯片16也通过粘合剂安装在半导体芯片18上。每个芯片中的内部电路通过引线键合连接到形成在基底20中的布线图案(不可见)，其中，一些引线键合一般在标号20处表示。布线图案依次穿过基底20以连接到多个焊料凸点24。成型(molding)材料26将半导体芯片16、18和引线键合22包封起来。因此，半导体芯片16和18中的内部电路被电连接到焊料凸点24。
在图1的模块10中，第二封装28包括安装在基底30上的单个半导体芯片，在图2的模块12中，第二封装28包括安装在基底30上的一对堆叠的芯片。按与模块10相似的方式，基底30中的布线将第二封装28中的一个半导体芯片或多个半导体芯片中的内部电路与附于第二封装下侧的焊料凸点32相连接。
基底30中的附加布线图案(不可见)也要将焊料凸点24连接到焊料凸点32。然而与这种POP有关的问题会妨碍在第一封装14和第二封装28之间提供良好的电连接。因为焊料凸点24必须足够大以在基底30的顶表面和基底20的底表面之间提供足够空间，来容纳安装在基底30上的半导体芯片封装的高度，所以出现这些问题中的一种。因此，由于焊料凸点必须比安装在基底30上的半导体芯片封装高，所以节距(即，相邻焊料凸点的中心之间的距离)由低端限制。使用具有尽可能最小的节距的大焊料凸点会在相邻焊料凸点彼此接触的时候引起短路。
另一问题涉及精确地确定焊料凸点24的尺寸。需要将焊料凸点24制造的尽可能小以产生最小的节距。这样将密度最大化，因此将可能连接的总数最大化。然而，如果凸点被制造的太小，可能在焊料凸点24和基底30中的电连接之间出现开路。当基底30上的半导体芯片封装的高度比焊料凸点24的高度高时，即使只高一点，也会出现这种情况。
本发明以将对本领域普通技术人员明显的方式来解决这些问题并改善半导体封装和模块。
发明内容
根据本发明的一方面，提供一种半导体堆叠模块，包括：第一基底，具有相对的第一表面和第二表面；空腔，由第一基底的第二表面限定；第一半导体芯片，安装在与空腔相对的第一表面上；第二基底，具有相对的第三表面和第四表面；第二半导体芯片，安装在第二基底的第三表面上；多个焊料凸点，形成在第一基底的第二表面和第二基底的第三表面之间，所述焊料凸点连接两个基底，第二半导体芯片至少部分容纳在空腔中。
根据本发明的另一方面，提供一种半导体堆叠模块，包括：第一基底，具有相对的第一表面和第二表面；第一空腔，由第一基底的第二表面限定；第二基底，具有相对的第三表面和第四表面；第二空腔，由第二基底的第三表面限定；至少一个半导体芯片，安装在限定第一空腔和第二空腔之一的表面上；多个焊料凸点，形成在第一基底的第二表面和第二基底的第三表面之间，所述焊料凸点连接基本上彼此相对的具有空腔的两个基底。
根据本发明的又一方面，提供一种可安装在基本上平坦的表面上的半导体封装，包括：基底，具有相对的第一表面和第二表面，当所述封装安装在基本上平坦的表面上时，第二表面面对所述基本上平坦的表面；基底的基本平坦的第一部分，当所述封装被安装在所述基本上平坦的表面上时，基本平坦的第一部分与所述基本上平坦的表面相隔第一距离；基底的基本平坦的第二部分，与基底的第一部分相邻，当所述封装被安装在所述基本上平坦的表面上时，基底的第二部分与所述基本上平坦的表面相隔与第一距离不同的第二距离；至少一个半导体芯片，安装在基底的第一部分的第一表面上。
根据本发明的又一方面，提供一种存储卡，包括：第一基底，具有相对的第一表面和第二表面；空腔，由第一基底的第二表面限定；第一半导体芯片，安装在第一基底的表面之一上；第二基底，具有相对的第三表面和第四表面；第二半导体芯片，安装在第二基底的第三表面上，所述半导体芯片之一包括存储器，另一个包括控制器；多个焊料凸点，形成在第一基底的第二表面和第二基底的第三表面之间，所述焊料凸点连接两个基底，第二半导体芯片至少部分容纳在空腔中。
根据本发明的又一方面，提供一种电子***，包括：第一基底，具有相对的第一表面和第二表面；空腔，由第一基底的第二表面限定；第一半导体芯片，安装在第一基底的表面之一上；第二基底，具有相对的第三表面和第四表面；第二半导体芯片，安装在第二基底的第三表面上，所述半导体芯片之一包括存储器，另一个包括处理器；多个焊料凸点，形成在第一基底的第二表面和第二基底的第三表面之间，所述焊料凸点连接两个基底，第二半导体芯片至少部分容纳在空腔中；输入/输出装置，将信息传输到所述***并从所述系传输信息。
根据本发明的又一方面，提供一种制造半导体封装的方法，该方法包括以下步骤：将基本上平坦的表面基底置于模具上方，所述模具具有基本平坦的第一表面和基本平坦的第二表面，所述第一表面与基底间隔第一距离，所述第二表面与第一表面相邻并与基底间隔第二距离；将基底压到模具中，直到基底呈现模具表面的形状；在基底的一侧上安装至少一个半导体芯片；在基底的另一侧上安装焊料凸点。
附图说明
图1是现有技术的堆叠模块的侧视图；
图2是另一种现有技术的堆叠模块的侧视图；
图3是根据本发明的第一半导体封装的侧面剖视图；
图4是根据本发明的第一堆叠模块的侧面剖视图，该堆叠模块包括图3的第一半导体封装；
图5是根据本发明的第二堆叠模块的侧面剖视图，该堆叠模块也包括图3的第一半导体封装；
图6是根据本发明的第二半导体封装的侧面剖视图；
图7是根据本发明的第三堆叠模块的侧面剖视图，该堆叠模块包括图6的第二半导体封装；
图8是根据本发明的第三半导体封装的侧面剖视图；
图9是根据本发明的第四堆叠模块的侧面剖视图，该堆叠模块包括图8的第三半导体封装；
图10是根据本发明的第四半导体封装的侧面剖视图；
图11是根据本发明的第五堆叠模块的侧面剖视图，该堆叠模块包括图10的第四半导体封装；
图12是根据本发明的第六堆叠模块的侧面剖视图，该堆叠模块也包括图10的第四半导体封装；
图13是根据本发明构造的卡的示意图；
图14是根据本发明构造的***的示意图；
图15和图16是根据本发明的制造示例性半导体封装的一方面的侧面剖视图；
图17和图18是图15和图16中示出的制造方面的替换方法的侧面剖视图；
图19至图21示出了根据本发明的示例性堆叠模块以及封装的制造的完成。
具体实施方式
一般，在图3中的标号36表示根据本发明构造的半导体封装。封装36包括第一基底40，第一基底40包括第一部分42和第二部分44。基底40具有第一表面46和第二表面48。基底40可由印刷电路板制成，或者可由液晶聚合物或聚酰亚胺构造。部分42和44可由相对硬的材料制造，而连接部分42和44的部分可由柔性基底制造。可选地，将更充分地解释，整个基底40可由成型为图3中示出的形状的单个材料制成。部分42以下的空间在这里被称为空腔。
第一芯片组50安装在基底40的部分42的第一表面46上。第一芯片组由两个半导体芯片52组成。应该注意的是，当这里使用“半导体芯片”时，它可以表示一个或多个半导体芯片(例如，芯片52)，或者可以表示包括多个芯片的单个芯片组。半导体芯片52分别通过粘合剂54固定到基底40的第一表面46并且彼此固定。引线键合(例如引线键合56)将半导体芯片52上的端子与用已知方式形成在基底40上或基底40中的布线图案(不可见)相连。这些布线图案还穿过基底40连接到焊料凸点58。焊料凸点58附于基底40的与第一表面46相对的第二表面48，并附于布线图案中对应的一个布线图案。因此，焊料凸点58和第一芯片组50上的端子之间存在电连接。成型材料60将第一芯片组50和引线键合(例如引线键合56)包封。
现在转到图4，一般，标号34表示包括半导体封装36的堆叠模块。与先前在图3中标记的结构相应的结构具有与图3中相同的标号，或者未标记。第二半导体封装38包括大体沿着第一芯片组50的排放构造的第二芯片组62。在这里，第二芯片组62或它的一个半导体芯片也称为第二半导体芯片。成型材料71将第二芯片组62和引线键合(例如引线键合67)包封。引线键合67将半导体芯片61上的端子连接到用已知方式形成在基底64上或基底64中的布线图案(不可见)。应该理解的是，不同的封装和半导体芯片可同样很好地应用在堆叠模块34中。如半导体封装36，第二芯片组62上的端子连接到引线键合(如所示的)，引线键合又连接到布线图案(不可见)，布线图案在第二基底64的表面上或第二基底64的所述表面中，第二芯片组62安装在第二基底64的表面上。第二基底分别包括第一表面66和第二表面68，第一表面66基本是平坦的。
基底64中或基底64上的布线图案还穿过基底64连接到附加的焊料凸点70。也在基底64上或基底64中的附加布线图案，也将焊料凸点58连接到附加焊料凸点中70选择的一些焊料凸点。换言之，焊料凸点70最终电连接到第一芯片组50和第二芯片组62的内部电路。焊料凸点70可用于将半导体模块34连接到另一板、封装、模块或装置。
在图4中，h1表示基底40的第二部分44上的表面48与基底40的第一部分42上的表面48之间的距离。如图所示，焊料凸点58的直径基本上是h2。h3表示基底64的表面66和基底40的第一部分42上的表面48之间的距离。可以看出，h1加h2等于h3。最后，h4是第二芯片组62和在第二芯片组62的顶表面上的成型材料71的总高度。下面，第二半导体封装38的该部分称为第二半导体封装38的主体(body)。此外，在模块34中，h3比h2大。
图4中的焊料凸点58的节距P1可以通过h1的大小来控制。换言之，h1越大，焊料凸点58的节距会越小。因此，可以以更小的在焊料凸点58和基底64之间的开路风险和更小的由相邻的焊料凸点58彼此接触引起的短路风险来制造更多的连接。虽然将焊料凸点58示出为与附加焊料凸点70的尺寸基本相同，但是，通过增加h1，焊料凸点58可比焊料凸点70小。这为焊料凸点58提供了更小的节距，因此在避免与现有技术有关的开路和短路的同时，提供了更高的密度和更多的连接。
如图4所示的半导体芯片可以是存储芯片或逻辑芯片。例如，由于一些类型的逻辑芯片可以比存储芯片大，所以第一半导体封装36的第一芯片组50可以由逻辑芯片组成，第二半导体封装38的第二芯片组62可以由存储芯片组成。优选地，第一芯片组50比第二芯片组62大，但这不是必需的。可以以任意类型的半导体芯片或芯片组合来构造半导体模块。
在图5中，一般，标号73表示包括图3中的半导体封装36的堆叠模块。与先前在图3中标记的结构相应的结构具有与图3中相同的标号，或者未标记。堆叠模块73包括第二半导体封装75，第二半导体封装75具有安装在基底81上的芯片组77和79。芯片组77和79连接到基底81上的布线图案(不可见)，布线图案也连接到在封装36上的焊料凸点58和在基底81下表面上的焊料凸点。这些连接使用与图4的堆叠模块的方式相同的方式来制成。
转到图6，一般，标号72表示根据本发明构造的另一半导体封装。与先前在图3中标记的结构相应的结构具有与图3中相同的标号，或者未标记。倒装芯片74包括半导体芯片76，半导体芯片76通过焊料凸点(例如，焊料凸点78)连接到基底40中的布线图案。
在图7中，另一种堆叠模块83包括图6中的半导体封装72和图4中的半导体封装38。同图3中的引线键合56一样，图7中的焊料凸点(例如，焊料凸点78)将倒装芯片的内部电路最终连接到半导体封装38上的焊料凸点70。同样如图4所示，半导体封装38中的第二芯片组62最终也连接到焊料凸点70，使得倒装芯片74和第二芯片组62可通过焊料凸点70被连接到另一板、封装、模块或装置。
附加半导体芯片(未示出)可被安装在倒装芯片74上，并且电连接到焊料凸点58。
现在考虑图8，根据本发明的另一半导体封装84包括具有第一部分90和第二部分92的基底88。如图8所示，非平坦部分将第一部分90和第二部分92相连。基底88还包括第一表面94和第二表面96。虚线98指示了基本上平坦的表面，在该平面上可用已知方式将附加焊料凸点100电连接到另一板、封装、模块或装置。在图8中，附加焊料凸点100包括在第二部分92之下的较大的焊料凸点(例如，凸点102)以及在第一部分90之下的较小的焊料凸点(例如，凸点104)。如图8所示，较大和较小的焊料凸点具有的直径导致所有焊料凸点接触由线98表示的基本上平坦的表面。这些附加焊料凸点104在避免与现有技术有关的开路和短路的同时，提供了具有更高密度和更多连接的模块80。
现在转到图9，一般，标号80表示根据本发明构造的另一堆叠模块，该模块包括图8中的半导体封装84。同样，与先前标记的结构相应的结构具有相同的标号，或者未标记。堆叠模块80包括第一半导体封装82和第二半导体封装84。第一半导体封装82包括基本上平坦的表面基底86。除了图9中的基底86基本上平坦而图3中的基底40包括第一部分42和第二部分44之间的非平坦部分之外，封装82与图3中的第一半导体封装36基本相同。
在图9中，第二半导体封装主体的高度用h4b表示，该高度是基底88上的第二芯片组91和成型材料93的高度之和。基底88的第二部分92上的第一表面和第二半导体封装82的基底86的下表面之间的距离用h2b表示。在图9中，基底88的第一部分90上的第一表面94和基底88的第二部分92上的第一表面94之间的距离用h1b表示。h1b越大，h2b就会越小。如附图中所示，h2b可比h4b小。随着h2b变小，焊料凸点中的相邻焊料凸点之间的节距P2会变小，同时保持相邻的焊料凸点之间的短路风险和在焊料凸点和基底88之间的开路风险低。焊料凸点58的更小的节距在避免与现有技术有关的开路和短路的同时，为第一半导体封装82提供更高的密度和更多的连接。
在图10中，一般，标号106表示根据本发明构造的半导体封装。与在前的附图一样，与先前标记的结构相应的结构具有相同的标号，或者未标记。除了通过焊料凸点(例如，焊料凸点110)附于基底40的第一部分42上的表面48的倒装芯片108之外，封装106与图3中的封装36相同。与第一芯片组50一样，用已知方式形成在基底40中或基底40上的布线图案(不可见)将倒装芯片焊料凸点和焊料凸点58相连。
在图11中，焊料凸点58又连接到在板111上或板111中形成的布线图案(不可见)。换言之，通过焊料凸点58形成第一芯片组50和倒装芯片108需要的所有电连接。板111具有安装在其上的电子组件112。板上的布线图案可以将第一芯片组50和/或倒装芯片108与组件112连接。电子组件112可以是电阻器、感应器、电容器或具有电子电路的电子装置。该实施例也提高装置密度并降低装置尺寸。
在图12中，一般，标号114表示根据本发明构造的另一堆叠模块。该堆叠模块包括第一半导体封装36和第二半导体封装84，第一半导体封装36与图3中的半导体封装36大体相同，第二半导体封装84与图9中的第二半导体封装84大体相同。与在前的附图一样，与先前标记的结构相应的结构具有相同的标号，或者未标记。由于基底40和88各自的形状，所以在两个基底之间有足够空间来容纳第二芯片组91和倒装芯片108。最后，用如上所述的方式通过附加焊料凸点100来形成倒装芯片108、第一芯片组50和基底88上的第二芯片组91需要的所有的电连接。
现在转到图13，一般，标号114表示根据本发明构造的卡的示意图。卡114可以是诸如多媒体卡(MMC)或安全数字(SD)卡。卡114包括控制器116和存储器118，存储器118可以是DRAM、闪存、PRAM或其他类型的存储器。一般，用标号120表示的通信信道允许控制器向存储器提供指令，并将数据传入或传出存储器118。控制器116和存储器118可包括根据前述任何实施例的BGA芯片组。
卡114可具有比传统的卡更高的密度。在图4中，可以去掉焊料凸点70并在基底64的第二表面68上形成卡的外部端子(未示出)。这表示第二半导体封装38的基底64可作为卡基底。本发明的所有实施例都可以类似地适于在卡中的应用。
现在考虑图14，一般，标号120表示根据本发明构造的***。***120可以是诸如移动电话、MP3播放器、GPS导航装置、固态盘(SSD)、家用电器等。***120包括：处理器122；存储器124，可以是DRAM、闪存、PRAM或其他类型的存储器；输入/输出装置126。通信信道128允许处理器向存储器提供指令，并通过信道128将数据传入或传出存储器124。可通过输入/输出装置126将数据和命令传输到***120，或者从***120传输数据或命令。处理器122和存储器124可包括根据前述任何实施例的BGA芯片组。与具有相同数量的连接的现有技术相比，本发明减小了电子装置的体积，所以本发明可减小***120的体积。
现在将考虑本发明实施例的制造方法。在图18中，半导体封装36与图3中的半导体封装36基本相同，并且一些结构包括相应的标号。半导体封装36位于模具130的顶部，模具130包括限定第一基底部分42、第二基底部分44和它们之间的过渡部分的凸起区132。多个孔134与为基底40的下侧提供真空的泵(未示出)连通。
有至少两种能够达到如图18所示的制造工艺的状态的方法。在第一方法中，参照图15，通过粘合剂54和引线键合56将半导体装置52附着到基本上平坦的基底40。还可使用倒装芯片键合或硅通孔(TSV)技术将半导体装置52彼此相连。如图15所示，随后将基本上平坦的基底置于模具130上方，并用压机(未示出)将基底挤压成如图16所示的形式。此外，或可选地，通过孔134施加的真空还可将基底吸成如图16所示的模具的形状。
在第二方法中，参照图17，没有在其上安装任何组件的基本上平坦的基底40置于模具130上方，并被挤压或利用施加到孔134的真空吸成如图17所示的形状。然后通过粘合剂54和引线键合56将半导体装置52附着到基底40。与第一方法一样，可使用例如倒装芯片键合或硅通孔(TSV)技术将半导体装置52彼此相连。
下面，不管使用了两种方法中的哪种，如图18所示，用成型材料60将半导体装置52包封，并将基底40从模具130移除。然后，在基底40的下侧上形成焊料凸点(例如，图20中的焊料凸点58)。可通过首先在基底上设置焊料凸点，然后对焊料凸点回流以将其附着到基底40的下侧，来形成这些凸点58，如图3所示。
最后，将焊料凸点58设置在图21中的第二半导体封装38上，并对凸点58执行回流工艺，以使其附于第二半导体封装，如图21所示。
因此，提供一种改善了的堆叠模块，该模块包括一种封装，该封装在另一封装上方，或在安装在板、卡或其它基底上的装置或半导体装置上方。封装上的焊料凸点的直径可减小，从而增加节距，同时降低相邻焊料凸点之间的短路的风险和焊料凸点和其对应的接触之间开路的风险。这有利于增加由焊料凸点形成的电连接的总数。

Claims (35)

1、一种半导体堆叠模块，包括：
第一基底，具有相对的第一表面和第二表面；
空腔，由第一基底的第二表面限定；
第一半导体芯片，安装在与空腔相对的第一表面上；
第二基底，具有相对的第三表面和第四表面；
第二半导体芯片，安装在第二基底的第三表面上；
多个焊料凸点，形成在第一基底的第二表面和第二基底的第三表面之间，所述焊料凸点连接两个基底，第二半导体芯片至少部分容纳在空腔中。
2、如权利要求1所述的半导体堆叠模块，还包括形成在焊料凸点和在第一半导体芯片上形成的端子之间的电连接。
3、如权利要求1所述的半导体堆叠模块，其中，所述模块被构造并布置为安装在基本上平坦的表面上，其中，当如此安装所述半导体堆叠模块时，所述半导体堆叠模块还包括形成在第二基底的第四表面和所述基本上平坦的表面之间的附加焊料凸点。
4、如权利要求3所述的半导体堆叠模块，其中，所有的焊料凸点尺寸基本相同。
5、如权利要求3所述的半导体堆叠模块，其中，形成在第一基底的第二面表和第二基底的第三表面之间的焊料凸点比形成在第二基底的第四表面和基本上平坦的表面之间的附加焊料凸点小。
6、如权利要求3所述的半导体堆叠模块，其中形成在第一基底的第二表面和第二基底的第三表面之间的焊料凸点的节距比所述附加焊料凸点的节距小。
7、如权利要求1所述的半导体堆叠模块，其中，第二半导体芯片的高度比焊料凸点的高度高。
8、如权利要求1所述的半导体堆叠模块，其中，第一半导体芯片包括倒装芯片。
9、如权利要求1所述的半导体堆叠模块，还包括在空腔中安装第二表面上的第三半导体芯片。
10、一种半导体堆叠模块，包括：
第一基底，具有相对的第一表面和第二表面；
第一空腔，由第一基底的第二表面限定；
第二基底，具有相对的第三表面和第四表面；
第二空腔，由第二基底的第三表面限定；
至少一个半导体芯片，安装在限定第一空腔和第二空腔之一的表面上；
多个焊料凸点，形成在第一基底的第二表面和第二基底的第三表面之间，所述焊料凸点连接基本上彼此相对的具有空腔的两个基底。
11、如权利要求10所述的半导体堆叠模块，还包括安装在与由第一基底的第二表面限定的第一空腔相对的第一基底的第一表面上的第二半导体芯片。
12、如权利要求11所述的半导体堆叠模块，其中，所述至少一个半导体芯片安装在由第一基底的第二表面限定的第一空腔中，所述半导体堆叠模块还包括安装在第二基底的第三表面上并且在第二空腔中的第三半导体芯片。
13、如权利要求10所述的半导体堆叠模块，其中，所述模块被构造并布置为安装在基本上平坦的表面上，其中，当如此安装所述模块时，所述模块还包括形成在第二基底的第四表面和所述基本上平坦的表面之间的附加焊料凸点。
14、如权利要求13所述的半导体堆叠模块，其中，在第二空腔下的附加焊料凸点比不在第二空腔下的附加焊料凸点小。
15、一种可安装在基本上平坦的表面上的半导体封装，包括：
基底，具有相对的第一表面和第二表面，当所述封装安装在基本上平坦的表面上时，第二表面面对所述基本上平坦的表面；
基底的基本平坦的第一部分，当所述封装被安装在所述基本上平坦的表面上时，基本平坦的第一部分与所述基本上平坦的表面相隔第一距离；
基底的基本平坦的第二部分，与基底的第一部分相邻，当所述封装被安装在所述基本上平坦的表面上时，基底的第二部分与所述基本上平坦的表面相隔与第一距离不同的第二距离；
至少一个半导体芯片，安装在基底的第一部分的第一表面上。
16、如权利要求15所述的半导体封装，其中，第一距离比第二距离大。
17、如权利要求15所述的半导体封装，其中，第一距离比第二距离小。
18、如权利要求17所述的半导体封装，其中，基底被构造并布置为具有通过焊料凸点安装在基底的基本平坦的第二部分的第一表面上的第二半导体封装，当第二半导体封装如此安装时，所述至少一个半导体芯片的高度比焊料凸点的高度高。
19、如权利要求15所述的半导体封装，其中，所述半导体芯片包括倒装芯片。
20、如权利要求15所述的半导体封装，还包括安装在基底的第一部分的第二表面上的第二半导体芯片。
21、如权利要求15所述的半导体封装，还包括安装在基底的第二部分的第二表面上的多个焊料凸点。
22、如权利要求21所述的半导体封装，还包括半导体芯片和焊料凸点之间的多个电连接。
23、如权利要求15所述的半导体封装，还包括安装在基底的第二部分的第二表面上的多个焊料凸点，所述多个焊料凸点用于将所述封装附着到板，当所述封装被如此附着时，凸点将封装与板分隔开足够的量，使得第一部分的第二表面与安装在板上并且在第一部分的第二表面下的组件分开。
24、一种存储卡，包括：
第一基底，具有相对的第一表面和第二表面；
空腔，由第一基底的第二表面限定；
第一半导体芯片，安装在第一基底的表面之一上；
第二基底，具有相对的第三表面和第四表面；
第二半导体芯片，安装在第二基底的第三表面上，所述半导体芯片之一包括存储器，另一个包括控制器；
多个焊料凸点，形成在第一基底的第二表面和第二基底的第三表面之间，所述焊料凸点连接两个基底，第二半导体芯片至少部分容纳在空腔中。
25、一种电子***，包括：
第一基底，具有相对的第一表面和第二表面；
空腔，由第一基底的第二表面限定；
第一半导体芯片，安装在第一基底的表面之一上；
第二基底，具有相对的第三表面和第四表面；
第二半导体芯片，安装在第二基底的第三表面上，所述半导体芯片之一包括存储器，另一个包括处理器；
多个焊料凸点，形成在第一基底的第二表面和第二基底的第三表面之间，所述焊料凸点连接两个基底，第二半导体芯片至少部分容纳在空腔中；
输入/输出装置，将信息传输到所述***并从所述系传输信息。
26、一种制造半导体封装的方法，该方法包括以下步骤：
将基本上平坦的表面基底置于模具上方，所述模具具有基本平坦的第一表面和基本平坦的第二表面，所述第一表面与基底间隔第一距离，所述第二表面与第一表面相邻并与基底间隔第二距离；
将基底压到模具中，直到基底呈现模具表面的形状；
在基底的一侧上安装至少一个半导体芯片；
在基底的另一侧上安装焊料凸点。
27、如权利要求26所述的方法，还包括在焊料凸点和所述至少一个半导体芯片之间形成多个电连接。
28、如权利要求26所述的方法，还包括在基底的另一侧上安装至少一个附加半导体芯片。
29、如权利要求26所述的方法，其中，第一距离比第二距离大。
30、如权利要求26所述的方法，其中，第一距离比第二距离小。
31、如权利要求26所述的方法，其中，所述方法还包括使用焊料凸点来将基底安装到另一基底上。
32、如权利要求26所述的方法，其中，在基底的一侧上安装至少一个半导体芯片的步骤包括通过焊料凸点在所述一侧上安装所述至少一个半导体芯片。
33、如权利要求26所述的方法，其中，所述焊料凸点安装在基底的被模具表面之一成形的部分上。
34、如权利要求33所述的方法，其中，所述焊料凸点安装在基底的被模具的两个表面成形的部分上。
35、如权利要求34所述的方法，还包括在由第一模具表面成形的部分上使用一种尺寸的焊料凸点，并在由第二模具表面成形的部分上使用不同尺寸的焊料凸点。
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