CN105097759A - 封装堆栈结构及其制法暨无核心层式封装基板及其制法 - Google Patents

封装堆栈结构及其制法暨无核心层式封装基板及其制法 Download PDF

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CN105097759A
CN105097759A CN201410219093.7A CN201410219093A CN105097759A CN 105097759 A CN105097759 A CN 105097759A CN 201410219093 A CN201410219093 A CN 201410219093A CN 105097759 A CN105097759 A CN 105097759A
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insulating barrier
plate body
packaging
making
base plate
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林俊贤
邱士超
白裕呈
沈子杰
孙铭成
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种封装堆栈结构及其制法暨无核心层式封装基板及其制法，该制法先形成一绝缘层于一具有多个外接垫的导电板体上；形成线路层于该绝缘层上，且形成多个导电盲孔于该绝缘层中，以电性连接该线路层与该些外接垫；以及移除部分该导电板体，使该导电板体成为多个导电组件，所以可减少核心层的材料及制程，以降低制作成本。

Description

封装堆栈结构及其制法暨无核心层式封装基板及其制法
技术领域
本发明有关一种封装堆栈结构，尤指一种得提升产品可靠度的封装堆栈结构及其制法。
背景技术
随着半导体封装技术的演进，半导体装置(Semiconductordevice)已开发出不同的封装型态，而为提升电性功能及节省封装空间，遂堆加多个封装结构以形成封装堆栈结构(PackageonPackage，POP)，此种封装方式能发挥***封装(SiP)异质整合特性，可将不同功用的电子组件，例如：内存、中央处理器、绘图处理器、影像应用处理器等，藉由堆栈设计达到***的整合，适合应用于各种轻薄型电子产品。
图1A及图1B为现有封装堆栈结构1,1’的不同实施例的剖面示意图。
如图1A所示，该封装堆栈结构1包含第一封装基板11及第二封装基板12，该第一封装基板11具有多个线路层110，且该第二封装基板12具有核心层120与多个线路层121。第一半导体组件10以覆晶方式设于该第一封装基板11上，再藉由底胶14充填于该第一半导体组件10与第一封装基板11之间，且第二半导体组件15以打线方式结合于该第二封装基板12上，再藉由封装胶体16包覆该第二半导体组件15，并以多个焊球13叠设且电性连接该第一封装基板11与该第二封装基板12。
如图1B所示，该封装堆栈结构1’包含第一封装基板11及第二封装基板12，该第一封装基板11具有多个线路层110，且该第二封装基板12具有核心层120与多个线路层121。第一半导体组件10以覆晶方式设于该第一封装基板11上，再藉由底胶14充填于该第一半导体组件10与第一封装基板11之间，之后以多个焊球13叠设且电性连接该第一封装基板11与该第二封装基板12，再藉由封装胶体16’包覆该些焊球13与第一半导体组件10，后续将第二半导体组件15’以覆晶方式设于该第二封装基板12上。
然而，于现有封装堆栈结构1,1’中，其第二封装基板12皆具有核心层120，导致其制作成本高，且不易符合薄化的需求。
此外，由于第一封装基板11与第二封装基板12间以焊球13作为支撑与电性连接的组件，而随着电子产品的接点(即I/O)数量愈来愈多，在封装件的尺寸大小不变的情况下，各该焊球13间的间距需缩小，致使容易发生桥接(bridge)的现象而发生短路(short)问题，因而造成产品良率过低及可靠度不佳等问题。
又，因该焊球13于回焊后的体积及高度的公差大，即尺寸变异不易控制，致使不仅接点容易产生缺陷(例如，于回焊时，该焊球13会先变成软塌状态，同时于承受上方第二封装基板12的重量后，该焊球13容易塌扁变形，继而与邻近的焊球13桥接)，导致电性连接品质不良，且该焊球13所排列成的栅状数组(gridarray)容易产生共面性(coplanarity)不良，导致接点应力(stress)不平衡而容易造成该第一与第二封装基板11,12之间呈倾斜接置，甚至产生接点偏移的问题。
因此，如何克服现有技术中的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失，本发明的目的为提供一种封装堆栈结构及其制法暨无核心层式封装基板及其制法，可减少核心层的材料及制程，以降低制作成本。
本发明的无核心层式封装基板，包括：一绝缘层，其具有相对的第一表面与第二表面；多个外接垫，其嵌埋于该绝缘层中，且外露出该第一表面；多个导电组件，其接触该些外接垫并立设于该绝缘层的第一表面上，且形成该导电组件的材质为非焊锡材料；线路层，其设于该绝缘层的第二表面上；以及多个导电盲孔，其形成于该绝缘层中并电性连接该线路层与该些外接垫。
本发明还提供一种封装堆栈结构，包括：前述的无核心层式封装基板；以及至少一板体，其堆栈于该无核心层式封装基板的绝缘层的第一表面上，供该板体接置于该些导电组件上。
本发明还提供一种无核心层式封装基板的制法，包括：提供一形成有多个外接垫的导电板体；形成一绝缘层于该导电板体上，该绝缘层具有相对的第一表面与第二表面，且该绝缘层藉其第一表面结合至该导电板体上；形成线路层于该绝缘层的第二表面上，且形成多个导电盲孔于该绝缘层中，以令各该导电盲孔电性连接该线路层与该些外接垫；以及移除部分该导电板体，使该导电板体成为多个导电组件，且该些导电组件接触该些外接垫并立设于该绝缘层的第一表面上。
本发明另提供一种封装堆栈结构的制法，其接续前述的无核心层式封装基板的制程，再堆栈至少一板体于该无核心层式封装基板的绝缘层的第一表面上，且该板体接置于该些导电组件上。
前述的封装堆栈结构及其制法中，该导电板体为金属板材，且形成该导电组件的材质为非焊锡材料，例如金属柱。
前述的封装堆栈结构及其制法中，该绝缘层以压合方式形成于该导电板体上。
前述的封装堆栈结构及其制法中，该外接垫的表面齐平于该绝缘层的第一表面。
前述的封装堆栈结构及其制法中，该板体为具有核心层的线路板、或无核心层的线路板。
前述的封装堆栈结构及其制法中，该板体藉由多个支撑件接置于该些导电组件上。例如，形成该支撑件的材质为铜或焊锡材料，且以封装材包覆该些支撑件与该电子组件。因此，可于堆栈该板体于该无核心层式封装基板上后，形成封装材包覆该些支撑件与该电子组件。或先形成封装材于该板体上，且各该支撑件外露于该封装材，再将该无核心层式封装基板以其导电组件接置该些支撑件。
前述的封装堆栈结构及其制法中，该板体上设有至少一电子组件。
前述的封装堆栈结构及其制法中，还包括形成封装材于该无核心层式封装基板与该板体之间。
另外，前述的封装堆栈结构及其制法中，还包括设置至少一电子组件于该线路层上。
由上可知，本发明封装堆栈结构及其制法，藉由形成无核心层的线路结构于该导电板体上，再将该导电板体制作成导电组件，所以相较于现有技术，可减少核心层的材料及制程，以降低制作成本。
此外，本发明藉由该导电组件做为该封装基板与该板体的堆栈组件，以减少焊锡材的使用量，所以于回焊时能减少融接处，以避免发生桥接现象，以提升产品的良率，且能满足细间距(finepitch)的需求，而避免发生短路(short)的问题，进而提高产品良率。
附图说明
图1A及图1B为现有封装堆栈结构的不同实施例的剖视示意图；
图2A至图2H为本发明的无核心层式封装基板的制法的剖视示意图；以及
图3A至图3C为本发明封装堆栈结构的不同实施例的剖视示意图；其中，图3A为图3A’的其它实施例。
符号说明
1,1’,3,3’,3”,4封装堆栈结构
10第一半导体组件
11第一封装基板
110,121线路层
12第二封装基板
120,300核心层
13焊球
14底胶
15,15’第二半导体组件
16,16’封装胶体
2封装基板
20承载件
200基材
201离型层
202导电板体
202’导电组件
21外接垫
21a表面
22线路
23绝缘层
23a第一表面
23b第二表面
230穿孔
24导电层
25线路层
250导电盲孔
26绝缘保护层
27表面处理层
30,30’板体
31,31’支撑件
310铜柱
311焊锡材料
32,33电子组件
34封装材
340开口。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2H为本发明的无核心层式封装基板2的制法的剖视示意图。
如图2A所示，提供一承载件20，其具有一基材200、设于该基材200上的一离型层201、与设于该离型层201上的一导电板体202。
于本实施例中，该导电板体202为金属板材，例如铜。
如图2B所示，形成多个外接垫21与多个线路22于该导电板体202上。
如图2C所示，形成一绝缘层23于该导电板体202上。
于本实施例中，该绝缘层23具有相对的第一表面23a与第二表面23b，令该第一表面23a结合至该导电板体202上，且该第二表面23b上接合一如铜材的导电层(seedlayer)24。
此外，该绝缘层23的材质为预浸材(prepreg,PP)，所以该绝缘层23可以压合方式形成于该导电板体202上。
如图2D所示，以激光钻孔方式于对应各该外接垫21的位置上形成贯穿该绝缘层23与该导电层24的多个穿孔230。
如图2E所示，于该绝缘层23上利用该导电层24电镀制作一线路层25，且于该些穿孔230中形成导电材料以作为导电盲孔250，并藉由该些导电盲孔250电性连接该线路层25与该些外接垫21。
如图2F所示，形成一绝缘保护层26于该绝缘层23与该线路层25上，且该绝缘保护层26外露出该线路层25，供后续制程中接置其它外部组件。
于本实施例中，形成一表面处理层27于该线路层25的外露表面上。
如图2G所示，藉由该离型层201以移除该基材200。
如图2H所示，图案化蚀刻移除部分该导电板体202，使该导电板体202成为多个导电组件202’，以完成无核心层式封装基板2的制作，且该些导电组件202’接触该些外接垫21的表面21a，以令该些导电组件202’立设于该绝缘层23的第一表面23a上。
于本实施例中，该外接垫21的表面21a齐平于该绝缘层23的第一表面23a，且该线路22外露于该绝缘层23的第一表面23a。
此外，由于该导电板体202为非焊锡材料的板材，所以该导电组件202’的材质为非焊锡材料，例如，金属柱，较佳为铜柱。
又，该导电组件202’的形状为钝面锥柱体，即体积由底端朝顶端渐缩。
如图3A所示，于后续制程中，可将该无核心层式封装基板2以其导电组件202’堆栈于一板体30上，以形成一封装堆栈结构3。
于本实施例中，该板体30为具有核心层300的线路板；或者，该板体30’也可为无核心层(coreless)的线路板，如图3A’所示。
此外，该板体30,30’藉由多个支撑件31接置于该些导电组件202’上，且该支撑件31的材质为焊锡材料。于其它实施例中，如图3B所示，该支撑件31’由铜柱310与焊锡材料311构成。
又，可设置至少一电子组件32于该无核心层式封装基板2的线路层25上，且该板体30上也可选择性设置电子组件33。具体地，该电子组件32,33为主动组件或被动组件，该主动组件例如：芯片，而该被动组件例如：电阻、电容及电感。
另外，还可于堆栈制程后，形成封装材34于该无核心层式封装基板2与该板体30’之间，如图3A’及图3B所示，以包覆该些导电组件202’、支撑件31,31’与该电子组件33。于另一方式，如图3C所示，也可先形成封装材34于该板体30上，且形成多个开口340，使各该支撑件31对应外露于该些开口340，之后再将该无核心层式封装基板2以其导电组件202’接置于该些开口340中的支撑件31上。
本发明的制法藉由形成无核心层(coreless)的线路结构于该导电板体202上，再蚀刻该导电板体202以形成导电组件202’，所以相较于现有技术，可减少核心层的材料及制程，以降低制作成本。
此外，本发明藉由该导电组件202’做为电性连接，以减少焊锡材的使用量，所以于回焊时能减少融接处，以避免发生桥接现象，以提升产品的良率，且能满足细间距(finepitch)的需求，而避免发生短路(short)的问题，进而提高产品良率。
又，因该导电组件202’于回焊时的体积及高度的公差小，即尺寸变异容易控制，使接点不易产生缺陷，而有效提升电性连接品质，且该导电组件202’所排列成的栅状数组(gridarray)的共面性(coplanarity)良好，以易于控制产品高度，使该封装基板2与该板体30之间不会呈倾斜接置。
本发明还提供一种无核心层式封装基板2，包括：一绝缘层23、多个外接垫21、多个导电组件202’、一线路层25、以及多个导电盲孔250。
所述的绝缘层23具有相对的第一表面23a与第二表面23b。
所述的外接垫21嵌埋于该绝缘层23中，且外露出该第一表面23a，且该外接垫21的表面21a齐平于该绝缘层23的第一表面23a。
所述的导电组件202’接触该些外接垫21以立设于该绝缘层23的第一表面23a上，且该导电组件202’的材质为非焊锡材料，例如金属柱。
所述的线路层25设于该绝缘层23的第二表面23b上。
所述的导电盲孔250设于该绝缘层23中并电性连接该线路层25与该些外接垫21。
本发明还提供一种封装堆栈结构3,3’,3”,4，包括：该无核心层式封装基板2、以及藉由多个支撑件31,31’接置于该些导电组件202’上的一板体30,30’。
所述的板体30,30’堆栈于该无核心层式封装基板2的绝缘层23的第一表面23a上，且该板体30,30’为具有核心层300的线路板、或无核心层的线路板。
所述的支撑件31,31’的材质为铜或焊锡材料。
于一实施例中，该板体30,30’上设有至少一电子组件33。还包括封装材34，其包覆该些支撑件31,31’与该电子组件33。
于一实施例中，该封装堆栈结构3,4还包括设于该线路层25上的至少一电子组件32。
综上所述，本发明封装堆栈结构及其制法，藉由形成无核心层式封装基板，以减少核心层的材料及制程，而降低制作成本。
此外，藉由该导电组件的设计，以减少焊锡材的使用量，所以能满足细间距的需求，且能提高产品良率。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (30)

1.一种无核心层式封装基板，包括：
一绝缘层，其具有相对的第一表面与第二表面；
多个外接垫，其嵌埋于该绝缘层中，且外露出该第一表面；
多个导电组件，其接触该些外接垫并立设于该绝缘层的第一表面上，且形成该导电组件的材质为非焊锡材料；
线路层，其设于该绝缘层的第二表面上；以及
多个导电盲孔，其形成于该绝缘层中并电性连接该线路层与该些外接垫。
2.如权利要求1所述的封装基板，其特征在于，该导电组件为金属柱。
3.如权利要求1所述的封装基板，其特征在于，该外接垫的表面齐平于该绝缘层的第一表面。
4.一种封装堆栈结构，包括：
一无核心层式封装基板，包含：
一绝缘层，其具有相对的第一表面与第二表面；
多个外接垫，其嵌埋于该绝缘层中，且外露出该第一表面；
多个导电组件，其接触该些外接垫并立设于该绝缘层的第一表面上，且形成该导电组件的材质为非焊锡材料；
线路层，其设于该绝缘层的第二表面上；及
多个导电盲孔，其形成于该绝缘层中并电性连接该线路层与该些外接垫；以及
至少一板体，其堆栈于该无核心层式封装基板的绝缘层的第一表面上，且该板体接置于该些导电组件上。
5.如权利要求4所述的封装堆栈结构，其特征在于，该导电组件为金属柱。
6.如权利要求4所述的封装堆栈结构，其特征在于，该外接垫的表面齐平于该绝缘层的第一表面。
7.如权利要求4所述的封装堆栈结构，其特征在于，该板体为具有核心层的线路板、或无核心层的线路板。
8.如权利要求4所述的封装堆栈结构，其特征在于，该板体藉由多个支撑件接置于该些导电组件上。
9.如权利要求8所述的封装堆栈结构，其特征在于，形成该支撑件的材质为铜或焊锡材料。
10.如权利要求8所述的封装堆栈结构，其特征在于，该封装堆栈结构还包括封装材，其包覆该些支撑件与该电子组件。
11.如权利要求4所述的封装堆栈结构，其特征在于，该板体上设有至少一电子组件。
12.如权利要求4所述的封装堆栈结构，其特征在于，该封装堆栈结构还包括封装材，其形成于该无核心层式封装基板与该板体之间。
13.如权利要求4所述的封装堆栈结构，其特征在于，该封装堆栈结构还包括设于该线路层上的至少一电子组件。
14.一种无核心层式封装基板的制法，包括：
提供一形成有多个外接垫的导电板体；
形成一绝缘层于该导电板体上，该绝缘层具有相对的第一表面与第二表面，且该绝缘层藉其第一表面结合至该导电板体上；
形成线路层于该绝缘层的第二表面上，且形成多个导电盲孔于该绝缘层中，以令各该导电盲孔电性连接该线路层与该些外接垫；以及
移除部分该导电板体，使该导电板体成为多个导电组件，且该些导电组件接触该些外接垫并立设于该绝缘层的第一表面上。
15.如权利要求14所述的封装基板的制法，其特征在于，该导电板体为金属板材。
16.如权利要求14所述的封装基板的制法，其特征在于，形成该导电组件的材质为非焊锡材料。
17.如权利要求14所述的封装基板的制法，其特征在于，该绝缘层以压合方式形成于该导电板体上。
18.一种封装堆栈结构的制法，包括：
提供一具有多个导电组件的无核心层式封装基板；以及
堆栈至少一板体于该无核心层式封装基板上，且该板体接置于该些导电组件上。
19.如权利要求18所述的封装堆栈结构的制法，其特征在于，形成该导电组件的材质为非焊锡材料。
20.如权利要求18所述的封装堆栈结构的制法，其特征在于，该无核心层式封装基板的制程包括：
提供一形成有多个外接垫的导电板体；
形成一绝缘层于该导电板体上，该绝缘层具有相对的第一表面与第二表面，供该绝缘层藉其第一表面结合至该导电板体上；
形成线路层于该绝缘层的第二表面上，且形成多个导电盲孔于该绝缘层中，以令各该导电盲孔电性连接该线路层与该些外接垫；以及
移除部分该导电板体，使该导电板体成为多个导电组件，以完成无核心层式封装基板的制作，且该些导电组件接触该些外接垫并立设于该绝缘层的第一表面上。
21.如权利要求20所述的封装堆栈结构的制法，其特征在于，该导电板体为金属板材。
22.如权利要求20所述的封装堆栈结构的制法，其特征在于，该外接垫的表面齐平于该绝缘层的第一表面。
23.如权利要求20所述的封装堆栈结构的制法，其特征在于，该制法还包括设置至少一电子组件于该线路层上。
24.如权利要求18所述的封装堆栈结构的制法，其特征在于，该板体为具有核心层的线路板、或无核心层的线路板。
25.如权利要求18所述的封装堆栈结构的制法，其特征在于，该板体藉由多个支撑件接置于该些导电组件上。
26.如权利要求25所述的封装堆栈结构的制法，其特征在于，形成该支撑件的材质为铜或焊锡材料。
27.如权利要求25所述的封装堆栈结构的制法，其特征在于，该制法还包括于堆栈该板体于该无核心层式封装基板上后，形成封装材包覆该些支撑件与该电子组件。
28.如权利要求25所述的封装堆栈结构的制法，其特征在于，该制法还包括形成封装材于该板体上，且各该支撑件外露于该封装材，再将该无核心层式封装基板以其导电组件接置该些支撑件。
29.如权利要求18所述的封装堆栈结构的制法，其特征在于，该板体上设有至少一电子组件。
30.如权利要求18所述的封装堆栈结构的制法，其特征在于，该制法还包括形成封装材于该无核心层式封装基板与该板体之间。
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