CN101878521B - 向半导体衬底的硅中蚀刻沟道的方法、在半导体衬底的硅中形成沟道隔离的方法及形成多个二极管的方法 - Google Patents
向半导体衬底的硅中蚀刻沟道的方法、在半导体衬底的硅中形成沟道隔离的方法及形成多个二极管的方法 Download PDFInfo
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Abstract
本发明提供一种向半导体衬底的硅中蚀刻沟道的方法,其包括在半导体衬底的硅上方形成掩模,其中所述掩模包含穿过所述掩模而形成的沟道。使用所述掩模进行等离子体蚀刻以向所述半导体衬底的所述硅中形成沟道。在一个实施例中,所述等离子体蚀刻包括使用包括SF6、含氧化合物及含氮化合物的前驱气体来形成蚀刻等离子体。在一个实施例中,所述等离子体蚀刻包括包含含硫组分、含氧组分及NFx的蚀刻等离子体。
Description
技术领域
本文中所揭示的实施例关于向半导体衬底的硅中蚀刻沟道的方法,关于在半导体衬底的硅中形成沟道隔离的方法,且关于形成多个二极管的方法。
背景技术
在集成电路的制造中,将众多装置封装到半导体衬底的小区域中以产生集成电路。所述个别装置中的许多装置彼此电隔离。因此,电隔离是半导体装置设计的整体部分以用于防止在邻近组件及装置之间产生不需要的电耦合。
随着集成电路的尺寸减小,组成电路的装置被更紧密地放置在一起。隔离电路组件的常规方法包括沟道隔离。此沟道隔离是通过向半导体衬底中蚀刻沟道且用绝缘材料填充所述沟道而发生的。随着半导体衬底上的组件的密度已增加,沟道的宽度也已减小。此外,沟道的深度已趋于增加。其内形成有隔离沟道的一种类型的半导体衬底材料为晶体硅,且所述半导体衬底材料可包括其它材料,例如锗及/或导电性修改掺杂剂。仍需要开发出使得能够例如在沟道隔离的制造中向硅中蚀刻沟道的经改进的蚀刻化学物质。
附图说明
图1为在根据本发明的实施例的工艺中的半导体衬底的一部分的图解等距视图。
图2为图1的衬底的穿过图1中的线2-2获取的剖视图。
图3为图2的衬底的处于图2所示的处理后的处理下的视图。
图4为图3的衬底的处于图3所示的处理后的处理下的视图。
图5为图1的衬底的处于图4所示的处理后的处理下的视图。
图6为图5的衬底的穿过图5中的线5-5获取的剖视图。
图7为图5的衬底的穿过图5中的线7-7获取的剖视图。
图8为图5的衬底的处于图5所示的处理后的处理下的视图。
图9为图8的衬底的穿过图8中的线9-9获取的剖视图。
图10为图5的衬底的穿过图8中的线10-10获取的剖视图。
图11为图8的衬底的处于图8所示的处理后的处理下的视图。
图12为图11的衬底的穿过图11中的线12-12获取的剖视图。
图13为图11的衬底的穿过图11中的线13-13获取的剖视图。
图14为图11的衬底的处于图11所示的处理后的处理下的视图。
图15为图14的衬底的穿过图14中的线15-15获取的剖视图。
图16为图14的衬底的穿过图14中的线16-16获取的剖视图。
图17为图14的衬底的处于图14所示的处理后的处理下的视图。
图18为图17的衬底的穿过图17中的线18-18获取的剖视图。
图19为图17的衬底的穿过图17中的线19-19获取的剖视图。
图20为图19的衬底的处于图19所示的处理后的处理下的视图。
图21为图17的衬底的处于图20所示的处理后的处理下的视图。
图22为图21的衬底的穿过图21中的线22-22获取的剖视图。
图23为图21的衬底的穿过图21中的线23-23获取的剖视图。
图24为图21的衬底的处于图21所示的处理后的处理下的视图。
图25为图25的衬底的穿过图24中的线25-25获取的剖视图。
图26为图25的衬底的穿过图24中的线26-26获取的剖视图。
具体实施方式
本发明的实施例包括向半导体衬底的硅中蚀刻沟道的方法,且还包括在半导体衬底的硅中形成沟道隔离的方法。此外,本发明的实施例还包括形成多个二极管的方法。
最初参看图1及图2,半导体衬底大体上用参考标号10指示。在本文献的上下文中,术语“半导体衬底”或“半导电衬底”经定义为意指包含半导电材料的任何构造,其包括(但不限于)例如半导电晶片等块状半导电材料(其是单独的或在其上包含其它材料的组合中)及半导电材料层(其是单独的或在包含其它材料的组合中)。术语“衬底”指代任何支撑结构,其包括(但不限于)上文所述的半导电衬底。衬底10经描绘为包含块状半导体衬底,例如包含单晶硅12,但可使用其它含硅衬底(例如绝缘体上半导体)及其它衬底。材料12可包括其它材料,例如锗及/或导电性修改掺杂剂。在一个实施例中,块状硅材料12包含经掺杂到任何适合的p级掺杂的p型块状区14。其上方依序描绘经n型掺杂的n+区16、n型n-掺杂区18及p型p+掺杂区20。当然还预期替代的含硅衬底。
一系列掩蔽层接纳于硅材料20上方。这些层包括衬垫氧化物层22、氮化硅或多晶硅层24、硬掩蔽层26、抗反射涂层28及经图案化的光致抗蚀剂层30。这些层中的任何层是任选的,且可包含多种互不相同的材料及/或层。所述材料可为或可不为最终牺牲的。在某些实施例中,硬掩模层26可为以下性质中的任一者:绝缘的、半导电的或导电的。用于硬掩模层26的实例绝缘材料包括经掺杂或未经掺杂的二氧化硅,以及氮化硅。用于硬掩模层26的实例导电材料包括难熔金属氮化物(即TiN、WN等)、难熔金属硅化物(WSix、TiSx等)或呈元素形式的任何金属(Ti、W等)中的任一者或其组合。光致抗蚀剂30经描绘为已被图案化以形成到达抗反射涂层28的沟道32。
参看图3,光致抗蚀剂30(未图示)及抗反射涂层28(未图示)已用作用以蚀刻穿过硬掩模层26的掩模,其中光致抗蚀剂层30及抗反射涂层28由所述蚀刻及/或随后被至少部分地移除。用于进行所述蚀刻的实例各向异性干式蚀刻化学物质针对光致抗蚀剂包括SO2+O2或O2+HBr或O2+N2,且针对抗反射涂层通常包括一种或一种以上碳氟化合物(例如,CF4)+HBr+He。
参看图4,经图案化的硬掩模层26已用作用于蚀刻穿过层24及22的掩模,进而使沟道32最终延伸到硅12。用于蚀刻穿过氮化硅层24的实例蚀刻化学物质包括一种或一种以上碳氟化合物+SF6+NF3,而用于在所述蚀刻后清除衬垫氧化物22的实例蚀刻化学物质包括一种或一种以上碳氟化合物(例如,CF4、CHF3、CH2F2等)。图4进而描绘(仅在一个实例实施例中)在半导体衬底的硅上方形成掩模35,其中掩模35包含穿过所述掩模35而形成的沟道32。所述掩模可包括或可不包括硬掩模层,且仅在一个实例中可被视为第一掩模,所述第一掩模包含穿过所述第一掩模而形成的第一沟道32,所述第一沟道32在衬底10上方在第一主要方向上延伸。在图4的描绘中的所述实例第一主要方向将垂直进入及离开图4所在页面的平面。当然,第一沟道32在此方向上可并不完全笔直且可(仅借助于实例)相对于彼此蜿蜒,尽管如此,在一个实施例中,第一沟道32如刚才所描述在衬底上方在第一主要方向上延伸。
参看图5、图6及图7,已通过使用掩模35来向衬底10的硅12中等离子体蚀刻而使沟道32相对于衬底10延伸。在一个实施例中,所述等离子体蚀刻包含使用包含SF6、含氧化合物及含氮化合物的前驱气体来形成蚀刻等离子体。含氧化合物及含氮化合物可包含不同化合物且/或可包含相同化合物。举例来说,在一个实施例中,含氧化合物包含O2且含氮化合物包含N2。相同化合物所包含的实例含氧化合物及含氮化合物包括NOx,其中“x”在例如约1到3的范围内。
此外,当然,前驱气体可包含两种含氧化合物,例如,其中含氧化合物中的一者不含氮且含氧化合物中的另一者包含氮。举例来说,仅在一个实施例中,前驱气体可包含SF6、N2、O2及NOx。或者,在所述实例中,使得发生等离子体蚀刻的前驱气体可不包括N2。此外,在一个实施例中,前驱气体可包含SF6、O2及N2,基本上由SF6、O2及N2组成,或由SF6、O2及N2组成。当然,还可使用额外的前驱气体,例如HBr。在一个实施例中,在使用SF6、O2及N2这三种气体的情况下,使得进行等离子体蚀刻的前驱气体可包含比SF6及O2中的每一者多的N2。在一个实施例中,在蚀刻期间使用的掩模在向硅中等离子体蚀刻的至少较后部分期间包含最外硬掩模层,且在一个实施例中,所述外部掩模层不含碳,因为所陈述的等离子体蚀刻化学物质可能会蚀刻包含碳的最外硬掩模层。
已使用LAM喜世(LAM Kiyo)等离子体蚀刻腔室将本发明付诸实践。无论如何且仅借助于实例,在蚀刻期间的实例压力可为约1毫托到约50毫托,且上面搁置衬底的基座的实例温度范围为约0℃到约50℃。实例电源功率范围为约100W到约1,000W,且实例偏压为约-20V到约-1,000V。在例如SF6、O2、N2及HBr为前驱气体的情况下,实例流动速率包括:对于SF6,约1sccm到约100sccm;对于O2,约10sccm到约500sccm;对于HBr,0sccm到约500sccm及对于N2,约1sccm到约500sccm。在LAM喜世(LAM Kiyo)等离子体蚀刻腔室中的特定付诸实践的实例包括:5毫托、7℃、-500V偏压、400W电源功率、350sccm的SF6、45sccm的O2、60sccm的N2及20sccm的HBr。所使用的特定等离子体蚀刻器可能能够操作以使得偏压或偏置功率可为设定点,同时允许另一者浮动。在一个实施例中,设定偏压,且允许偏置功率浮动。在另一实施例中,设定偏置功率,且允许偏压浮动。
已确定,使用SF6及O2而不使用任何含氮化合物的蚀刻可导致显著的沟道侧壁侵蚀、不规则沟道侧壁及/或V形沟道底部。然而,已发现,通过将含氮化合物添加到等离子体蚀刻化学物质,产生较平滑且/或较笔直的沟道侧壁且具有较平坦的沟道底部,但除非字面上如此主张,否则本发明不必要求实现所述结果中的任一者。此外且在不必受本发明的任何理论限制的情况下,在等离子体中存在氮可产生NFx物质,此物质可有助于或可并不有助于形成较笔直的侧壁及较平坦的底部。
无论如何,本发明的一个实施例包括使用掩模来向半导体衬底的硅中等离子体蚀刻沟道,所述掩模具有穿过所述掩模而形成的沟道,其中所述等离子体蚀刻包含包括含硫组分、含氧组分及NFx的蚀刻等离子体。在一个实施例中,含硫组分由包含SF6的前驱气体形成。在一个实施例中,含氧组分的氧可由包含O2的前驱气体形成,且NFx的氮可由不含氧的前驱气体化合物形成。此外,在一个实施例中,含氧组分的氧及NFx的氮可由包含NOx的前驱气体形成。此外,实例前驱气体包括上文所述的前驱气体中的任一者,包括其任何组合。
沟道32在硅12内的实例蚀刻深度为约7,500埃到约20,000埃,其中9,000埃仅为一个特定实例。
参看图8、图9及图10,掩蔽层40已形成于衬底10上方且因此形成于衬底的硅内的第一沟道32上方。在一个实施例中,掩蔽层40包含多层抗蚀剂,其中三个此类实例层被依序展示为包含第一层42、在第一层42上方的层44及另一层45。在一个实例中,层42呈液态树脂的形式,所述液态树脂沉积以完全填充第一沟道32并被接纳于第一掩模35的硬掩模层26上方且其后经固化。实例层44为任何含硅硬掩模,其上方为包含感光材料(例如光致抗蚀剂)的实例层45。
参看图11、图12及图13,感光层45已经图案化以形成第二沟道50,所述第二沟道50在衬底10上方在与第一主要方向正交的第二主要方向上延伸。图13中的实例第二主要方向将垂直进入及离开图13所在页面的平面,且在图11中的箭头13所指的方向上。此外,如上文所述的所述第一主要方向将在图11中的箭头12所指的方向上。当然,第二沟道50在此第二主要方向上可并不完全笔直且可(仅借助于实例)相对于彼此而蜿蜒,尽管如此,在一个实施例中,第二沟道50如刚才所描述在衬底上方在第二主要方向上延伸。
参看图14、图15及图16,经图案化的感光材料45(未图示)已用作用以蚀刻含硅硬掩模层44、树脂42及第一掩模35的硬掩模层26的掩模,以使第二沟道50穿过硬掩模层26而延伸到氮化硅层24,其中感光材料45在所述蚀刻期间及/或随后被移除。
参看图17、图18及图19,已进行蚀刻以使沟道50穿过氮化硅层24及衬垫氧化物层22而延伸到硅材料12。因此,且仅在一个实施例中,第二沟道50延伸穿过第一掩模35的硬掩模层26,且第二掩模55形成于第一沟道上方且包含第一掩模的硬掩模层26。
参看图20,已通过使用第二掩模55对硅12进行等离子体蚀刻而使第二沟道50延伸到硅12中。材料42的一些材料(图20中未展示或不可见)可保留而免受图14、图15及图16所描绘的处理(未图示),或将另一材料提供于第一沟道32的底部(图20中未展示或不可见),以防止在蚀刻第二沟道50的同时将所述第一沟道的若干部分蚀刻得较深。在一个实施例中,向硅中等离子体蚀刻第二沟道包含使用包含SF6、含氧化合物及含氮化合物的前驱气体来形成蚀刻等离子体。可使用上文所描述的处理中的任一者。此外,用以在硅内形成第二沟道的等离子体蚀刻可与用以在硅材料内形成第一沟道的等离子体蚀刻相同或不同。此外且无论如何,用以形成第二沟道的等离子体蚀刻可包含包括含硫组分、含氧组分及NFx的蚀刻等离子体,例如也如上所述。无论如何且仅借助于实例,沟道50在硅材料12内的实例深度为约2,500埃到约3,500埃,其中约3,000埃为 特定实例。
所述材料22、24、26、42及44中的一些或全部材料最终可被或可不被从衬底移除。仅借助于实例,图21、图22及图23描绘所有所述材料已被移除,且无论如何,对第二沟道的等离子体蚀刻导致形成间隔的含硅台面65。
本发明的实施例包括在半导体衬底的硅内形成沟道隔离的方法,且可包含或可不包含间隔的含硅台面的形成。举例来说且仅借助于实例,上文所述的在图5到图7之后的处理或其它处理可包括将绝缘的沟道隔离材料沉积到所述沟道内而不必形成上述实例第二沟道。此外且不管形成台面,可将绝缘的沟道隔离材料沉积到形成于硅内的第一及第二沟道内。
无论如何,本发明的实施例还包含结合形成间隔的含硅台面而形成多个二极管的方法。举例来说且仅借助于实例,图24、图25及图26描绘后续处理,借此已沉积绝缘材料66以使其接纳于间隔的含硅台面65周围且将导电硅化物层68形成于台面65上方。实例绝缘材料66包括氮化硅及二氧化硅中的一者或其组合,且特定实例导电硅化物材料68包括硅化钴。当然,可使用替代及/或额外的材料。仅借助于实例,可通过以下方式来制造图24到26的构造:沉积材料66以过量填充沟道,将其平面化且图案化以暴露含硅台面,继而将台面的暴露的硅材料予以后续硅化金属沉积。
无论如何,图24到26描绘在间隔的含硅台面65中的个别台面上形成个别实例二极管75。在一个实施例中,个别二极管包含p型含硅区(即,区20)及n型含硅区(即,区16、18)。在一个实施例中,个别二极管包含含硅区(即,区20)及金属区(即,区68)。仅借助于实例,二极管可用于可编程导电随机存取存储器(PCRAM)应用中。
Claims (26)
1.一种在半导体衬底的硅中形成沟道隔离的方法,其包含:
在半导体衬底的硅上方形成第一掩模,所述第一掩模包含穿过所述第一掩模而形成的在所述衬底上方在第一主要方向上延伸的第一沟道,所述第一掩模包含硬掩模层;
使用所述第一掩模来向所述半导体衬底的所述硅中等离子体蚀刻第一沟道,所述向所述硅中等离子体蚀刻所述第一沟道包含使用包含SF6、含氧组分及含氮组分的前驱气体来形成蚀刻等离子体;
在所述第一沟道上方形成第二掩模,所述第二掩模包含穿过所述第二掩模而形成的在所述衬底上方在与所述第一主要方向正交的第二主要方向上延伸的第二沟道,所述第二掩模包含所述第一掩模的所述硬掩模层并且不越过所述第一沟道;
使用所述第二掩模来向所述半导体衬底的所述硅中等离子体蚀刻第二沟道,所述向所述硅中等离子体蚀刻所述第二沟道包含使用包含SF6、含氧组分及含氮组分的前驱气体来形成蚀刻等离子体;及
在等离子体蚀刻所述第二沟道之后,将绝缘的沟道隔离材料沉积到所述硅中的所述第一及第二沟道内。
2.根据权利要求1所述的方法,其中所述第二掩模是由接纳于所述第一掩模的所述硬掩模层上方的多层抗蚀剂形成的。
3.根据权利要求1所述的方法,其中所述第一掩模的所述硬掩模层为绝缘的。
4.根据权利要求1所述的方法,其中所述第一掩模的所述硬掩模层为导电的。
5.根据权利要求4所述的方法,其中所述第一掩模的所述导电硬掩模层包含难熔金属氮化物、难熔金属硅化物或呈元素形式的金属中的至少一者。
6.根据权利要求1所述的方法,其包含等离子蚀刻所述第二沟道以使其与所述第一沟道相比较浅地进入所述硅。
7.一种形成多个二极管的方法,其包含:
在半导体衬底的硅上方形成第一掩模,所述第一掩模包含穿过所述第一掩模而形成的在所述衬底上方在第一主要方向上延伸的第一沟道,所述第一掩模包含硬掩模层;
使用所述第一掩模来向所述半导体衬底的所述硅中等离子体蚀刻第一沟道,所述向所述硅中等离子体蚀刻所述第一沟道包含使用包含SF6、含氧组分及含氮组分的前驱气体来形成蚀刻等离子体;
在所述第一沟道上方形成第二掩模,所述第二掩模包含穿过所述第二掩模而形成的在所述衬底上方在与所述第一主要方向正交的第二主要方向上延伸的第二沟道,所述第二掩模包含所述第一掩模的所述硬掩模层,所述第二沟道延伸穿过所述第一掩模的所述硬掩模层并且不越过所述第一沟道;
使用所述第二掩模来向所述半导体衬底的所述硅中等离子体蚀刻第二沟道,所述向所述硅中等离子体蚀刻所述第二沟道包含使用包含SF6、含氧组分及含氮组分的前驱气体来形成蚀刻等离子体,所述向所述硅中等离子体蚀刻所述第二沟道形成间隔的含硅台面;及
在所述台面中的个别台面上提供个别二极管,且沉积绝缘材料以使其被接纳于所述间隔的含硅台面周围。
8.根据权利要求7所述的方法,其中所述个别二极管包含p型含硅区及n型含硅区。
9.根据权利要求7所述的方法,其中所述含氧组分和所述含氮组分在所述第一和第二沟道的所述等离子蚀刻的每一个中包含不同组分。
10.根据权利要求7所述的方法,其中所述含氧组分和所述含氮组分在所述第一和第二沟道的所述等离子蚀刻的每一个中包含相同组分。
11.根据权利要求10所述的方法,其中所述相同组分包含NOx。
12.根据权利要求7所述的方法,其中所述前驱气体在所述第一和第二沟道的所述等离子蚀刻的每一个中包含HBr。
13.一种在半导体衬底的硅中形成沟道隔离的方法,其包含:
在半导体衬底的硅上方形成第一掩模,所述第一掩模包含穿过所述第一掩模而形成的在所述衬底上方在第一主要方向上延伸的第一沟道,所述第一掩模包含硬掩模层;
使用所述第一掩模来向所述半导体衬底的所述硅中等离子体蚀刻第一沟道,所述向所述硅中等离子体蚀刻所述第一沟道包含使用包含SF6、含氧组分及含氮组分的前驱气体来形成蚀刻等离子体;
在所述第一沟道上方形成第二掩模,所述第二掩模包含穿过所述第二掩模而形成的在所述衬底上方在与所述第一主要方向正交的第二主要方向上延伸的第二沟道,所述第二掩模包含所述第一掩模的所述硬掩模层;
使用所述第二掩模来向所述半导体衬底的所述硅中等离子体蚀刻第二沟道,所述向所述硅中等离子体蚀刻所述第二沟道包含使用包含SF6、含氧组分及含氮组分的前驱气体来形成蚀刻等离子体;
在等离子体蚀刻所述第二沟道之后,将绝缘的沟道隔离材料沉积到所述硅中的所述第一及第二沟道内;及
所述形成所述第二掩膜包含用牺牲材料填充所述第一沟道,并且在所述沉积之前移除所述牺牲材料。
14.根据权利要求13所述的方法,其包含用所述牺牲材料过量填充所述第一沟道。
15.一种在半导体衬底的硅中形成沟道隔离的方法,其包含:
在半导体衬底的硅上方形成第一掩模,所述第一掩模包含穿过所述第一掩模而形成的在所述衬底上方在第一主要方向上延伸的第一沟道,所述第一掩模包含硬掩模层;
使用所述第一掩模来向所述半导体衬底的所述硅中等离子体蚀刻第一沟道,所述向所述硅中等离子体蚀刻所述第一沟道包含使用包含SF6、含氧组分及含氮组分的前驱气体来形成蚀刻等离子体;
在所述第一沟道上方形成第二掩模,所述第二掩模包含穿过所述第二掩模而形成的在所述衬底上方在与所述第一主要方向正交的第二主要方向上延伸的第二沟道,所述第二掩模包含所述第一掩模的所述硬掩模层,所述形成所述第二掩膜包含将液体沉积到所述第一沟道内;
使用所述第二掩模来向所述半导体衬底的所述硅中等离子体蚀刻第二沟道,所述向所述硅中等离子体蚀刻所述第二沟道包含使用包含SF6、含氧组分及含氮组分的前驱气体来形成蚀刻等离子体;及
在等离子体蚀刻所述第二沟道之后,将绝缘的沟道隔离材料沉积到所述硅中的所述第一及第二沟道内。
16.根据权利要求15所述的方法,其中所述液体被沉积以填充所述第一沟道。
17.根据权利要求16所述的方法,其中所述液体被沉积以过量填充所述第一沟道。
18.根据权利要求15所述的方法,其包含:
将所述液体固化为固体;以及
在将绝缘的沟道隔离材料沉积到所述硅中的所述第一及第二沟道内之前移除所述固体。
19.一种在半导体衬底的硅中形成沟道隔离的方法,其包含:
在半导体衬底的硅上方形成第一掩模,所述第一掩模包含穿过所述第一掩模而形成的在所述衬底上方在第一主要方向上延伸的第一沟道,所述第一掩模包含硬掩模层;
使用所述第一掩模来向所述半导体衬底的所述硅中等离子体蚀刻第一沟道,所述向所述硅中等离子体蚀刻所述第一沟道包含蚀刻等离子体,所述蚀刻等离子体包含含氟组分、含氧组分和NFx;
在所述第一沟道上方形成第二掩模,所述第二掩模包含穿过所述第二掩模而形成的在所述衬底上方在与所述第一主要方向正交的第二主要方向上延伸的第二沟道,所述第二掩模包含所述第一掩模的所述硬掩模层并且不越过所述第一沟道;
使用所述第二掩模来向所述半导体衬底的所述硅中等离子体蚀刻第二沟道,所述向所述硅中等离子体蚀刻所述第二沟道包含蚀刻等离子体,所述蚀刻等离子体包含含氟组分、含氧组分和NFx;及
在等离子体蚀刻所述第二沟道之后,将绝缘的沟道隔离材料沉积到所述硅中的所述第一及第二沟道内。
20.根据权利要求20所述的方法,其包含等离子蚀刻所述第二沟道以使其与所述第一沟道相比较浅地进入所述硅。
21.一种在半导体衬底的硅中形成沟道隔离的方法,其包含:
在半导体衬底的硅上方形成第一掩模,所述第一掩模包含穿过所述第一掩模而形成的在所述衬底上方在第一主要方向上延伸的第一沟道,所述第一掩模包含硬掩模层;
使用所述第一掩模来向所述半导体衬底的所述硅中等离子体蚀刻第一沟道,所述向所述硅中等离子体蚀刻所述第一沟道包含蚀刻等离子体,所述蚀刻等离子体包含含氟组分、含氧组分和NFx;
在所述第一沟道上方形成第二掩模,所述第二掩模包含穿过所述第二掩模而形成的在所述衬底上方在与所述第一主要方向正交的第二主要方向上延伸的第二沟道,所述第二掩模包含所述第一掩模的所述硬掩模层;
使用所述第二掩模来向所述半导体衬底的所述硅中等离子体蚀刻第二沟道,所述向所述硅中等离子体蚀刻所述第二沟道包含蚀刻等离子体,所述蚀刻等离子体包含含氟组分、含氧组分和NFx;
在等离子体蚀刻所述第二沟道之后,将绝缘的沟道隔离材料沉积到所述硅中的所述第一及第二沟道内;及
所述形成所述第二掩膜包含用牺牲材料填充所述第一沟道,并且在所述沉积之前移除所述牺牲材料。
22.根据权利要求21所述的方法,其包含用所述牺牲材料过量填充所述第一沟道。
23.一种在半导体衬底的硅中形成沟道隔离的方法,其包含:
在半导体衬底的硅上方形成第一掩模,所述第一掩模包含穿过所述第一掩模而形成的在所述衬底上方在第一主要方向上延伸的第一沟道,所述第一掩模包含硬掩模层;
使用所述第一掩模来向所述半导体衬底的所述硅中等离子体蚀刻第一沟道,所述向所述硅中等离子体蚀刻所述第一沟道包含蚀刻等离子体,所述蚀刻等离子体包含含氟组分、含氧组分和NFx;
在所述第一沟道上方形成第二掩模,所述第二掩模包含穿过所述第二掩模而形成的在所述衬底上方在与所述第一主要方向正交的第二主要方向上延伸的第二沟道,所述第二掩模包含所述第一掩模的所述硬掩模层,所述形成所述第二掩膜包含将液体沉积到所述第一沟道内;
使用所述第二掩模来向所述半导体衬底的所述硅中等离子体蚀刻第二沟道,所述向所述硅中等离子体蚀刻所述第二沟道包含蚀刻等离子体,所述蚀刻等离子体包含含氟组分、含氧组分和NFx;及
在等离子体蚀刻所述第二沟道之后,将绝缘的沟道隔离材料沉积到所述硅中的所述第一及第二沟道内。
24.根据权利要求23所述的方法,其中所述液体被沉积以填充所述第一沟道。
25.根据权利要求24所述的方法,其中所述液体被沉积以过量填充所述第一沟道。
26.根据权利要求23所述的方法,其包含:
将所述液体固化为固体;以及
在将绝缘的沟道隔离材料沉积到所述硅中的所述第一及第二沟道内之前移除所述固体。
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US9524875B2 (en) | 2016-12-20 |
CN101878521A (zh) | 2010-11-03 |
KR101148641B1 (ko) | 2012-05-21 |
SG186613A1 (en) | 2013-01-30 |
TW200937519A (en) | 2009-09-01 |
TWI379355B (en) | 2012-12-11 |
WO2009073308A1 (en) | 2009-06-11 |
EP2218095A4 (en) | 2012-02-22 |
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