CN113725277A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN113725277A
CN113725277A CN202110377536.5A CN202110377536A CN113725277A CN 113725277 A CN113725277 A CN 113725277A CN 202110377536 A CN202110377536 A CN 202110377536A CN 113725277 A CN113725277 A CN 113725277A
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layer
region
epitaxial
source
drain
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陈仕承
江国诚
林志昌
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的半导体装置包括有源区、多个通道部件的垂直堆叠、栅极结构、底部介电结构、源极/漏极结构和锗层，有源区包括通道区以及与通道区相邻的源极/漏极区。多个通道部件的垂直堆叠位于通道区上。栅极结构位于通道部件的垂直堆叠周围与之上。底部介电结构位于源极/漏极区上。源极/漏极结构位于底部介电结构上。锗层位于底部介电结构与源极/漏极区之间。

Description

半导体装置
技术领域
本发明实施例涉及半导体装置，更特别涉及形成半导体氧化物结构于源极/漏极结构之下的方法，以得拟绝缘层上硅结构。
背景技术
半导体集成电路产业已经历指数成长。集成电路材料与设计的技术进展使每一代的集成电路比前一代具有更小且更复杂的电路。在集成电路演进中，功能密度(比如单位芯片面积的内连线装置数目)通常随着几何尺寸(比如采用的制作工艺所能产生的最小构件或线路)缩小而增加。尺寸缩小通常有利于增加产能并降低相关成本。尺寸缩小亦增加处理与制造集成电路的复杂度。
举例来说，随着集成电路技术朝更小的技术节点进展，已导入多栅极装置以增加栅极-通道耦合、降低关闭状态电流、并减少短通道效应而改善栅极控制。多栅极装置通常指的是具有栅极结构或其部分于通道区的多侧上的装置。鳍状场效晶体管与全绕式栅极晶体管(易可视作非平面晶体管)为多栅极装置的例子，其为高效能与低漏电流应用的泛用有力候补。鳍状场效晶体管具有***的通道，而栅极包覆通道的多侧(比如栅极包覆自基板延伸的半导体材料鳍状物的顶部与侧壁)。与平面晶体管相较，此设置可较佳地控制通道并大幅减少短通道效应(具体为减少次临界漏电流，比如减少关闭状态中的鳍状场效晶体管的源极与漏极之间的耦合)。全绕式栅极晶体管的栅极结构可部分或完全延伸于通道区周围，以接触通道区的多侧。全绕式栅极晶体管的通道区可由纳米线、纳米片、其他纳米结构、及/或其他合适结构所形成。在一些实施方式中，这些通道区包括垂直堆叠的多个纳米结构(其水平延伸以提供水平方向的通道)。此全绕式栅极晶体管可视作垂直堆叠的水平全绕式栅极晶体管。
闩锁为互补式金氧半集成电路的失效机制，其特征在于多余的漏极电流与装置失效或装置损坏。多栅极装置无法避免闩锁。闩锁通常来自于寄生的PNP与NPN双极晶体管其基体基板中的井区与有源掺杂区的配置。制作于绝缘层上硅基板之上的互补式金氧半装置通常可避免闩锁，因为埋置氧化硅隔离层的存在实质上隔离n型井与p型井。避免闩锁的装置如保护环与分接单元常见于电路设计中。分接单元置于标准单元之间，并与标准单元隔有一或多个隔离结构。分接单元与隔离结构会增加集成电路的总体积。在集成电路晶面的固定面积中，分接单元与隔离结构会取代功能装置所用的实际空间。虽然分接单元所用的现有结构适用于其预期目的，但无法符合所有方面的需求。
发明内容
本发明一实施例关于半导体装置。半导体装置包括有源区，包括通道区以及与通道区相邻的源极/漏极区；多个通道部件的垂直堆叠，位于通道区上；栅极结构，位于通道部件的垂直堆叠周围与之上；底部介电结构，位于源极/漏极区上；源极/漏极结构，位于底部介电结构上；以及锗层，位于底部介电结构与源极/漏极区之间。
本发明另一实施例关于半导体装置。半导体装置包括：基板，具有第一区与第二区；第一晶体管，位于第一区中；以及第二晶体管，位于第二区中。第一晶体管包括第一有源区，含有第一通道区以及与第一通道区相邻的第一源极/漏极区，通道部件的第一垂直堆叠，位于第一通道区上，第一栅极结构，位于通道部件的第一垂直堆叠周围与之上，第一底部介电结构，位于第一源极/漏极区上，第一源极/漏极结构，位于第一底部介电结构上，以及第一锗层，位于第一底部介电结构与第一源极/漏极区之间。第二晶体管包含第二有源区，含有第二通道区以及与第二通道区相邻的第二源极/漏极区，通道部件的第二垂直堆叠，位于第二通道区上，第二栅极结构，位于通道部件的第二垂直堆叠周围与之上，第二底部介电结构，位于第二源极/漏极区上，第二源极/漏极结构，位于第二底部介电结构上，以及第二锗层，位于第二底部介电结构与第二源极/漏极区之间。第一底部介电结构具有第一深度，第二底部介电结构具有第二深度，且第二深度小于第一深度。
本发明又一实施例关于半导体装置的形成方法。方法包括形成含有交错的多个半导体层与多个牺牲层的堆叠于基板上；自堆叠形成鳍状结构；形成虚置栅极堆叠于鳍状结构上；沉积栅极间隔物层于虚置栅极堆叠上；形成源极/漏极凹陷以与虚置栅极堆叠相邻；选择性地部分蚀刻多个牺牲层，以形成多个内侧间隔物凹陷；形成多个内侧间隔物结构于内侧间隔物凹陷中；形成介电层于基板上；移除源极/漏极凹陷中的介电层的一部分，以露出基板的顶面表面；形成底部介电结构于顶面表面上的源极/漏极凹陷中；以及形成外延结构于底部介电结构上。
附图说明
图1是本发明一或多个实施例中，形成半导体装置的方法的流程图。
图2至图19是本发明一或多个实施例中，工件依据图1的方法的制作工艺时的部分剖视图。
附图标记说明如下：
D1:第一深度
D2:第二深度
10:通道区
20:源极/漏极区
100:方法
102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138:步骤
200:工件
202:基板
203:抗击穿注入区
204:外延堆叠
205:鳍状结构
205A:第一鳍状结构
205B:第二鳍状结构
206,208:外延层
210:虚置栅极堆叠
212:虚置栅极介电层
214:虚置栅极层
216:硬遮罩
218:氧化物层
220:氮化物层
222:栅极间隔物层
222-1:第一栅极间隔物层
222-2:第二栅极间隔物层
222-3:第三栅极间隔物层
224:内侧间隔物结构
224-1:第一内侧间隔物层
224-2:第二内侧间隔物层
228:源极/漏极沟槽
230:第一阻挡层
232:成长表面
234:第一外延结构
235:第二外延结构
236:第一底抗反射涂层
238:第二阻挡层
240:第二底抗反射涂层
242:第一源极/漏极结构
244:第三阻挡层
246:第三底抗反射涂层
248:第二源极/漏极结构
250:接点蚀刻停止层
252:层间介电层
254:栅极结构
300:第一晶体管
400:第二晶体管
1000:第一区
2000:第二区
2340:第一半导体氧化物结构2342:锗结构
2345:第一底部介电结构
2350:第二半导体氧化物结构
2355:第二底部介电结构
具体实施方式
述详细描述可搭配附图说明，以利理解本发明的各方面。值得注意的是，各种结构仅用于说明目的而未按比例绘制，如本业常态。实际上为了清楚说明，可任意增加或减少各种结构的尺寸。
下述内容提供的不同实施例或例子可实施本发明实施例的不同结构。特定构件与排列的实施例用以简化本揭露而非局限本发明。举例来说，形成第一构件于第二构件上的叙述包含两者直接接触，或两者之间隔有其他额外构件而非直接接触。此外，本发明的多种实例可重复采用相同标号以求简洁，但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。
此外，本发明实施例的结构形成于另一结构上、连接至另一结构、及/或耦接至另一结构中，结构可直接接触另一结构，或可形成额外结构于结构及另一结构之间(即结构未接触另一结构)。此外，空间性的相对用语如“下方”、“其下”、“下侧”、“上方”、“上侧”、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。此外，当数值或数值范围的描述有“约”、“近似”、或类似用语时，除非特别说明否则其包含所述数值的+/-10％。举例来说，用语“约5nm”包含的尺寸范围为4.5nm至5.5nm。
在电路设计中，标准单元为依据设计布局中的一组设计规则重复的晶体管区块。标准单元可用于不同功能。举例来说，标准单元可为逻辑操作锁用的逻辑单元或静态随机存取存储器标准单元。标准单元可包含一或多个p型晶体管与一或多个n型晶体管。晶体管可为平面晶体管或多栅极晶体管，比如鳍状场效晶体管或全绕式栅极晶体管。为了制作晶体管于基体基板上，可形成掺杂n型掺质的n型井与掺杂p型掺质的p型井于基体基板中，并形成相反导电型态的有源区于个别的n型井与p型井上。综上所述，p型晶体管包括p型有源区形成于n型井上，而n型晶体管包括n型有源区形成于p型井上。当n型晶体管与p型晶体管相邻时，p型有源区、p形有源区下的n型井、与相邻的p型井(有时p型井形成于整个基板上)可形成寄生PNP双极性晶体管。类似地，n型有源区、n型有源区之下的p型有源井(有时p型井形成于整个基板上)、与相邻的n型井可形成寄生NPN双极性晶体管。可闩锁寄生NPN与PNP双极性晶体管以形成短接漏极电源电压与地线的反向放大器，其将破坏装置。
可由寄生双极晶体管实施分接单元，以避免漏极短接至地线。在一些例子中，分接单元可用于耦接n型井至漏极电源电压(或正电源电压)。在一些实施例中，漏极电源电压为集成电路装置或标准单元的正电压，而源极电源电压为集成电路装置或标准单元的负电压。源极电源电压可为地线电压或接地。分接单元可具有晶体管的形状，但不具有功能栅极结构。分接单元的功能为经由其源极/漏极区避免闩锁。与标准单元中的晶体管不同，分接单元中的有源区与下方井的导电型态相同。举例来说，当分接单元形成于n型井上时，其有源区掺杂n型掺质而非p型掺质。当分接单元形成于p型井上时，其有源区掺杂p型掺质而非n型掺质。
虽然现有设计中的分接单元可解决闩锁问题，其仍占有空间并减少集成电路芯片中的功能密度。举例来说，一些现有设计中的n型井与p型井(各自具有伸长的形状)可沿着相同方向延伸且交错配置。在这些现有设计中，伸长的有源区如鳍状物或通道部件的垂直堆叠可形成于n型井或p型井上，并掺杂不同型态的掺质。虽然分接单元与标准单元形成于相同有源区中，但应避免不同掺杂型态的两者紧邻。这是因为当分接单元的有源区紧邻标准单元的不同导电型态有源区时，会使标准单元的电性飘移而劣化效能。为了隔离分接单元与相邻的标准单元，导入不连续的有源区。由于有源区位于含有氧化物的隔离结构(如浅沟槽隔离)中并由隔离结构定义，有源区可称作氧化物定义区，而有源区的不连续可视作氧化物定义区分开处。在一些实施例中，可在沉积隔离结构与形成源极/漏极结构之前形成氧化物定义区分开处。由于在形成隔离结构之前形成氧化物定义区分开处，隔离结构所用的材料亦沉积于氧化物定义区分开处中。由于在形成施加应力于有源区上的源极/漏极结构之前形成氧化物定义区分开处，与氧化物定义区分开处相邻的有源区暴露致不同环境并具有不同特性。氧化物定义区分开处亦因此造成布局相关效应，即分接单元的另一有源区会分开标准单元的有源区。为了解决氧化物定义区分开处所造成的布局相关效应，可导入多种尺寸的虚置单元至标准单元与氧化物定义区分开处之间，以作为氧化物定义区分开处与标准单元之间的过渡区。在实施分接单元时，分接单元、氧化物定义区分开处、与虚置单元都会占据集成电路芯片的空间但不具有功能。
本发明实施例提供方法以形成半导体氧化物结构于源极/漏极结构之下，以得拟绝缘层上硅结构。半导体氧化物结构可绝缘源极/漏极结构与基板，进而避免闩锁而不需实施任何分接单元或保护环等占据空间的结构。此外，本发明实施例可提供额外优点。举例来说，半导体氧化物结构可避免漏电流穿过通道区基底的抗击穿注入区。换言之，本发明实施例的结构享有基体装置与绝缘层上硅装置的优点。
图1显示形成半导体装置的方法100。方法100的步骤将搭配图2至19说明，其显示进行方法100的工件200的部分剖视图。方法100仅为一例，而非局限本发明实施例至方法100实际记载处。可在方法100之前、之中、与之后提供额外步骤，且方法的额外实施例可置换、省略、或调换一些所述步骤。此处并未详述所有步骤以简化说明。制作工艺的结果为制作工件200成半导体装置。因此工件200与半导体装置可依说明需求互换。此外，此处所述的例示性半导体装置可包含多种其他装置与结构，比如其他种类的装置如额外晶体管、双极性接面晶体管、电阻、电容器、电感、二极管、熔丝、静态随机存取存储器、及/或其他逻辑电路，但相关内容已简化以利理解本发明实施例的发明概念。在一些实施例中，例示性的装置包括多个半导体装置如晶体管，其可内连线。此外，应注意本发明实施例的方法100的工艺步骤与附图，仅用于举例说明而非局限本发明实施例至权利要求未实际记载处。
图2至19包括末尾为(A)的附图如图2(A)，以及末尾为B的附图如图2(B)。附图末尾为(A)者指的是工件200的第一区1000的部分剖视图，而附图末尾为(B)者指的是工件200的第二区2000的部分剖视图。如下所述，本发明实施例的方法可实施不同处理于第一区1000与第二区2000中。
如图1及2所示，方法100的步骤102接收工件200。工件200包括多个交错的半导体层于其第一区1000与第二区2000上。如图2所示，工件200包括基板202。在一些实施例中，基板202可为半导体基板如硅基板。基板202可包含多种层状物，包含导电或绝缘层形成于半导体基板上。基板202可包含多种掺杂设置，端视本技术领域已知的设计需求而定。举例来说，可形成不同掺杂轮廓(如n型井或p型井)于基板202上的区域中，其设计为用于不同装置型态(比如n型多栅极晶体管或p型多栅极晶体管)。合适的掺杂方法可包含离子注入掺质及/或扩散工艺。基板202可具有隔离结构夹设于区域之间以提供不同的装置型态。基板202亦可包括其他半导体如锗、碳化硅、硅锗、或钻石。基板202可改为包含半导体化合物及/或半导体合金。此外，基板202可视情况包含外延层(可具有应力以增进效能)，可包含绝缘层上硅结构、及/或可具有其他合适的增进结构。在方法100的一实施例中，进行抗击穿注入以形成抗击穿注入区203。抗击穿注入区203形成于通道区之下，其功能为避免击穿或不想要的扩散。
在图2所示的一些实施例中，外延堆叠204形成于第一区1000与第二区2000的基板202上。外延堆叠204包括第一半导体组成的外延层206夹设于第二半导体组成的外延区208之间。第一半导体组成与第二半导体组成可不同。在一实施例中，外延层206为硅锗而外延层208为硅。然而含有不同氧化速率及/或蚀刻选择性的第一组成与第二组成的其他实施例亦属可能。在一些实施例中，外延层206包括硅锗，而外延层208包括硅。
值得注意的是，图2与后续附图显示五个外延层206与四个外延层208交错配置，但此仅用于举例说明而非局限本发明实施例至权利要求为实际记载处。应理解可形成任何数目的外延层于外延堆叠204中。外延层的数目取决于装置如工件200所需的通道数目。在一些实施例中，外延层208的数目介于2至10之间。在一些实施例中，所有外延层206可具有实质上一致的第一厚度，而所有外延层208可具有实质上一致的第二厚度。第一厚度与第二厚度可相同或不同。如下详述，外延层208或其部分将做为后续形成的多栅极装置所用的通道部件，且每一外延层208的厚度取决于装置效能考量。最后将移除通道区中的外延层206，以定义后续形成的多栅极装置所用的相邻通道区之间的垂直距离(如空间)，而外延层206的厚度取决于装置效能考量。综上所述，外延层206亦可视作牺牲层，而外延层208亦可视作通道层。
举例来说，外延成长外延堆叠204的层状物的方法可为分子束外延工艺、有机金属化学气相沉积工艺、及/或其他合适的外延成长工艺。在一些实施例中，外延层成长的层状物如外延层208包含的材料与基板202相同。在一些实施例中，外延层206及208包含的材料与基板202不同。如上所述，至少一些例子的外延层206包括外延成长的硅锗层，而外延层208包含外延成长的硅层。在一些其他实施例中，外延层206及208可包含其他材料如锗、半导体化合物(如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、及/或锑化铟)、半导体合金(如硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化铟镓、磷化镓铟、及/或磷砷化镓铟)、或上述的组合。如上所述，可选择外延层206及208的材料以提供不同的氧化特性与蚀刻选择性。在一些实施例中，外延层206及208实质上无掺质(比如本质的掺质浓度为约0cm-3至约1x1017cm-3)。举例来说，在外延成长工艺时不刻意进行掺杂。
如图1及2所示，方法100的步骤104形成第一鳍状结构205A于第一区1000中，并形成第二鳍状结构205B于第二区2000中。步骤104图案化基板202上的外延堆叠204，以形成第一鳍状结构205A于第一区1000中，并形成第二鳍状结构205B于第二区2000中。第一鳍状结构205A与第二鳍状结构205B自基板202延伸，且其长度方向沿着X方向延伸。在一些实施例中，图案化步骤亦蚀刻至基板202中，使第一鳍状结构205A与第二鳍状结构205B的每一者包含由基板202形成的下侧部分，以及由外延堆叠204形成的上侧部分。上侧部分包含外延堆叠204的每一外延层。第一鳍状结构205A与第二鳍状结构205B的制作方法可采用合适工艺，其包含双重图案化或多重图案化工艺。一般而言，双重图案化或多重图案化工艺结合光学光刻与自对准工艺，其产生的图案间距小于采用单一的直接光学光刻工艺所得的图案间距。举例来说，一实施例形成牺牲层于基板上，并采用光学光刻工艺图案化牺牲层。采用自对准工艺可沿着图案化的牺牲层侧部形成间隔物。接着移除牺牲层，而保留的间隔物或芯之后可用于蚀刻外延堆叠204以图案化第一鳍状结构205A与第二鳍状结构205B。蚀刻工艺可包含干蚀刻、湿蚀刻、反应性离子蚀刻、及/或其他合适工艺。
虽然图2未显示，形成第一鳍状结构205A与第二鳍状结构205B之后，可形成隔离结构于相邻的第一鳍状结构205A之间与相邻的第二鳍状结构205B之间。隔离结构亦可视作浅沟槽隔离结构。举例来说，一些实施例先沉积介电层于基板202上、以将介电材料填入鳍状结构(如第一鳍状结构205A与第二鳍状结构205B)之间的沟槽。在一些实施例中，介电层可包含氧化硅、氮化硅、氮氧化硅、氟硅酸盐玻璃、低介电常数的介电层、上述的组合、及/或其他合适材料。在多种例子中，介电层的沉积方法可为化学气相沉积工艺、次压化学气相沉积工艺、可流动的化学气相沉积工艺、原子层沉积工艺、物理气相沉积工艺、及/或其他合适工艺。接着可薄化与平坦化沉积的介电材料，比如进行化学机械研磨工艺。接着可使平坦化的介电层进一步凹陷以形成浅沟槽隔离结构，且凹陷的方法可为干蚀刻工艺、湿蚀刻工艺、及/或上述的组合。第一鳍状结构205A与第二鳍状结构205B可***高于浅沟槽隔离结构。在一些实施例中，介电层(与后续形成的浅沟槽隔离结构)可包含多层结构，比如具有一或多个衬垫层。
如图1及2所示，方法100的步骤106形成虚置栅极堆叠210于第一区1000中的第一鳍状结构205A与第二区2000中的第二鳍状结构205B的通道区10上。一些实施例采用栅极置换工艺(如栅极后制工艺)，其中虚置栅极堆叠210作为功能栅极结构所用的占位物，后续步骤中将被移除并置换为功能栅极结构。其他工艺与设置亦属可能。在一些实施例中，虚置栅极堆叠210形成于基板202上，且至少部分地位于第一鳍状结构205A与第二鳍状结构205B上。第一鳍状结构205A或第二鳍状结构205B位于虚置栅极堆叠210之下的部分，为第一鳍状结构205A或第二鳍状结构205B的通道区。虚置栅极堆叠210亦可定义源极/漏极区20于通道区10的两侧上，且源极/漏极区20与通道区10相邻。
在所述实施例中，步骤106先形成虚置栅极介电层212于鳍状结构(如第一鳍状结构205A与第二鳍状结构205B)上。在一些实施例中，虚置栅极介电层212可包含氧化硅、氮化硅、高介电常数的介电材料、及/或其他合适材料。在多种例子中，虚置栅极介电层212的沉积方法可为化学气相沉积工艺、次压化学气相沉积工艺、可流动的化学气相沉积工艺、原子层沉积工艺、物理气相沉积工艺、或其他合适工艺。举例来说，虚置栅极介电层212可用于避免后续工艺(如形成虚置栅极堆叠的方法)损伤鳍状结构205。步骤106接着形成虚置栅极堆叠210的其他部分，包括虚置栅极层214与硬遮罩216(其可包含多层如氧化物层218与氮化物层220)。在一些实施例中，虚置栅极堆叠210的形成方法可为多种工艺步骤，比如沉积层状物、图案化、与蚀刻，以及其他合适工艺部分。例示性的沉积层状物的工艺包含低压化学气相沉积、化学气相沉积、电浆辅助化学气相沉积、物理气相沉积、原子层沉积、热氧化、电子束蒸镀、其他合适的沉积技术、或上述的组合。举例来说，图案化工艺可包含光刻工艺(如光学光刻或电子束光刻)，其可进一步包括光致抗蚀剂涂布(如旋转涂布)、软烘烤、对准光罩、曝光、曝光后烘烤、显影光致抗蚀剂、冲洗、干燥(如旋干及/或硬烘烤)、其他合适的光刻技术、及/或上述的组合。在一些实施例中，蚀刻工艺可包含干蚀刻(如反应性离子蚀刻)、湿蚀刻、及/或其他蚀刻方法。在一些实施例中，虚置栅极层214可包含多晶硅。硬遮罩216可包含多层。在一些实施例中，硬遮罩216包含氧化物层218如含氧化硅的垫氧化物层，以及含氮化硅及/或氮氧化硅的垫氮化物层的氮化物层220
如图2所示的一些实施例，形成虚置栅极堆叠210之后，自鳍状结构205的源极/漏极区20移除虚置栅极介电层212。此步骤移除虚置栅极层214未覆盖的虚置栅极介电层212。移除工艺可包含湿蚀刻、干蚀刻、及/或上述的组合。选择蚀刻工艺以选择性地蚀刻虚置栅极介电层212，而实质上不蚀刻鳍状结构205、硬遮罩216、与虚置栅极层214。
如图1及2所示，方法100的步骤108形成栅极间隔物层222于虚置栅极堆叠210上。在一些实施例中，可顺应性沉积栅极间隔物层222所用的间隔物材料于工件200上，包括虚置栅极堆叠210与鳍状结构205的上表面与侧壁上，以形成间隔物材料层。此处的用语“顺应性”可简单说明层状物在不同区上具有实质上一致的厚度。栅极间隔物层222可包含单层结构或包含多层。在图2所示的一些实施例中，栅极间隔物层222包括第一栅极间隔物层222-1、第二栅极间隔物层222-2、与第三栅极间隔物层222-3。在这些实施例中，第一栅极间隔物层222-1、第二栅极间隔物层222-2、与第三栅极间隔物层222-3可具有不同组成以导入蚀刻选择性。第一栅极间隔物层222-1、第二栅极间隔物层222-2、与第三栅极间隔物层222-3可包含氮化硅、铪硅化物、氮氧化铝、氧化铪、氧化镧、氧化铝、氮化锆、碳化硅、氧化锌、碳氮氧化硅、硅、氧化钇、碳氮化钽、锆硅化物、碳氮化硅、氧化锆铝、氧化钛、氧化钽、氧化锆、碳氧化硅、或氧化硅。间隔物材料层沉积于虚置栅极堆叠210与鳍状结构205上的工艺，可采用化学气相沉积工艺、次压化学气相沉积工艺、可流动的化学气相沉积工艺、原子层沉积工艺、物理气相沉积工艺、或其他合适工艺。
如图1及3所示，方法100的步骤110形成源极/漏极沟槽228。虽然未直接图示，但可采用光学光刻工艺与至少一硬遮罩进行步骤110。在一些实施例中，蚀刻虚置栅极堆叠210与栅极间隔物层222未覆盖的鳍状结构205的部分以形成源极/漏极沟槽228，且蚀刻方法可为干蚀刻或合适的蚀刻工艺。举例来说，干蚀刻工艺可实施含氧气体、含氟气体(如四氟化碳、六氟化硫、二氟甲烷、氟仿、及/或六氟乙烷)、含氯气体(如氯气、氯仿、四氯化碳、及/或三氯化硼)、含溴气体(如溴化氢及/或溴仿)、含碘气体、其他合适气体及/或电浆、及/或上述的组合。在图3所示的实施例中，使鳍状结构205的上侧部分凹陷以露出源极/漏极沟槽228中的牺牲层如外延层206与通道层如外延层208。在一些实施例中，使鳍状结构205的下侧部分至少一部分凹陷。因此源极/漏极沟槽228可延伸至最底部的牺牲层如外延层206之下以及抗击穿注入区203中。
如图1及4所示，方法100的步骤112形成内侧间隔物结构224。步骤112包括形成内侧间隔物凹陷、沉积内侧间隔物层、并拉回沉积的内侧间隔物层。如图4所示，在源极/漏极沟槽228中露出牺牲层如外延层206与通道层如外延层208之后，可使牺牲层如外延层206选择性地部分凹陷，以形成内侧间隔物凹陷(将填有图4中的内侧间隔物结构224)于相邻的通道区如外延层208之间，而实质上不蚀刻露出的通道层如外延层208。在一实施例中，通道层如外延层208基本上为硅，牺牲层如外延层206基本上为硅锗，而使牺牲层如外延层206选择性凹陷的步骤可包含硅锗氧化工艺与之后的硅锗氧化物移除工艺。在这些实施例中，硅锗氧化工艺可采用臭氧。在一些实施例中，选择性凹陷可为选择性等向蚀刻工艺(比如选择性干蚀刻工艺或选择性湿蚀刻工艺)，且蚀刻工艺的时间可控制牺牲层如外延层206的凹陷量。在一些实施例中，选择性干蚀刻工艺可采用一或多种氟为主的蚀刻剂，比如氟气或碳氢氟化合物。如图4所示，内侧间隔物凹陷自源极/漏极沟槽228沿着X方向延伸至通道区10中。在一些实施例中，选择性湿蚀刻工艺可包含氢氟酸或氢氧化铵蚀刻剂。
在步骤112中，形成内侧间隔物凹陷之后，可沉积一或多个内侧间隔物层于工件200的第一区1000与第二区2000上。在图4所示的一些实施例中，步骤112沉积两个内侧间隔物层，比如第一内侧间隔物层224-1与第二内侧间隔物层224-2。第一内侧间隔物层224-1与第二内侧间隔物层224-2的材料组成可为氮化硅、铪硅化物、氮氧化铝、氧化铪、氧化镧、氧化铝、氮化锆、碳化硅、氧化锌、碳氮氧化硅、硅、氧化钇、碳氮化钽、锆硅化物、碳氮化硅、氧化锆铝、氧化钛、氧化钽、氧化锆、碳氧化硅、或氧化硅。在一实施例中，第一内侧间隔物层224-1的组成可为富碳的碳氮化硅，而第二内侧间隔物层224-2的组成可为氧化硅。第一内侧间隔物层224-1与第二内侧间隔物层224-2的沉积方法可为化学气相沉积、电浆辅助化学气相沉积、低压化学气相沉积、原子层沉积、或其他合适方法。第一内侧间隔物层224-1与第二内侧间隔物层224-2的厚度可各自介于约1nm至约5nm之间。
接着可拉回(如回蚀刻)一或多个内侧间隔物层，以形成内侧间隔物结构224于内侧间隔物凹陷中。在一些实施例中，等向地选择性回蚀刻第二内侧间隔物层224-2，直到自硬遮罩216的上表面、栅极间隔物层222的上表面、源极/漏极沟槽228中露出的基板202的部分、与位于栅极间隔物层222上的第一内侧间隔物层224-1完全移除第二内侧间隔物层224-2。第一内侧间隔物层224-1的组成可与第二内侧间隔物层224-2的组成不同，以在选择性蚀刻第二内侧间隔物层224-2时，第一内侧间隔物层224-1具有较慢的蚀刻速率。在一些实施方式中，步骤112进行的等向蚀刻可采用氢氟酸、氟气、氢气、氨、三氟化氮、或其他氟为主的蚀刻剂。如图4所示，内侧间隔物凹陷中拉回的第二内侧间隔物层224-2与第一内侧间隔物层224-1，构成内侧间隔物结构224。内侧间隔物结构224使相邻的通道区如外延层208彼此部分地分开，或使最底部的通道区如外延层208与抗击穿注入区203部分地分开。
如图1及4所示，方法100的步骤114沉积第一阻挡层230于工件200上。在一些实施例中，第一阻挡层230的组成为介电材料而不适于外延成长，因此其可用于限制半导体材料外延成长于预定区。第一阻挡层230的材料组成可为氮化硅、铪硅化物、氮氧化铝、氧化铪、氧化镧、氧化铝、氮化锆、碳化硅、氧化锌、碳氧化硅、硅、氧化钇、碳氮化钽、锆硅化物、碳氮化硅、氧化锆铝、氧化钛、氧化钽、氧化锆、碳氧化硅、或氧化硅。在一实施例中，第一阻挡层230可包含氮化硅。如图4所示，第一阻挡层230可沉积于第一内侧间隔物层224-1(其沉积于源极/漏极沟槽228中露出的硬遮罩216、栅极间隔物层222、与基板202的一部分上)与内侧间隔物结构224上。在一些例子中，第一阻挡层230的沉积方法可采用原子层沉积。
如图1及5所示，方法100的步骤116非等向拉回第一阻挡层230，以移除顶面表面上的第一阻挡层230的部分。如图5所示，步骤116的结果为露出源极/漏极沟槽228的底部的基板202的一部分以形成成长表面232，而第一阻挡层230维持覆盖通道层如外延层208。在一些实施方式中，回蚀刻第一阻挡层230的方法可为干蚀刻或合适的蚀刻工艺。
如图1及6所示，方法100的步骤118外延形成第一外延结构234于源极/漏极区20上的源极/漏极沟槽228中。在一些实施例中，可自图5所示的成长表面232选择性外延成长第一外延结构234。在这些实施方式中，第一外延结构234的组成为含硅与锗的半导体材料。在一实施例中，第一外延结构234包括含硅与锗的半导体合金材料，其中硅含量介于约55原子％至约80原子％之间，而锗含量介于约20原子％至约45原子％之间。第一外延结构234可自露出的半导体表面(如图5所示的成长表面232)成长，且不自介电材料表面(如第一阻挡层230的表面)成长。第一阻挡层230的配置因此可确保第一外延结构234由下至上地自成长表面232成长。如图6所示，第一外延结构234自基板202的上表面量测的深度为第一深度D1。在一些例子中，第一深度D1使第一外延结构234的上表面比最底部的通道部件如外延层208的上表面更远离基板202。
如图1、7及8所示，方法100可视情况包含步骤120以选择性拉回第二区2000中的第一外延结构234至第二深度D2，且第二深度D2小于第一深度D1。如图7所示，为了选择性拉回第二区2000中的第一外延结构234，可采用第一底抗反射涂层236遮罩第一区1000。为了形成底抗反射涂层遮罩于第一区1000上，可毯覆性地沉积底抗反射涂层材料层于工件200上，并采用光学光刻技术图案化底抗反射涂层材料层成第一底抗反射涂层236于第一区1000上。在例示性工艺中，采用旋转涂布以沉积光致抗蚀剂层于底抗反射涂层材料层上。接着预烘烤光致抗蚀剂层、以射线源曝光光致抗蚀剂层、曝光后烘烤光致抗蚀剂层、并在显影溶液中显影光致抗蚀剂层，以形成图案化的光致抗蚀剂层。采用图案化的光致抗蚀剂层作为蚀刻遮罩，并蚀刻毯覆性的底抗反射涂层材料层以形成第一底抗反射涂层236。以第一底抗反射涂层236遮罩第一区1000，接着可蚀刻第二区2000中的第一外延结构234以得第二外延结构235。第二外延结构235的第二厚度如第二深度D2小于第一厚度如第一深度D1。如图7所示，第二厚度如第二深度D2使第二外延结构235的上表面低于最底部的通道部件如外延层208的下表面。如图8所示，拉回第一外延结构234之后，可自第一区1000移除第一底抗反射涂层236。
如图1及9所示，方法100的步骤122氧化第一外延结构234。在一些实施例中，步骤122可对工件200进行退火工艺，使第一外延结构234与第二外延结构235分别转换成第一半导体氧化物结构2340与第二半导体氧化物结构2350。在第一外延结构234与第二外延结构235的组成为硅锗的实施例中，第一半导体氧化物结构2340与第二半导体氧化物结构2350的组成为硅锗氧化物。在一些实施例中，退火工艺可包含快速热退火工艺、激光峰值退火工艺、快闪退火工艺、或炉退火工艺。在一些例子中，退火工艺的温度可介于约300℃至约650℃之间。在一些实施例中，步骤122的退火工艺亦可采用氧化剂如臭氧、水、或氧气。在第一区1000中，第一阻挡层230的保留部分位于第一半导体氧化物结构2340与最底部的通道层如外延层208之间，并位于第一半导体氧化物结构2340与抗击穿注入区203之间。类似地，第二区2000中的第一阻挡层230的保留部分位于第二半导体氧化物结构2350与最底部的通道层如外延层208之间，并位于第二半导体氧化物结构2350与抗击穿注入区203之间。
选择第一外延结构234与第二外延结构235的组成，以充分氧化第一外延结构234与第二外延结构235而不损伤基板202与通道区如外延层208。如上所述，第一外延结构234以及第二外延结构235可包括含硅与锗的半导体合金材料，其中硅含量介于约55原子％至约80原子％之间，而锗含量介于约20原子％至约45原子％之间。当硅原子浓度大于80％时，锗的存在无法充分催化硅锗的氧化，且氧化速率不足以有效氧化第一外延结构234与第二外延结构235。然而当硅原子浓度小于55原子％时，第一外延结构234与第二外延结构235中可能存在过多缺陷。
如图9所示，在第一外延结构234与第二外延结构235的组成为硅锗的实施例中，锗可能累积于上述外延结构与基板202的界面。锗累积会造成第一半导体氧化物结构2340的下表面与基板202之间的锗结构2342以及第二半导体氧化结构2350的下表面与基板202之间的锗结构2342。
如图1及10所示，方法100的步骤124沉积第二阻挡层238于工件上。在一些例子中，由于蚀刻与退火可能损伤第一阻挡层230，因此需进行步骤124。为了适当地保护下方结构，可采用合适的蚀刻工艺选择性移除第一阻挡层230，并重新沉积第二阻挡层238。步骤124将第一阻挡层230置换成第二阻挡层238。由于第二阻挡层238与第一阻挡层230的组成与形成方法类似，在此不重述第二阻挡层238的细节。第二阻挡层238沉积于第一区1000中的第一半导体氧化物结构2340、第二区2000中的第二半导体氧化物结构2350、栅极间隔物层222、硬遮罩216、通道层如外延层208、与内侧间隔物结构224上。在图10所示的实施例中，直接沉积第二阻挡层238于第一区1000中的第一半导体氧化物结构2340、第二区2000中的第二半导体氧化物结构2350、栅极间隔物层222、硬遮罩216、通道层如外延层208、与内侧间隔物结构224上。
如图1、11、及12所示，方法100的步骤126选择性移除第一区1000中的第二阻挡层238。如图11所示，为了选择性移除第一区1000中的第二阻挡层238，可采用第二底抗反射涂层240遮罩第二区2000。为了形成底抗反射涂层遮罩于第二区2000上，可毯覆性沉积底抗反射涂层材料层于工件200上，并采用光学光刻技术以图案化底抗反射涂层材料层成第二底抗反射涂层240于第二区2000上。在工艺的一例中，采用旋转涂布以沉积光致抗蚀剂层于底抗反射涂层材料层上。接着预烘烤光致抗蚀剂层、以射线源曝光光致抗蚀剂层、曝光后烘烤光致抗蚀剂层、并在显影溶液中显影光致抗蚀剂层以形成图案化的光致抗蚀剂层。采用图案化的光致抗蚀剂层作为蚀刻遮罩，并蚀刻毯覆性的底抗反射涂层材料层以形成第二底抗反射涂层240。由于第二底抗反射涂层240遮罩第二区2000，可选择性移除第一区1000中的第二阻挡层238以露出通道层如外延层208的侧壁(如侧表面)。如图12所示，移除第一区1000中的第二阻挡层238之后，可自第二区2000移除第二底抗反射涂层240。
如图1及13所示，方法100的步骤128选择性沉积第一源极/漏极结构242于第一区1000中。步骤128所用的合适外延工艺包含化学气相沉积技术(如气相外延及/或超高真空化学气相沉积)、分子束外延、及/或其他合适工艺。外延成长工艺可采用气态及/或液态前驱物，其可与通道层如外延层208的组成作用。在图13(A)及13(B)所示的实施例中，自第二区2000中的通道层如外延层208成长第一源极/漏极结构242，而不成长于第二阻挡层238上。第一区1000中的第一源极/漏极结构242与基板202隔有第一半导体氧化物结构2340与第一阻挡层230。此外，第一源极/漏极结构242亦与牺牲层如外延层206隔有内侧间隔物结构224。第一源极/漏极结构242可为n型或p型，端视设计需求而定。当第一源极/漏极结构242为n型时，第一源极/漏极结构242可包含硅、砷化镓、磷砷化镓、磷化硅、或其他合适材料。当第一源极/漏极结构242为p型时，第一源极/漏极结构242可包含硅、锗、砷化铝镓、硅锗、硼化硅锗、或其他合适材料。可在外延工艺时导入含掺质的掺杂物种，以原位掺杂第一源极/漏极结构242。若不原位掺杂第一源极/漏极结构242，可进行注入工艺(如接面注入工艺)以掺杂第一源极/漏极结构242。在其他实施例中，第一源极/漏极结构242为p型且包含硼化硅锗。
如图1及14所示，方法100的步骤130沉积第三阻挡层244于工件200上。在一些例子中，第二阻挡层238可能因工艺损伤而需进行步骤130。为了适当地保护下方结构，可采用合适的蚀刻工艺选择性移除第二阻挡层238，并新沉积第三阻挡层244。因此步骤130将第二阻挡层238置换成第三阻挡层244。由于第三阻挡层244与第一阻挡层230的组成与形成方法类似，在此不重述第三阻挡层244的细节。如图14(A)所示，第一区1000中的第三阻挡层244沉积于第一源极/漏极结构242、栅极间隔物层222、与硬遮罩216上。如图14(B)所示，在第二区2000中沉积第三阻挡层244于第二半导体氧化物结构2350、栅极间隔物层222、硬遮罩216、通道层如外延层208、与内侧间隔物结构224上。
如图1、15、及16所示，方法100的步骤132选择性移除第二区2000中的第三阻挡层244。如图15所示，为了选择性移除第二区2000中的第三阻挡层244，可采用第三底抗反射涂层246以遮罩第一区1000。为了形成底抗反射涂层遮罩于第一区1000上，可毯覆性沉积底抗反射涂层材料层于工件200上，并采用光学光刻技术以图案化底抗反射涂层材料层成第三底抗反射涂层246于第一区1000上。在工艺的一例中，采用旋转涂布以沉积光致抗蚀剂层于底抗反射涂层材料层上。接着预烘烤光致抗蚀剂层、以射线源曝光光致抗蚀剂层、曝光后烘烤光致抗蚀剂层、并在显影溶液中显影光致抗蚀剂，以形成图案化的光致抗蚀剂层。采用图案化的光致抗蚀剂层作为蚀刻遮罩，并毯覆性的底抗反射涂层材料层以形成第三底抗反射涂层246。由于第三底抗反射涂层246遮罩第一区1000，可选择性移除第二区2000中的第三阻挡层244以露出通道层如外延层208的侧壁(如侧表面)。如图16所示，在移除第二区2000中的第三阻挡层244之后，可自第一区1000移除第三底抗反射涂层246。
如图1及17所示，方法100的步骤134选择性沉积第二源极/漏极结构248于第二区2000中。步骤134所用的合适外延工艺包含化学气相沉积技术(比如气相外延及/或超高真空化学气相沉积)、分子束外延、及/或其他合适工艺。外延成长工艺可采用气态及/或液态前驱物，其可与通道层如外延层208的组成作用。在图17(A)及17(B)所示的实施例中，第二区2000中的第二源极/漏极结构248直接接触通道层如外延层208。第二区2000中的第二源极/漏极结构248与基板202隔有第二半导体氧化物结构2350与第一阻挡层230。第二源极/漏极结构248可自第二区2000中的通道层如外延层208成长，而不成长于第一区1000中的第三阻挡层244上。此外，第二源极/漏极结构248亦与牺牲层如外延层206隔有内侧间隔物结构224。第二源极/漏极结构248可为n型或p型，端视设计需求而定。当第二源极/漏极结构248为n型时，第二源极/漏极结构248可包含硅、砷化镓、磷砷化镓、磷化硅、或其他合适材料。当第二源极/漏极结构248为p型时，第二源极/漏极结构248可包含硅、锗、砷化铝镓、硅锗、硼化硅锗、或其他合适材料。可在外延工艺时导入含掺质的掺杂物种，以原位掺杂第二源极/漏极结构248。若不原位掺杂第二源极/漏极结构248，可进行注入工艺(如接面注入工艺)以掺杂第二源极/漏极结构248。在一实施例中，第二源极/漏极结构248为n型且包含硅与磷。
如图1及18所示，方法100的步骤136移除第三阻挡层244。为了使工件200用于后续工艺，移除覆盖第一区1000的保留的第三阻挡层244，如图17所示。如图18所示，步骤136之后可露出第一区1000中的栅极间隔物层222、硬遮罩216的上表面、与第一源极/漏极结构242的上表面，并露出第二区2000中的栅极间隔物层222、硬遮罩216的上表面、与第二源极/漏极结构248的上表面。
如图1及19所示，方法100的步骤138进行后续工艺。如图19(含19(A)及19(B))所示，后续工艺可包含沉积接点蚀刻停止层250、沉积层间介电层252、移除硬遮罩216的平坦化工艺、移除虚置栅极层214与虚置栅极介电层212、释放通道层如外延层208以形成通道部件如外延层208、形成栅极结构254、与平坦化工件200。在一些例子中，接点蚀刻停止层250包括氮化硅层、氧化硅层、氮氧化硅层、及/或本技术领域已知的其他材料。接点蚀刻停止层250的形成方法可为原子层沉积、电浆辅助化学气相沉积工艺、及/或其他合适的沉积或氧化工艺。接着沉积层间介电层252于接点蚀刻停止层250上。在一些实施例中，层间介电层252的材料包括四乙氧基硅烷的氧化物、未掺杂的硅酸盐玻璃、或掺杂氧化硅(如硼磷硅酸盐玻璃、氟硅酸盐玻璃、磷硅酸盐玻璃、硼硅酸盐玻璃、及/或其他合适的介电材料。层间介电层252的沉积方法可为电浆辅助化学气相沉积或其他合适的沉积技术。在一些实施例中，形成层间介电层252之后可退火工件200以改善层间介电层252的完整性。
在一些例子中，沉积层间介电层252之后可进行平坦化工艺以移除多余的介电材料。举例来说，平坦化工艺包含化学机械研磨工艺，其可移除虚置栅极堆叠210上的层间介电层252(与接点蚀刻停止层250，若存在)，并平坦化工件200的上表面。在一些实施例中，化学机械研磨工艺亦移除硬遮罩216并露出虚置栅极层214。露出虚置栅极层214之后，可移除虚置栅极层214、移除虚置栅极介电层212、并释放通道层如外延层208。
在一些实施例中，移除虚置栅极层214与虚置栅极介电层212会造成栅极沟槽于第一区1000与第二区2000中的通道区10上。移除虚置栅极层214与虚置栅极介电层212的方法可包含一或多道蚀刻工艺，其对虚置栅极层214与虚置栅极介电层212中的材料具有选择性。举例来说，可采用选择性湿蚀刻、选择性干蚀刻、或上述的组合以移除虚置栅极层214与虚置栅极介电层212，其对虚置栅极层214与虚置栅极介电层212具有选择性。在移除虚置栅极层214与虚置栅极介电层212之后，栅极沟槽中露出外延层206及208的侧壁。
在移除虚置栅极层214与虚置栅极介电层212之后，方法100可选择性移除第一区1000与第二区2000中的通道区10中的通道层如外延层208之间的牺牲层如外延层206。选择性移除牺牲层如外延层206，可释放通道层如外延层208以形成通道部件如外延层208。值得注意的是，相同标号208用于标示通道部件如外延层208以简化附图。可实施选择性干蚀刻、选择性湿蚀刻、或其他选择性蚀刻工艺，以选择性移除牺牲层如外延层206。在一些实施例中，选择性湿蚀刻包括氢氧化铵、过氧化氢、与水的混合物蚀刻。在一些实施例中，选择性移除步骤包括硅锗氧化步骤与之后的硅锗氧化物移除步骤。举例来说，可由臭氧清洁进行氧化，接着以蚀刻剂如氢氧化铵移除硅锗氧化物。
方法100可包含后续步骤以形成栅极结构254。在一些实施例中，形成栅极结构254于工件200上的栅极沟槽中，即沉积于移除牺牲层如外延层206所留下的空间中。在此考量下，栅极结构254包覆第一区1000与第二区2000中的每一通道部件如外延层208。在多种实施例中，每一栅极结构254包括界面层、高介电常数的栅极介电层位于界面层上、及/或栅极层形成于高介电常数的栅极介电层上。此处所述的高介电常数的栅极介电层包含高介电常数(比如大于氧化硅的介电常数如3.9)的介电材料。栅极结构254中所用的栅极层可包含金属、金属合金、或金属硅化物。
在一些实施例中，栅极结构254的界面层可包含介电材料如氧化硅、硅酸铪、或氮氧化硅。界面层的形成方法可为化学氧化、热氧化、原子层沉积、化学气相沉积、及/或其他合适方法。栅极结构254的高介电常数的栅极介电层可包含高介电常数的介电层如氧化铪。在其他实施例中，栅极结构254的高介电常数的栅极介电层可包含其他高介电常数的介电层，比如氧化钛、氧化铪锆、氧化钽、硅酸铪、二氧化锆、氧化锆硅、氧化镧、氧化铝、氧化锆、氧化钛、氧化钽、氧化钇、钛酸锶、钛酸钡、氧化钡锆、氧化铪锆、氧化铪镧、氧化铪硅、氧化镧硅、氧化铝硅、氧化铪钽、氧化铪钛、钛酸钡锶、氧化铝、氮化硅、氮氧化硅、上述之组合、或其他合适材料。高介电常数的栅极介电层的形成方法可为原子层沉积、物理气相沉积、化学气相沉积、氧化、及/或其他合适方法。
栅极结构254的栅极层可包含单层或多层结构，比如具有选定功函数以增进装置效能的金属层(如功函数金属层)、衬垫层、湿润层、黏着层、金属合金、或金属硅化物的多种组合。举例来说，栅极结构254的栅极层可包含钛、银、铝、氮化钛铝、碳化钽、碳氮化钽、氮化钽硅、锰、锆、氮化钛、氮化钽、钌、钼、铝、氮化钨、铜、钨、铼、铱、钴、镍、其他合适的金属材料、或上述的组合。在多种实施例中，栅极结构254的栅极层的形成方法可为原子层沉积、物理气相沉积、化学气相沉积、电子束蒸镀、或其他合适工艺。此外，可分别形成n型场效晶体管与p型场效晶体管所用的栅极层，使其采用不同金属层(比如用于提供不同的n型功函数金属层与p型功函数金属层)。在多种实施例中，可进行化学机械研磨工艺以自栅极结构254的栅极层移除多余金属，进而提供栅极结构254的实质上平坦上表面。栅极结构254包括的部分夹设于通道区10中相邻的通道部件如外延层208之间。
步骤138的结果为第一晶体管300形成于工件200的第一区1000中，而第二晶体管400形成于工件200的第二区2000中。由于第一晶体管300与第二晶体管400的每一者包含垂直堆叠的通道部件如外延层208，第一晶体管300与第二晶体管400可为全绕式栅极晶体管。第一晶体管300与第二晶体管400可为相同导电型态或不同导电型态，端视设计需求而定。在一例中，第一区1000中的第一晶体管300为p型装置，而第二区2000中的第二晶体管400为n型装置。在进行步骤120以实施不同深度的第一区1000中的第一半导体氧化物结构2340与第二区2000中的第二半导体氧化物结构2350的实施例中，第一晶体管300与第二晶体管400可具有不同数目的有源/功能通道部件如外延层208。如图19所示，第一半导体氧化物结构2340与衬垫第一半导体氧化物结构2340的第一阻挡层230可一起视作第一底部介电结构2345，而第二半导体氧化物结构2350与衬垫第二半导体氧化物结构2350的第一阻挡层230可一起视作第二底部介电结构2355。在第一晶体管300中，第一底部介电结构2345可绝缘第一区1000中的最底部通道部件如外延层208与第一源极/漏极结构242，造成第一区1000中的最底部通道部件如外延层208非有源或无功能。在第二晶体管400中，第二底部介电结构2355不绝缘最底部的通道部件如外延层208与第二源极/漏极结构248。如此一来，第一晶体管300的有源通道部件如外延层208的数目，比第二晶体管400的有源通道部件如外延层208的数目少一个。在未实际图示于此的一些其他实施例中，步骤118形成的第一外延结构234的深度，使其未覆盖最底部的通道区如外延层208，因此可省略步骤120。在这些其他实施例中，半导体氧化物层与第一阻挡层230未覆盖第一区1000与第二区2000中的最底部的通道层，而最终的第一晶体管300与第二晶体管400具有相同数目的有源/功能通道部件。
本发明一或多个实施例有利于半导体装置与其形成方法，但不局限于此。举例来说，本发明实施例的半导体装置可包含底部介电结构位于源极/漏极结构之下。底部介电结构可绝缘源极/漏极结构与下方基板以避免闩锁。此外，底部介电结构可中断漏电流穿过通道区之下的抗击穿注入区的路径。此外，本发明实施例的方法可形成全绕式栅极晶体管，其于单一基板上可具有不同数目的通道部件数目。由于实施底部介电结构，可减少或省略分接单元、保护环、或其他避免闩锁的结构，以提供更多空间给功能装置。
本发明一实施例关于半导体装置。半导体装置包括有源区，包括通道区以及与通道区相邻的源极/漏极区；多个通道部件的垂直堆叠，位于通道区上；栅极结构，位于通道部件的垂直堆叠周围与之上；底部介电结构，位于源极/漏极区上；源极/漏极结构，位于底部介电结构上；以及锗层，位于底部介电结构与源极/漏极区之间。
在一些实施例中，底部介电结构包括硅锗氧化物结构夹设于两个介电间隔物结构之间。在一些实施方式中，两个介电间隔物结构包括氮化硅。在一些例子中，硅锗氧化物结构直接位于锗层上。在一些实施例中，通道部件的垂直堆叠部分地隔有多个内侧间隔物结构。在一些实施方式中，两个介电间隔物结构接触内侧间隔物结构的至少一者。在一些例子中，通道部件的垂直堆叠的最底部的通道部件接触底部介电结构。
本发明另一实施例关于半导体装置。半导体装置包括：基板，具有第一区与第二区；第一晶体管，位于第一区中；以及第二晶体管，位于第二区中。第一晶体管包括第一有源区，含有第一通道区以及与第一通道区相邻的第一源极/漏极区，通道部件的第一垂直堆叠，位于第一通道区上，第一栅极结构，位于通道部件的第一垂直堆叠周围与之上，第一底部介电结构，位于第一源极/漏极区上，第一源极/漏极结构，位于第一底部介电结构上，以及第一锗层，位于第一底部介电结构与第一源极/漏极区之间。第二晶体管包含第二有源区，含有第二通道区以及与第二通道区相邻的第二源极/漏极区，通道部件的第二垂直堆叠，位于第二通道区上，第二栅极结构，位于通道部件的第二垂直堆叠周围与之上，第二底部介电结构，位于第二源极/漏极区上，第二源极/漏极结构，位于第二底部介电结构上，以及第二锗层，位于第二底部介电结构与第二源极/漏极区之间。第一底部介电结构具有第一深度，第二底部介电结构具有第二深度，且第二深度小于第一深度。
在一些实施例中，第一有源区与第二有源区包括硅，第一底部介电结构包括第一硅锗氧化物结构夹设于两个第一介电间隔物结构之间。第二底部介电结构包括第二硅锗氧化物结构夹设于两个第二介电间隔物结构之间。在一些实施方式中，两个第一介电间隔物结构与两个第二介电间隔物结构包括氮化硅。在一些实施例中，第一硅锗氧化物结构直接位于第一锗层上，且第二硅锗氧化物结构直接位于第二锗层上。在一些实施方式中，通道部件的第一垂直堆叠部分地隔有多个第一内侧间隔物结构，且通道部件的第二垂直堆叠部分地隔有多个第二内侧间隔物结构。在一些例子中，通道部件的第一垂直堆叠的最底部的通道部件接触第一底部介电结构，而其中通道部件的第二垂直堆叠的最底部的通道部件不接触第二底部介电结构。
本发明又一实施例关于半导体装置的形成方法。方法包括形成含有交错的多个半导体层与多个牺牲层的堆叠于基板上；自堆叠形成鳍状结构；形成虚置栅极堆叠于鳍状结构上；沉积栅极间隔物层于虚置栅极堆叠上；形成源极/漏极凹陷以与虚置栅极堆叠相邻；选择性地部分蚀刻多个牺牲层，以形成多个内侧间隔物凹陷；形成多个内侧间隔物结构于内侧间隔物凹陷中；形成介电层于基板上；移除源极/漏极凹陷中的介电层的一部分，以露出基板的顶面表面；形成底部介电结构于顶面表面上的源极/漏极凹陷中；以及形成外延结构于底部介电结构上。
在一些实施例中，形成底部介电结构的步骤包括：外延沉积硅锗层于顶面表面上；以及退火硅锗层以形成硅锗氧化物结构。在一些实施方式中，硅锗层包括约55原子％至约80原子％之间的硅，与介于约20原子％至约45原子％之间的锗。在一些例子中，形成底部介电结构的步骤还包括在外延沉积硅锗层脂后拉回硅锗层。在一些实施例中，退火硅锗层的步骤还包括形成锗层于顶面表面与硅锗氧化物结构之间。在一些实施方式中，基板包括硅，半导体层包括硅，且牺牲层包括硅锗。在一些例子中，多个内侧间隔物结构包括氧化硅、碳氧化硅、或碳氮化硅，而介电层包括氮化硅。
上述实施例的特征有利于本技术领域中普通技术人员理解本发明。本技术领域中普通技术人员应理解可采用本发明作基础，设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中普通技术人员亦应理解，这些等效置换并未脱离本发明精神与范畴，并可在未脱离本发明的精神与范畴的前提下进行改变、替换、或更动。

Claims (1)

1.一种半导体装置，包括：
一有源区，包括一通道区以及与该通道区相邻的一源极/漏极区；
多个通道部件的一垂直堆叠，位于该通道区上；
一栅极结构，位于所述多个通道部件的该垂直堆叠周围与之上；
一底部介电结构，位于该源极/漏极区上；
一源极/漏极结构，位于该底部介电结构上；以及
一锗层，位于该底部介电结构与该源极/漏极区之间。
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